OSDN Git Service
Sam Kolton [Tue, 18 Jul 2017 14:23:26 +0000 (14:23 +0000)]
[AMDGPU] resubmit r308179: CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308310
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Simon Pilgrim [Tue, 18 Jul 2017 14:19:34 +0000 (14:19 +0000)]
[X86] Added cmov target to memcmp test
As discussed by @spatel on D35067:
"I added the cmov attribute to the 32-bit codegen test because it removes some noise for that file. I think the intent for the SSE vs no-SSE runs is to show the potential difference for the 16 and 32 byte cases rather than the lack of cmov (which has been available for all CPUs since SSE1, so that's why it shows up automatically with -mattr=sse2)."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308309
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Daniel Sanders [Tue, 18 Jul 2017 14:10:07 +0000 (14:10 +0000)]
[globalisel][tablegen] Enable the import of rules involving fma.
Summary:
G_FMA was recently added to GlobalISel which enables the import of rules
involving fma. Add the mapping to allow it.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Reviewed By: rovka
Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D35130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308308
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Hiroshi Inoue [Tue, 18 Jul 2017 13:31:40 +0000 (13:31 +0000)]
fix formatting issue; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308305
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Dmitry Preobrazhensky [Tue, 18 Jul 2017 13:12:48 +0000 (13:12 +0000)]
[AMDGPU][MC] Corrected disassembler for proper decoding of v_mqsad_u32_u8
See Bug 33639: https://bugs.llvm.org//show_bug.cgi?id=33639
Reviewers: vpykhtin, artem.tamazov
Differential Revision: https://reviews.llvm.org/D34892
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308303
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Simon Pilgrim [Tue, 18 Jul 2017 12:31:46 +0000 (12:31 +0000)]
[DAGCombine] Fix issue with out of bound constant rotation (PR33828)
Take the modulo of rotations by a constant greater than or equal to the bit-width
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308302
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Stefan Maksimovic [Tue, 18 Jul 2017 12:05:35 +0000 (12:05 +0000)]
[mips] Alter register classes for MSA pseudo f16 instructions
This change introduces additional machine instructions in functions
dealing with the expansion of msa pseudo f16 instructions due to
register classes being inappropriate when checked with machine
verifier.
Differential Revision: https://reviews.llvm.org/D34276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308301
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Dorit Nuzman [Tue, 18 Jul 2017 11:57:08 +0000 (11:57 +0000)]
PSCEV] Create AddRec for Phis in cases of possible integer overflow,
using runtime checks
Extend the SCEVPredicateRewriter to work a bit harder when it encounters an
UnknownSCEV for a Phi node; Try to build an AddRecurrence also for Phi nodes
whose update chain involves casts that can be ignored under the proper runtime
overflow test. This is one step towards addressing PR30654.
Differential revision: http://reviews.llvm.org/D30041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308299
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Alexander Potapenko [Tue, 18 Jul 2017 11:47:56 +0000 (11:47 +0000)]
[sancov] Fix PR33732
Coverage hooks that take less-than-64-bit-integers as parameters need the
zeroext parameter attribute (http://llvm.org/docs/LangRef.html#paramattrs)
to make sure they are properly extended by the x86_64 ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308296
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Simon Pilgrim [Tue, 18 Jul 2017 11:18:38 +0000 (11:18 +0000)]
[X86][AVX512] Add ISD::ROTL/ISD::ROTR constant folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308295
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Dmitry Preobrazhensky [Tue, 18 Jul 2017 11:14:02 +0000 (11:14 +0000)]
[AMDGPU][MC] Optimized IsRegIntersect function
Optimized IsRegIntersect by using MCRegAliasIterator
See Bug 33800: https://bugs.llvm.org//show_bug.cgi?id=33800
Reviewers: arsenm, artem.tamazov
Differential Revision: https://reviews.llvm.org/D35452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308294
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George Rimar [Tue, 18 Jul 2017 10:59:30 +0000 (10:59 +0000)]
[libOption] - Replace std::pair with helper struct. NFC.
Splitted from D35476.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308293
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Javed Absar [Tue, 18 Jul 2017 10:19:48 +0000 (10:19 +0000)]
[ARM|CodeGen] Improve the code in FastISel
Cleaned up the code in FastISel a bit.
Had to add make_range to MCInstrDesc as that was needed and seems missing.
Reviewed by: @t.p.northover
Differential Revision: https://reviews.llvm.org/D35494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308291
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Simon Pilgrim [Tue, 18 Jul 2017 10:09:40 +0000 (10:09 +0000)]
[X86] Add test case for PR32282
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308286
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Diana Picus [Tue, 18 Jul 2017 10:07:01 +0000 (10:07 +0000)]
[ARM] GlobalISel: Support G_(S|U)REM for s8 and s16
Widen to s32, and then do whatever Lowering/Custom/Libcall action the
subtarget wants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308285
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Florian Hahn [Tue, 18 Jul 2017 09:47:06 +0000 (09:47 +0000)]
[LoopInterchange] Split up interchange.ll test case (NFC).
Summary:
Currently most tests for the loop interchange pass are in
test/Transforms/LoopInterchange/interchange.ll. This patch splits up the
large test file in smaller pieces, which makes debugging test failures
easier.
Reviewers: karthikthecool, blitz.opensource, hfinkel
Reviewed By: hfinkel
Subscribers: hfinkel, mcrosier, mkuper, mzolotukhin, mssimpso, llvm-commits
Differential Revision: https://reviews.llvm.org/D35488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308284
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Florian Hahn [Tue, 18 Jul 2017 09:31:18 +0000 (09:31 +0000)]
[AArch64] Use 16 bytes as preferred function alignment on Cortex-A73.
Summary:
Using 16 byte alignment is beneficial on Cortex-A73, similar to
Cortex-A72 (added in D34961).
Reviewers: mcrosier, t.p.northover, aadg, silviu.baranga
Reviewed By: t.p.northover
Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D35493
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308283
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Dmitry Preobrazhensky [Tue, 18 Jul 2017 09:24:10 +0000 (09:24 +0000)]
[AMDGPU][MC] Added missing VOP3P opcodes
Added support of the following opcodes:
v_pk_sub_u16
v_pk_mad_i16
v_pk_mad_u16
See Bug 33593: https://bugs.llvm.org//show_bug.cgi?id=33593
Reviewers: vpykhtin, artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D34890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308281
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Jonas Paulsson [Tue, 18 Jul 2017 09:17:00 +0000 (09:17 +0000)]
[SystemZ, AsmParser] Enable the mnemonic spell corrector.
This enables the suggestions of other mnemonics when invalid ones are
specified.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308280
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Diana Picus [Tue, 18 Jul 2017 09:08:47 +0000 (09:08 +0000)]
GlobalISel: Support G_(S|U)REM widening in LegalizerHelper
Treat widening G_SREM and G_UREM the same as G_SDIV and G_UDIV. This is
going to be used in the ARM backend (and that's when the test will come
too).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308278
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NAKAMURA Takumi [Tue, 18 Jul 2017 08:52:02 +0000 (08:52 +0000)]
llvm/DebugInfo/CodeView/TypeStreamMerger.h: Prune a couple of \param(s), removed in r308212. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308276
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Serge Guelton [Tue, 18 Jul 2017 08:36:22 +0000 (08:36 +0000)]
Normalize constructor call syntax, NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308275
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Chandler Carruth [Tue, 18 Jul 2017 08:20:50 +0000 (08:20 +0000)]
Revert part of r308100 since the cause (r308025) was also reverted.
The commit r308100 updated WebAssembly tests for r308025. In one case it
merely made the test more resilient but in another case it made
a substantive update. Because r308025 was reverted in r308271, these
changes to the test also need to be reverted. They should be folded into
the recommit of r308025 when it is ready.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308273
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Chandler Carruth [Tue, 18 Jul 2017 08:16:32 +0000 (08:16 +0000)]
[x86] Add a missing triple, without which the CPU won't parse.
Notably, this is failing on our PPC build bots:
http://lab.llvm.org:8011/builders/clang-ppc64le-linux/builds/8338/steps/ninja%20check%201/logs/FAIL%3A%20LLVM%3A%3Apr33772.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308272
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Chandler Carruth [Tue, 18 Jul 2017 07:53:47 +0000 (07:53 +0000)]
Revert r308025 due to uncovering a crash in SelectionDAG. This is filed
with a minimal test case in http://llvm.org/PR33833.
Original commit message:
Improve Aliasing of operations to static alloca
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308271
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Chandler Carruth [Tue, 18 Jul 2017 07:40:47 +0000 (07:40 +0000)]
Revert r308179 which causes tablegen to spam stderr on every build.
Original commit log:
[AMDGPU] CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308270
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Craig Topper [Tue, 18 Jul 2017 06:49:23 +0000 (06:49 +0000)]
[X86] Prevent an assertion failure if a gather intrinsic is passed a non-constant scale value.
This isn't legal code, but we shouldn't crash on it. Now we just don't convert the gather intrinsic if the scale isn't constant and let it go through to isel where we'll report an isel failure.
Fixes PR33772.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308267
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Serguei Katkov [Tue, 18 Jul 2017 05:16:38 +0000 (05:16 +0000)]
[CGP] Cleanup - remove redundant code in OptimizeMemoryInst. NFC
optimizeMemoryInst contains a vector AddrModeInsts.
The only use of this vector is to check that all instructions are in the same
block as memory instruction. This check is guarded by PhiSeen flag,
so if we traversed through phi node then we do not need to keep information
in AddrModeInsts. AddModeInsts is set first time we found some addressing mode
and updated if we found new one later.
We can find next addressing mode only if we traverse phi node so all code
related to update of AddModeInsts can be safely removed.
Reviewers: loladiro, spatel, efriedma
Reviewed By: efriedma
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D35291
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308265
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Max Kazantsev [Tue, 18 Jul 2017 04:53:48 +0000 (04:53 +0000)]
[IRCE] Recognize loops with ne/eq latch conditions
In some particular cases eq/ne conditions can be turned into equivalent
slt/sgt conditions. This patch teaches parseLoopStructure to handle some
of these cases.
Differential Revision: https://reviews.llvm.org/D35010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308264
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Eric Beckmann [Tue, 18 Jul 2017 03:38:04 +0000 (03:38 +0000)]
Revert "Adding temporary debugging info to llvm-mt to solve fedora failure."
This reverts commit
223ef99f839f6b056272bcf4390841fcb26dda3c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308263
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Eric Beckmann [Tue, 18 Jul 2017 03:37:49 +0000 (03:37 +0000)]
Revert "Adding yet more debug info to fix fedora issue."
This reverts commit
f3aaaac609f801df6c12655ec203455be7094627.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308262
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Eric Beckmann [Tue, 18 Jul 2017 03:37:34 +0000 (03:37 +0000)]
Revert "Adding extra test info for llvm-mt."
This reverts commit
66093fd60b848572f676023b8387bff69b151511.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308261
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Craig Topper [Tue, 18 Jul 2017 02:41:12 +0000 (02:41 +0000)]
[Analysis] RemoveTotalMemInst counting in InstCount to avoid reading back other Statistic variables
Summary:
Previously, we counted TotalMemInst by reading certain instruction counters before and after calling visit and then finding the difference. But that wouldn't be thread safe if this same pass was being ran on multiple threads.
This list of "memory instructions" doesn't make sense to me as it includes call/invoke and is missing atomics.
This patch removes the counter all together.
Reviewers: hfinkel, chandlerc, davide
Reviewed By: davide
Subscribers: davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D33608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308260
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Eric Beckmann [Tue, 18 Jul 2017 02:18:19 +0000 (02:18 +0000)]
Change '?' to 'h' in llvm-mt test.
Some shells seem to have trouble parsing non-alphanumeric symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308259
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Kostya Serebryany [Tue, 18 Jul 2017 01:36:50 +0000 (01:36 +0000)]
[libFuzzer] improve -reduce_inputs=1: now only consider the unique features of very input (seems to work much better)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308253
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Eric Beckmann [Tue, 18 Jul 2017 01:13:10 +0000 (01:13 +0000)]
Adding extra test info for llvm-mt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308252
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Daniel Neilson [Tue, 18 Jul 2017 01:06:54 +0000 (01:06 +0000)]
Add element-atomic mem intrinsic canary tests for Memory Sanitizer.
Summary:
Add canary tests to verify that MSAN currently does nothing with the element atomic memory intrinsics for memcpy, memmove, and memset.
Placeholder tests that will fail once element atomic @llvm.mem[cpy|move|set] instrinsics have been added to the MemIntrinsic class hierarchy. These will act as a reminder to verify that MSAN handles these intrinsics properly once they have been added to that class hierarchy.
Reviewers: reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D35510
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308251
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Daniel Neilson [Tue, 18 Jul 2017 01:06:53 +0000 (01:06 +0000)]
Add element-atomic mem intrinsic canary tests for Efficiency Sanitizer.
Summary:
Add canary tests to verify that ESAN currently does nothing with the element atomic memory intrinsics for memcpy, memmove, and memset.
Placeholder tests that will fail once element atomic @llvm.mem[cpy|move|set] instrinsics have been added to the MemIntrinsic class hierarchy. These will act as a reminder to verify that ESAN handles these intrinsics properly once they have been added to that class hierarchy.
Reviewers: reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D35508
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308250
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Daniel Neilson [Tue, 18 Jul 2017 01:06:52 +0000 (01:06 +0000)]
Add element-atomic mem intrinsic canary tests for Dataflow Sanitizer.
Summary:
Add canary tests to verify that DFSAN currently does nothing with the element atomic memory intrinsics for memcpy, memmove, and memset.
Placeholder tests that will fail once @llvm.mem[cpy|move|set] instrinsics have been added to the MemIntrinsic class hierarchy. These will act as a reminder to verify that DFSAN handles these intrinsics properly once they have been added to that class hierarchy.
Note that there could be some trickiness with these element-atomic intrinsics for the dataflow sanitizer in racy multithreaded programs. The data flow sanitizer inserts additional lib calls to mirror the memory intrinsic's action, so it is possible (very likely, even) that the dfsan buffers will not be in sync with the original buffers. Furthermore, implementation of the dfsan buffer updates for the element atomic intrinsics will have to also use unordered atomic instructions. If we can assume that dfsan is never run on racy multithreaded programs, then the element atomic memory intrinsics can pretty much be treated the same as the regular memory intrinsics.
Reviewers: reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D35507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308249
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Daniel Neilson [Tue, 18 Jul 2017 01:06:52 +0000 (01:06 +0000)]
Add element-atomic mem intrinsic canary tests for Address Sanitizer.
Summary:
Add canary tests to verify that ASAN currently does nothing with the element atomic memory intrinsics for memcpy, memmove, and memset.
Placeholder tests that will fail once element atomic @llvm.mem[cpy|move|set] instrinsics have been added to the MemIntrinsic class hierarchy. These will act as a reminder to verify that ASAN handles these intrinsics properly once they have been added to that class hierarchy.
Reviewers: reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D35505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308248
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Daniel Neilson [Tue, 18 Jul 2017 01:06:47 +0000 (01:06 +0000)]
Add element-atomic mem intrinsic canary tests for InstCombine.
Summary:
Add canary tests to verify that InstCombine currently does nothing with the element atomic memory intrinsics for memmove and memset.
Placeholder tests that will fail once element atomic @llvm.mem[move|set] instrinsics have been added to the MemIntrinsic class hierarchy. These will act as a reminder to verify that inst combine handles these intrinsics properly once they have been added to that class hierarchy.
Reviewers: reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D35502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308247
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Kostya Serebryany [Tue, 18 Jul 2017 01:00:28 +0000 (01:00 +0000)]
[libFuzzer] disable fuzzer-flags.test on windows to fix the bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308246
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Spyridoula Gravani [Tue, 18 Jul 2017 01:00:26 +0000 (01:00 +0000)]
[DWARF] Modification of code for the verification of .debug_info section.
Summary:
This patch modifies the handleDebugInfo() function so that we verify the contents of each unit
in the .debug_info section only if its header has been successfully verified.
This change will allow for more/different verification checks depending on the type of the unit since from
dwarf5, the .debug_info section may consist of different types of units.
Subscribers: aprantl
Differential Revision: https://reviews.llvm.org/D35521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308245
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Reid Kleckner [Tue, 18 Jul 2017 00:44:10 +0000 (00:44 +0000)]
Fix pdbdump-headers.test after TPI hash changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308244
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Reid Kleckner [Tue, 18 Jul 2017 00:33:45 +0000 (00:33 +0000)]
[PDB] Finish and simplify TPI hashing
Summary:
This removes the CVTypeVisitor updater and verifier classes. They were
made dead by the minimal type dumping refactoring. Replace them with a
single function that takes a type record and produces a hash. Call this
from the minimal type dumper and compare the hash.
I also noticed that the microsoft-pdb reference repository uses a basic
CRC32 for records that aren't special. We already have an implementation
of that CRC ready to use, because it's used in COFF for ICF.
I'll make LLD call this hashing utility in a follow-up change. We might
also consider using this same hash in type stream merging, so that we
don't have to hash our records twice.
Reviewers: inglorion, ruiu
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D35515
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308240
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Reid Kleckner [Tue, 18 Jul 2017 00:21:25 +0000 (00:21 +0000)]
[PDB] Merge in types and items from type servers (/Zi)
Summary:
Object files compiled with /Zi emit type information into a type server
PDB. The .debug$S section will contain a single TypeServer2Record with
the absolute path and GUID of the type server. LLD needs to load the
type server PDB and merge all types and items it finds in it into the
destination PDB.
Depends on D35495
Reviewers: ruiu, inglorion
Subscribers: zturner, llvm-commits
Differential Revision: https://reviews.llvm.org/D35504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308235
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Reid Kleckner [Mon, 17 Jul 2017 23:59:44 +0000 (23:59 +0000)]
[codeview] Fix YAML for LF_TYPESERVER2 by hoisting PDB_UniqueId
Summary:
We were treating the GUIDs in TypeServer2Record as strings, and the
non-ASCII bytes in the GUID would not round-trip through YAML.
We already had the PDB_UniqueId type portably represent a Windows GUID,
but we need to hoist that up to the DebugInfo/CodeView library so that
we can use it in the TypeServer2Record as well as in PDB parsing code.
Reviewers: inglorion, amccarth
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D35495
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308234
91177308-0d34-0410-b5e6-
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Eric Beckmann [Mon, 17 Jul 2017 23:36:13 +0000 (23:36 +0000)]
Adding yet more debug info to fix fedora issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308232
91177308-0d34-0410-b5e6-
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Eric Beckmann [Mon, 17 Jul 2017 22:46:10 +0000 (22:46 +0000)]
Adding temporary debugging info to llvm-mt to solve fedora failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308227
91177308-0d34-0410-b5e6-
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Matt Arsenault [Mon, 17 Jul 2017 22:35:50 +0000 (22:35 +0000)]
AMDGPU: Annotate features from x work item/group IDs.
This wasn't necessary before since they are always enabled
for kernels, but this is necessary if they need to be
forwarded to a callable function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308226
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Eric Beckmann [Mon, 17 Jul 2017 21:35:12 +0000 (21:35 +0000)]
Create empty shell of llvm-mt.
Summary:
This is the first patch towards creating the llvm-mt tool for merging
Windows manifests. This is a reimplementation of mt.exe.
Reviewers: zturner, ruiu, rnk
Subscribers: llvm-commits, mgorny
Differential Revision: https://reviews.llvm.org/D35333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308224
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Mandeep Singh Grang [Mon, 17 Jul 2017 21:25:19 +0000 (21:25 +0000)]
[COFF, ARM64] Correct the data layout string for COFF ARM64 target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308223
91177308-0d34-0410-b5e6-
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Reid Kleckner [Mon, 17 Jul 2017 20:31:38 +0000 (20:31 +0000)]
[codeview] Don't use the type visitor to merge types
Summary:
This didn't do much to speed things up, but it implements a FIXME, and I
think it's a nice simplification. We don't need the record kind switch.
We're doing that ourselves.
Reviewers: ruiu, inglorion
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D35496
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308213
91177308-0d34-0410-b5e6-
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Reid Kleckner [Mon, 17 Jul 2017 20:28:06 +0000 (20:28 +0000)]
[codeview] Remove TypeServerHandler and PDBTypeServerHandler
Summary:
Instead of wiring these through the CVTypeVisitor interface, clients
should inspect the CVTypeArray before visiting it and potentially load
up the type server's TPI stream if they need it.
No tests relied on this functionality because LLD was the only client.
Reviewers: ruiu
Subscribers: mgorny, hiraditya, zturner, llvm-commits
Differential Revision: https://reviews.llvm.org/D35394
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308212
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Geoff Berry [Mon, 17 Jul 2017 20:19:05 +0000 (20:19 +0000)]
[AArch64][Falkor] Address some stylistic review comments. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308211
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Martin Storsjo [Mon, 17 Jul 2017 20:05:19 +0000 (20:05 +0000)]
[AArch64] Extend CallingConv::X86_64_Win64 to AArch64 as well
Rename the enum value from X86_64_Win64 to plain Win64.
The symbol exposed in the textual IR is changed from 'x86_64_win64cc'
to 'win64cc', but the numeric value is kept, keeping support for
old bitcode.
Differential Revision: https://reviews.llvm.org/D34474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308208
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Teresa Johnson [Mon, 17 Jul 2017 19:25:38 +0000 (19:25 +0000)]
Revert "Restore with fix "[ThinLTO] Ensure we always select the same function copy to import""
This reverts commit r308114 (and follow on fixes to test).
There is a linking failure in a ThinLTO bot:
http://green.lab.llvm.org/green/job/clang-stage2-configure-Rthinlto_build/3663/
(and undefined reference). It seems like it must be a second order
effect of the heuristic change I made, and may take some time to try
to reproduce locally and track down. Therefore, reverting for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308206
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Lang Hames [Mon, 17 Jul 2017 18:36:35 +0000 (18:36 +0000)]
[ORC] Remove extraneous else.
As suggested by Dave Blaikie in review on r307952. Thanks Dave!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308203
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George Karpenkov [Mon, 17 Jul 2017 18:18:03 +0000 (18:18 +0000)]
Revert "[libFuzzer] Add a dependency on symbolizer from libFuzzer tests"
This reverts commit
546e006a023cccd0fd32afd442ab992d3515d4b8.
Reverting until I can figure out llvm-symbolizer breakages on mac os.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308202
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Adam Nemet [Mon, 17 Jul 2017 18:00:41 +0000 (18:00 +0000)]
[opt-viewer] Accept directories that are searched for opt.yaml files
This allows to pass the build directory where all the opt.yaml files are
rather than find | xargs which may invoke opt-viewer multiple times producing
incomplete html output.
The patch generalizes the same functionality from opt-diff.
Differential Revision: https://reviews.llvm.org/D35491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308200
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Ulrich Weigand [Mon, 17 Jul 2017 17:44:20 +0000 (17:44 +0000)]
[SystemZ] Add support for IBM z14 processor (3/3)
This adds support for the new 128-bit vector float instructions of z14.
Note that these instructions actually only operate on the f128 type,
since only each 128-bit vector register can hold only one 128-bit
float value. However, this is still preferable to the legacy 128-bit
float instructions, since those operate on pairs of floating-point
registers (so we can hold at most 8 values in registers), while the
new instructions use single vector registers (so we hold up to 32
value in registers).
Adding support includes:
- Enabling the instructions for the assembler/disassembler.
- CodeGen for the instructions. This includes allocating the f128
type now to the VR128BitRegClass instead of FP128BitRegClass.
- Scheduler description support for the instructions.
Note that for a small number of operations, we have no new vector
instructions (like integer <-> 128-bit float conversions), and so
we use the legacy instruction and then reformat the operand
(i.e. copy between a pair of floating-point registers and a
vector register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308196
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Ulrich Weigand [Mon, 17 Jul 2017 17:42:48 +0000 (17:42 +0000)]
[SystemZ] Add support for IBM z14 processor (2/3)
This adds support for the new 32-bit vector float instructions of z14.
This includes:
- Enabling the instructions for the assembler/disassembler.
- CodeGen for the instructions, including new LLVM intrinsics.
- Scheduler description support for the instructions.
- Update to the vector cost function calculations.
In general, CodeGen support for the new v4f32 instructions closely
matches support for the existing v2f64 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308195
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Ulrich Weigand [Mon, 17 Jul 2017 17:41:11 +0000 (17:41 +0000)]
[SystemZ] Add support for IBM z14 processor (1/3)
This patch series adds support for the IBM z14 processor. This part includes:
- Basic support for the new processor and its features.
- Support for new instructions (except vector 32-bit float and 128-bit float).
- CodeGen for new instructions, including new LLVM intrinsics.
- Scheduler description for the new processor.
- Detection of z14 as host processor.
Support for the new 32-bit vector float and 128-bit vector float
instructions is provided by separate patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308194
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Mandeep Singh Grang [Mon, 17 Jul 2017 17:32:45 +0000 (17:32 +0000)]
[llvm] Remove redundant check-prefix=CHECK from tests. NFC.
Reviewers: t.p.northover, oren_ben_simhon, niravd, mcrosier
Reviewed By: oren_ben_simhon, mcrosier
Subscribers: nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D35466
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308193
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Krzysztof Parzyszek [Mon, 17 Jul 2017 15:45:45 +0000 (15:45 +0000)]
[Hexagon] Remove custom lowering of loads of v4i16
The target-independent lowering works fine, except concatenating 32-bit
words. Add a pattern to generate A2_combinew instead of 64-bit asl/or.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308186
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Nirav Dave [Mon, 17 Jul 2017 15:09:47 +0000 (15:09 +0000)]
Avoid store merge to f128 in context of noimpiccitfloat NFCI.
Prevent store merge from merging stores into an invalid 128-bit store
(realized as a f128 value in the context of the noimplicitfloat
attribute). Previously, such stores are immediately split back into
valid stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308184
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Simon Pilgrim [Mon, 17 Jul 2017 14:37:17 +0000 (14:37 +0000)]
[X86] Add LEA scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308180
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Sam Kolton [Mon, 17 Jul 2017 14:23:38 +0000 (14:23 +0000)]
[AMDGPU] CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions
Summary:
Previously, CodeGen checked first src operand type to determine if omod is supported by instruction. This isn't correct for some instructions: e.g. V_CMP_EQ_F32 has floating-point src operands but desn't support omod.
Changed .td files to check if dst operand instead of src operand.
Reviewers: arsenm, vpykhtin
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D35350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308179
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Simon Pilgrim [Mon, 17 Jul 2017 14:11:30 +0000 (14:11 +0000)]
[X86][AVX512] Add lowering of vXi32/vXi64 ISD::ROTL/ISD::ROTR
Add support for lowering to ISD::ROTL/ISD::ROTR, including rotate by immediate
Differential Revision: https://reviews.llvm.org/D35463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308177
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Simon Pilgrim [Mon, 17 Jul 2017 13:58:20 +0000 (13:58 +0000)]
Fixed line endings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308175
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Javed Absar [Mon, 17 Jul 2017 13:15:26 +0000 (13:15 +0000)]
[CodeGen] Add begin-end iterators to MachineInstr
Convert iteration over operands to range-loop.
Reviewed by: @rovka, @echristo
Differential Revision: https://reviews.llvm.org/D35419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308173
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Alex Bradbury [Mon, 17 Jul 2017 11:41:30 +0000 (11:41 +0000)]
[YAMLTraits] Add filename support to yaml::Input
Summary:
The current yaml::Input constructor takes a StringRef of data as its
first parameter, discarding any filename information that may have been
present when a YAML file was opened. Add an alterate yaml::Input
constructor that takes a MemoryBufferRef, which can have a filename
associated with it. This leads to clearer diagnostic messages.
Sponsored By: DARPA, AFRL
Reviewed By: arphaman
Differential Revision: https://reviews.llvm.org/D35398
Patch by: Jonathan Anderson (trombonehero)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308172
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Simon Pilgrim [Mon, 17 Jul 2017 10:35:51 +0000 (10:35 +0000)]
[X86][AVX] Fix typo in vector rotate tests
Was preventing rotate matching
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308171
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Simon Pilgrim [Mon, 17 Jul 2017 10:09:48 +0000 (10:09 +0000)]
[X86][AVX512] Add constant splat vector rotate tests for D35463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308169
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Simon Pilgrim [Mon, 17 Jul 2017 09:53:45 +0000 (09:53 +0000)]
[X86][AVX512] Regenerate shift tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308168
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Simon Pilgrim [Mon, 17 Jul 2017 09:35:03 +0000 (09:35 +0000)]
Remove unnecessary cast. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308166
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Craig Topper [Mon, 17 Jul 2017 05:16:16 +0000 (05:16 +0000)]
[X86] Use MSVC's __cpuidex intrinsic instead of inline assembly in getHostCPUName/getHostCPUFeatures for 32-bit builds too.
We're already using it in 64-bit builds because 64-bit MSVC doesn't support inline assembly.
As far as I know we were using inline assembly because at the time the code was added we had to support MSVC 2008 pre-SP1 while the intrinsic was added to MSVC in SP1. Now that we don't have to support that we should be able to just use the intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308163
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NAKAMURA Takumi [Mon, 17 Jul 2017 04:31:26 +0000 (04:31 +0000)]
Analysis/MemorySSA.cpp: Prune unused "llvm/Transforms/Scalar.h".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308162
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NAKAMURA Takumi [Mon, 17 Jul 2017 04:31:23 +0000 (04:31 +0000)]
IR/Core.cpp: Prune unused "llvm/Bitcode/BitcodeReader.h".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308161
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NAKAMURA Takumi [Mon, 17 Jul 2017 04:31:20 +0000 (04:31 +0000)]
Support/Path.cpp: Prune unused "llvm/BinaryFormat".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308160
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Mandeep Singh Grang [Mon, 17 Jul 2017 00:05:32 +0000 (00:05 +0000)]
[COFF, ARM64] Add initial relocation types
Reviewers: compnerd, ruiu, rnk
Reviewed By: compnerd
Subscribers: mstorsjo, aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308154
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Dylan McKay [Sun, 16 Jul 2017 23:33:50 +0000 (23:33 +0000)]
[AVR] Add/remove XFAILs to get the backend passing Generic CodeGen tests
A few tests have since been fixed, and a few since now fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308151
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Andrew Zhogin [Sun, 16 Jul 2017 23:11:45 +0000 (23:11 +0000)]
[DAGCombiner] Recognise vector rotations with non-splat constants
Fixes PR33691.
Differential revision: https://reviews.llvm.org/D35381
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308150
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Dylan McKay [Sun, 16 Jul 2017 22:31:07 +0000 (22:31 +0000)]
[AVR] Fix a typo in the tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308148
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Konstantin Zhuravlyov [Sun, 16 Jul 2017 19:38:47 +0000 (19:38 +0000)]
AMDGPU: Fix amdgpu-flat-work-group-size/amdgpu-waves-per-eu check
Differential Revision: https://reviews.llvm.org/D35433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308147
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Simon Pilgrim [Sun, 16 Jul 2017 19:26:49 +0000 (19:26 +0000)]
[X86][AVX512] Add 512-bit vector rotate tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308146
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Konstantin Zhuravlyov [Sun, 16 Jul 2017 19:24:08 +0000 (19:24 +0000)]
AMDGPU: Remove duplicate print outs from .AMDGPU.csdata
Differential Revision: https://reviews.llvm.org/D35428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308145
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Davide Italiano [Sun, 16 Jul 2017 18:56:30 +0000 (18:56 +0000)]
[InstCombine] Don't violate dominance when replacing instructions.
Differential Revision: https://reviews.llvm.org/D35376
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308144
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Simon Pilgrim [Sun, 16 Jul 2017 18:37:23 +0000 (18:37 +0000)]
Strip trailing whitespace. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308143
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Amjad Aboud [Sun, 16 Jul 2017 17:39:56 +0000 (17:39 +0000)]
[X86] X86::CMOV to Branch heuristic based optimization.
LLVM compiler recognizes opportunities to transform a branch into IR select instruction(s) - later it will be lowered into X86::CMOV instruction, assuming no other optimization eliminated the SelectInst.
However, it is not always profitable to emit X86::CMOV instruction. For example, branch is preferable over an X86::CMOV instruction when:
1. Branch is well predicted
2. Condition operand is expensive, compared to True-value and the False-value operands
In CodeGenPrepare pass there is a shallow optimization that tries to convert SelectInst into branch, but it is not enough.
This commit, implements machine optimization pass that converts X86::CMOV instruction(s) into branch, based on a conservative heuristic.
Differential Revision: https://reviews.llvm.org/D34769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308142
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Jakub Kuderski [Sun, 16 Jul 2017 17:29:19 +0000 (17:29 +0000)]
Apply explicit instantiation workaround to DominanceFrontier
This is a workaround for the same explicit instantiation bug
as in DominatorTreeBase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308141
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Jakub Kuderski [Sun, 16 Jul 2017 17:01:40 +0000 (17:01 +0000)]
[Dominators] Workaround explicit instantiation bug.
Some platforms have problems with emmiting constructors when class
templates get explicitly instantiated.
This patch fixes the bug reported in D35315 by replacing `= default`
with an empty constructor body.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308140
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Simon Pilgrim [Sun, 16 Jul 2017 14:34:18 +0000 (14:34 +0000)]
[X86] Add F16C scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308138
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Simon Pilgrim [Sun, 16 Jul 2017 14:22:39 +0000 (14:22 +0000)]
[X86] Add POPCNT scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308137
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Simon Pilgrim [Sun, 16 Jul 2017 14:09:15 +0000 (14:09 +0000)]
[X86] Add BMI2 scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308136
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Simon Pilgrim [Sun, 16 Jul 2017 13:59:44 +0000 (13:59 +0000)]
[X86] Add BMI1 scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308135
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Simon Pilgrim [Sun, 16 Jul 2017 13:40:44 +0000 (13:40 +0000)]
[X86] Add LZCNT scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308133
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Simon Pilgrim [Sun, 16 Jul 2017 12:06:06 +0000 (12:06 +0000)]
[X86][SSE4A] Add EXTRQ/INSERTQ values to BTVER2 scheduling model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308132
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Simon Pilgrim [Sun, 16 Jul 2017 11:43:16 +0000 (11:43 +0000)]
[X86][AVX] Regenerate tests with constant broadcast comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308131
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Simon Pilgrim [Sun, 16 Jul 2017 11:40:23 +0000 (11:40 +0000)]
[X86][AVX] Regenerate vector tzcnt tests with constant broadcast comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308130
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