OSDN Git Service
Sanjay Patel [Wed, 16 May 2018 22:20:33 +0000 (22:20 +0000)]
[ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332539
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 22:20:26 +0000 (22:20 +0000)]
[ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332538
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 22:20:11 +0000 (22:20 +0000)]
[ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332537
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 16 May 2018 22:14:29 +0000 (22:14 +0000)]
[X86][SNB] Remove unnecessary CVT InstRW overrides
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332536
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Clegg [Wed, 16 May 2018 22:13:18 +0000 (22:13 +0000)]
[WebAssembly] Remove unused headers in MCWasmObjectWriter
Differential Revision: https://reviews.llvm.org/D46969
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332535
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 21:57:57 +0000 (21:57 +0000)]
[AArch64] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332534
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 21:57:19 +0000 (21:57 +0000)]
[ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332533
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 21:57:00 +0000 (21:57 +0000)]
[ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332532
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Wed, 16 May 2018 21:45:39 +0000 (21:45 +0000)]
[InstCombine] Fix the signature of fgets_unlocked.
It returns a pointer, not an int. This miscompiles all code that uses
the return value of fgets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332531
91177308-0d34-0410-b5e6-
96231b3b80d8
JF Bastien [Wed, 16 May 2018 21:24:03 +0000 (21:24 +0000)]
[NFC] WebAssembly build fix
Summary:
r332305 added a use of llvm::wasm::toString in llvm::object::WasmSymbol::print,
which is in a header file. It also moves toString to BinaryFormat. This has the
unintended side-effect that any inclusion of Object/Wasm.h now relies on
toString, and needs to required_libraries = BinaryFormat. Thankfully most builds
don't fail with this because print just isn't used and gets eliminated, dropping
the required dependency in the process. Not all builds are so lucky.
Fix this issue by moving print to the corresponding .cpp file.
<rdar://problem/
40258137>
Reviewers: sbc100, ncw, paquette
Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D46977
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332530
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Wed, 16 May 2018 21:20:16 +0000 (21:20 +0000)]
[MachineOutliner] Don't outline instructions that modify SP.
This breaks the code which saves and restores LR, so we can't outline
without doing something more complicated for stack adjustment.
Found by inspection; we get lucky in most cases because getMemOpInfo
only handles STRWpost, not any other pre/post-increment forms. But it
hits a couple of artificial testcases in the tree.
Differential Revision: https://reviews.llvm.org/D46920
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332529
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 16 May 2018 21:13:56 +0000 (21:13 +0000)]
_WIN32 straggler I missed in r331127; no-op in practice
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332528
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Wed, 16 May 2018 21:02:43 +0000 (21:02 +0000)]
[Hexagon] Fix the order of operands when selecting QCAT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332526
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Wed, 16 May 2018 21:00:24 +0000 (21:00 +0000)]
[Hexagon] Mark HVX vector predicate bitwise ops as legal, add patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332525
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 16 May 2018 20:52:52 +0000 (20:52 +0000)]
[X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441)
As suggested by Fabian on PR37441, use PSHUFLW to extend shift amount types for use with PSRAD/PSRLD to reduce register pressure.
Some of this ideally would be done by combineTargetShuffle but its tricky to do as most of the shuffles are sharing inputs.
Differential Revision: https://reviews.llvm.org/D46959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332524
91177308-0d34-0410-b5e6-
96231b3b80d8
Konstantin Zhuravlyov [Wed, 16 May 2018 20:47:48 +0000 (20:47 +0000)]
AMDGPU : Recalculate SGPRs when trap handler is supported
Differential Revision: https://reviews.llvm.org/D29911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332523
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Wed, 16 May 2018 20:34:00 +0000 (20:34 +0000)]
Fix small grammar-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332522
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Wed, 16 May 2018 20:33:59 +0000 (20:33 +0000)]
Fix up a misleading format warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332521
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Clegg [Wed, 16 May 2018 20:09:05 +0000 (20:09 +0000)]
[WebAssembly] MC: Ensure that FUNCTION_OFFSET relocations are always against function symbols.
The getAtom() method wasn't doing what we needed in all cases. We want
the symbols for the function which defines that section. We can compute
this easily enough and we know that we have at most one function in each
section.
Once this lands I will revert rL331412 which is no longer needed.
Fixes PR37409
Differential Revision: https://reviews.llvm.org/D46970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332517
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Wed, 16 May 2018 19:49:01 +0000 (19:49 +0000)]
[MachineOutliner] Don't save/restore LR for tail calls.
The cost computation assumes we do this correctly, but the actual
lowering was wrong.
Differential Revision: https://reviews.llvm.org/D46923
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332514
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 16 May 2018 18:31:17 +0000 (18:31 +0000)]
[X86] Fix typo in instregex for CVTSI642SDrr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332510
91177308-0d34-0410-b5e6-
96231b3b80d8
Greg Clayton [Wed, 16 May 2018 18:25:51 +0000 (18:25 +0000)]
Fix llvm::sys::path::remove_dots() to return "." instead of an empty path.
Differential Revision: https://reviews.llvm.org/D46887
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332508
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 16 May 2018 18:16:01 +0000 (18:16 +0000)]
[Timers] TimerGroup: add constructor from StringMap<TimeRecord>
Summary:
This is needed for the continuation of D46504,
to be able to store the timings.
Reviewers: george.karpenkov, NoQ, alexfh, sbenza
Reviewed By: alexfh
Subscribers: llvm-commits, cfe-commits
Differential Revision: https://reviews.llvm.org/D46939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332506
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 16 May 2018 18:15:56 +0000 (18:15 +0000)]
[Timers] TimerGroup: make printJSONValues() method public
Summary:
This is needed for the continuation of D46504,
to be able to store the timings.
Reviewers: george.karpenkov, NoQ, alexfh, sbenza
Reviewed By: alexfh
Subscribers: llvm-commits, cfe-commits
Differential Revision: https://reviews.llvm.org/D46938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332505
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 16 May 2018 18:15:51 +0000 (18:15 +0000)]
[Timers] TimerGroup::printJSONValue(): print doubles with no precision loss
Summary:
Although this is not stricly required, i would very much prefer
not to have known random precision losses along the way.
Reviewers: george.karpenkov, NoQ, alexfh, sbenza
Reviewed By: george.karpenkov
Subscribers: llvm-commits, cfe-commits
Differential Revision: https://reviews.llvm.org/D46937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332504
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 16 May 2018 18:15:47 +0000 (18:15 +0000)]
[Timers] TimerGroup::printJSONValues(): print mem timer with .mem suffix
Summary: We have just used `.sys` suffix for the previous timer, this is clearly a typo
Reviewers: george.karpenkov, NoQ, alexfh, sbenza
Reviewed By: alexfh
Subscribers: llvm-commits, cfe-commits
Differential Revision: https://reviews.llvm.org/D46936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332503
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 17:58:50 +0000 (17:58 +0000)]
[x86] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we make those fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332501
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 17:58:08 +0000 (17:58 +0000)]
[x86] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we make those fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332500
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 17:57:35 +0000 (17:57 +0000)]
[x86] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we make those fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332499
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 16 May 2018 17:40:07 +0000 (17:40 +0000)]
[X86][AVX512DQ] Use packed instructions for scalar FP<->i64 conversions on 32-bit targets
As i64 types are not legal on 32-bit targets, insert these into a suitable zero vector and use the packed vXi64<->FP conversion instructions instead.
Fixes PR3163.
Differential Revision: https://reviews.llvm.org/D43441
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332498
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Wed, 16 May 2018 17:30:58 +0000 (17:30 +0000)]
[Debugify] Tighten up the test for -debugify-each, NFC
In post-commit review for r332416, Paul Robinson pointed out that the
test for -debugify-each is not checking what it needs to.
This commit tightens up the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332497
91177308-0d34-0410-b5e6-
96231b3b80d8
JF Bastien [Wed, 16 May 2018 17:25:35 +0000 (17:25 +0000)]
Signal handling should be signal-safe
Summary:
Before this patch, signal handling wasn't signal safe. This leads to real-world
crashes. It used ManagedStatic inside of signals, this can allocate and can lead
to unexpected state when a signal occurs during llvm_shutdown (because
llvm_shutdown destroys the ManagedStatic). It also used cl::opt without custom
backing storage. Some de-allocation was performed as well. Acquiring a lock in a
signal handler is also a great way to deadlock.
We can't just disable signals on llvm_shutdown because the signals might do
useful work during that shutdown. We also can't just disable llvm_shutdown for
programs (instead of library uses of clang) because we'd have to then mark the
pointers as not leaked and make sure all the ManagedStatic uses are OK to leak
and remain so.
Move all of the code to lock-free datastructures instead, and avoid having any
of them in an inconsistent state. I'm not trying to be fancy, I'm not using any
explicit memory order because this code isn't hot. The only purpose of the
atomics is to guarantee that a signal firing on the same or a different thread
doesn't see an inconsistent state and crash. In some cases we might miss some
state (for example, we might fail to delete a temporary file), but that's fine.
Note that I haven't touched any of the backtrace support despite it not
technically being totally signal-safe. When that code is called we know
something bad is up and we don't expect to continue execution, so calling
something that e.g. sets errno is the least of our problems.
A similar patch should be applied to lib/Support/Windows/Signals.inc, but that
can be done separately.
Fix r332428 which I reverted in r332429. I originally used double-wide CAS
because I was lazy, but some platforms use a runtime function for that which
thankfully failed to link (it would have been bad for signal handlers
otherwise). I use a separate flag to guard the data instead.
<rdar://problem/
28010281>
Reviewers: dexonsmith
Subscribers: steven_wu, llvm-commits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332496
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Davis [Wed, 16 May 2018 17:07:08 +0000 (17:07 +0000)]
[llvm-mca] Move the RegisterFile class into its own translation unit. NFC
Summary: This change will help us turn the DispatchUnit into its own stage.
Reviewers: andreadb, RKSimon, courbet
Reviewed By: andreadb, courbet
Subscribers: mgorny, tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D46916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332493
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Wed, 16 May 2018 16:48:20 +0000 (16:48 +0000)]
[DAG] Prune cycle check in store merge.
As part of merging stores we check that fusing the nodes does not
cause a cycle due to one candidate store being indirectly dependent on
another store (this may happen via chained memory copies). This is
done by searching if a store is a predecessor to another store's
value.
Prune the search at the candidate search's root node which is a
predecessor to all candidate stores. This reduces the
size of the subgraph searched in large basic blocks.
Reviewers: jyknight
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D46955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332490
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Wed, 16 May 2018 16:47:54 +0000 (16:47 +0000)]
[DAG] Defer merge store cycle checking to just before merge. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332489
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 16 May 2018 16:29:05 +0000 (16:29 +0000)]
Give shared modules in unittests the platform-native extension, make PipSqueak a MODULE
As far as I can tell from revision history, there's no good reason to call
these files .so instead of .dll in Windows, so use the normal extension.
Also change PipSquak from SHARED to MODULE -- it's never passed to
target_link_libraries() and only loaded via dlopen(), so MODULE is more
appropriate. This makes it possible to delete a workaround for SHARED ldflags
being not quite right as well.
No intended behavior change.
https://reviews.llvm.org/D46898
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332487
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 16:23:41 +0000 (16:23 +0000)]
[x86] add run with unsafe global param; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332486
91177308-0d34-0410-b5e6-
96231b3b80d8
Tony Tye [Wed, 16 May 2018 16:19:34 +0000 (16:19 +0000)]
[AMDGPU] Change llvm.debugtrap to be a debug breakpoint that can resume execution.
No longer require the queue pointer to be passed in in fixed SGPRs.
Differential Revision: https://reviews.llvm.org/D46769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332485
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 16:16:48 +0000 (16:16 +0000)]
[x86] add tests for DAG FP undef operands; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332484
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Wed, 16 May 2018 15:45:17 +0000 (15:45 +0000)]
[AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.
For regular SVE vector operands, this patch introduces a more
sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b).
For example:
add z0.s, z1.s, z2.b -> invalid element width
^_____^
mismatch
For the vector-with-shift/extend (e.g. z0.s, uxtw #2) this patch takes
a slightly different approach and instead returns a 'invalid operand'
if the element size is not as expected. This is because the diagnostics
are more specificied to suggest using the right shift/extend suffix. This
is a trade-off not to introduce more operand classes and still provide
useful diagnostics for LD1 and PRF instructions.
For example:
ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand
^________________^
mismatch
For gather prefetches, both 'z0.s' and 'z0.d' would be allowed:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
prfw #0, p0, [x0, z0.d] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Without this change, the diagnostic would unnecessarily suggest a
different element size:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Reviewers: SjoerdMeijer, aemerson, fhahn, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46688
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332483
91177308-0d34-0410-b5e6-
96231b3b80d8
Sirish Pande [Wed, 16 May 2018 15:36:52 +0000 (15:36 +0000)]
[AArch64] Gangup loads and stores for pairing.
Keep loads and stores together (target defines how many loads
and stores to gang up), such that it will help in pairing
and vectorization.
Differential Revision https://reviews.llvm.org/D46477
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332482
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 15:15:22 +0000 (15:15 +0000)]
[InstCombine] allow more binop (shuffle X), C transforms
The canonicalization was restricted to shuffle masks with
a 1-to-1 mapping to the constant vector, but that disqualifies
the common splat pattern. This is part of solving PR37463:
https://bugs.llvm.org/show_bug.cgi?id=37463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332479
91177308-0d34-0410-b5e6-
96231b3b80d8
Teresa Johnson [Wed, 16 May 2018 14:58:14 +0000 (14:58 +0000)]
[ThinLTO] Make llvm-lto module ID numbering consistent with linkers
The module ID numbering typically starts at 0 (in both the new and old
LTO APIs, used by linkers). Make llvm-lto consistent with that.
Split out of D46699.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332476
91177308-0d34-0410-b5e6-
96231b3b80d8
Teresa Johnson [Wed, 16 May 2018 14:56:02 +0000 (14:56 +0000)]
[ThinLTO] Add const qualifier to a couple of flag getter methods
Split these minor fixes out of D46699.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332475
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Wed, 16 May 2018 14:16:01 +0000 (14:16 +0000)]
[AArch64][SVE] Asm: Support for gather PRF prefetch instructions
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332472
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Wed, 16 May 2018 13:38:17 +0000 (13:38 +0000)]
[llvm-mca] Move definitions in FetchStage.cpp inside namespace mca. NFC
Also, get rid of a redundant include in FetchStage.h and FetchStage.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332468
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Pszeniczny [Wed, 16 May 2018 13:16:54 +0000 (13:16 +0000)]
[BasicAA] Fix handling of invariant group launders
Summary:
A recent patch ([[ https://reviews.llvm.org/rL331587 | rL331587 ]]) to Capture Tracking taught it that the `launder_invariant_group` intrinsic captures its argument only by returning it. Unfortunately, BasicAA still considered every call instruction as a possible escape source and hence concluded that the result of a `launder_invariant_group` call cannot alias any local non-escaping value. This led to [[ https://bugs.llvm.org/show_bug.cgi?id=37458 | bug 37458 ]].
This patch updates the relevant check for escape sources in BasicAA.
Reviewers: Prazek, kuhar, rsmith, hfinkel, sanjoy, xbolva00
Reviewed By: hfinkel, xbolva00
Subscribers: JDevlieghere, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D46900
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332466
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Dardis [Wed, 16 May 2018 12:44:27 +0000 (12:44 +0000)]
[mips] Simplify some of the predicate scopes for (negative) multiply add/sub instructions (NFCI)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332464
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Dardis [Wed, 16 May 2018 12:37:04 +0000 (12:37 +0000)]
[mips] Join existing scopes for DecoderNamespace (NFCI)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332462
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Wed, 16 May 2018 12:33:09 +0000 (12:33 +0000)]
[llvm-mca] Fix perf regression after r332390.
Revision 332390 introduced a FetchStage class in llvm-mca.
By design, FetchStage owns all the instructions in-flight in the OoO Backend.
Before this change, new instructions were added to a DenseMap indexed by
instruction id. The problem with using a DenseMap is that elements are not
ordered by key. This was causing a massive slow down in method
FetchStage::postExecute(), which searches for instructions retired that can be
deleted.
This patch replaces the DenseMap with a std::map ordered by instruction index.
At the end of every cycle, we search for the first instruction which is not
marked as "retired", and we remove all the previous instructions before it.
This works well because instructions are retired in-order.
Before this patch, a debug build of llvm-mca (on my Ryzen linux machine) took
~8.0 seconds to simulate 3000 iterations of a x86 dot-product (a `vmulps,
vpermilps, vaddps, vpermilps, vaddps` sequence). With this patch, it now takes
~0.8s to run all the 3000 iterations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332461
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Wed, 16 May 2018 11:49:15 +0000 (11:49 +0000)]
[llvm-exegesis] Fix unused variable warning in release mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332455
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 16 May 2018 11:47:30 +0000 (11:47 +0000)]
AMDGPU: Custom lower v4i16/v4f16 vector operations
Avoids stack access.
Also handle extract hi elt pattern from truncate + shift
to avoid a couple test regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332453
91177308-0d34-0410-b5e6-
96231b3b80d8
David Bolvansky [Wed, 16 May 2018 11:39:52 +0000 (11:39 +0000)]
[SimplifyLibcalls] Replace locked IO with unlocked IO
Summary: If file stream arg is not captured and source is fopen, we could replace IO calls by unlocked IO ("_unlocked" function variants) to gain better speed,
Reviewers: efriedma, RKSimon, spatel, sanjoy, hfinkel, majnemer, lebedev.ri, rja
Reviewed By: rja
Subscribers: rja, srhines, efriedma, lebedev.ri, llvm-commits
Differential Revision: https://reviews.llvm.org/D45736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332452
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 16 May 2018 10:53:45 +0000 (10:53 +0000)]
[X86] Split WriteCvtI2F/WriteCvtF2I into I<->F32 and I<->F64 scheduler classes
A lot of the models still have too many InstRW overrides for these new classes - this needs cleaning up but I wanted to get the classes in first
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332451
91177308-0d34-0410-b5e6-
96231b3b80d8
David Green [Wed, 16 May 2018 10:41:58 +0000 (10:41 +0000)]
[LoopUnroll] Split out simplify code after Unroll into a new function. NFC
So that it can be shared with other passes that may end up doing the same
thing.
Differential Revision: https://reviews.llvm.org/D45874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332450
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Wed, 16 May 2018 10:32:02 +0000 (10:32 +0000)]
[GlobalISel][IRTranslator] Split aggregates during IR translation.
We currently handle all aggregates by creating one large LLT, and letting the
legalizer deal with splitting them up. However using this approach means that
we can't support big endian code correctly.
This patch changes the way that the IRTranslator deals with aggregate values,
by splitting them up into their constituent element values. To do this, parts
of the translator need to be modified to deal with multiple VRegs for a single
Value.
A new Value to VReg mapper is introduced to help keep compile time under
control, currently there is no measurable impact on CTMark despite the extra
code being generated in some cases.
Patch is based on the original work of Tim Northover.
Differential Revision: https://reviews.llvm.org/D46018
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332449
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Wed, 16 May 2018 10:12:06 +0000 (10:12 +0000)]
[llvm-mca] Regenerate tests after r332381 and r332361. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332447
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Dardis [Wed, 16 May 2018 10:03:05 +0000 (10:03 +0000)]
[mips] Add support for isBranchOffsetInRange and use it for MipsLongBranch
Add support for this target hook, covering MIPS, microMIPS and MIPSR6, along
with some tests. Also add missing getOppositeBranchOpc() cases exposed by the
tests.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D46794
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332446
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Wed, 16 May 2018 09:50:04 +0000 (09:50 +0000)]
[llvm-exegesis] Add a flag to output analysis csv to a file.
Reviewers: gchatelet
Subscribers: llvm-commits, tschuett
Differential Revision: https://reviews.llvm.org/D46931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332445
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Smith [Wed, 16 May 2018 09:33:25 +0000 (09:33 +0000)]
[AArch64] Support "S" inline assembler constraint
This patch re-introduces the "S" inline assembler constraint. This matches
an absolute symbolic address or a label reference. The primary use case is
asm("adrp %0, %1\n\t"
"add %0, %0, :lo12:%1" : "=r"(addr) : "S"(&var));
I say re-introduces as it seems like "S" was implemented in the original
AArch64 backend, but it looks like it wasn't carried forward to the merged
backend. The original implementation had A and L modifiers that could be
used to print ":lo12:" to the string. It looks like gcc doesn't use these
and :lo12: is expected to be written in the inline assembly string so I've
not implemented A and L. Clang already supports the S modifier.
Fixes PR37180
Differential Revision: https://reviews.llvm.org/D46745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332444
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Wed, 16 May 2018 09:24:38 +0000 (09:24 +0000)]
[llvm-mca] Remove redundant includes in Stage.h.
This patch also makes Stage::isReady() a const method.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332443
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Wed, 16 May 2018 09:16:20 +0000 (09:16 +0000)]
[AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) load instructions.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46679
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332442
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Wed, 16 May 2018 09:10:04 +0000 (09:10 +0000)]
Fix unused variable warning in r332437.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332441
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexander Richardson [Wed, 16 May 2018 09:00:28 +0000 (09:00 +0000)]
Escape ]]> in xunit xml output
Summary:
This sequence ends the CDATA block so any characters after that are no
longer escaped. This can be fixed by replacing "]]>" with "]]]]><![CDATA[>".
Reviewers: cmatthews
Reviewed By: cmatthews
Differential Revision: https://reviews.llvm.org/D46886
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332440
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexander Richardson [Wed, 16 May 2018 08:58:26 +0000 (08:58 +0000)]
Emit a left-shift instead of a power-of-two multiply for jump-tables
Summary:
SelectionDAGLegalize::ExpandNode() inserts an ISD::MUL when lowering a
BR_JT opcode. While many backends optimize this multiply into a shift, e.g.
the MIPS backend currently always lowers this into a sequence of
load-immediate+multiply+mflo in MipsSETargetLowering::lowerMulDiv().
I initially changed the multiply to a shift in the MIPS backend but it
turns out that would not have handled the MIPSR6 case and was a lot more
code than doing it in LegalizeDAG.
I believe performing this simple optimization in LegalizeDAG instead of
each individual backend is the better solution since this also fixes other
backeds such as MSP430 which calls the multiply runtime function
__mspabi_mpyi without this patch.
Reviewers: sdardis, atanasyan, pftbest, asl
Reviewed By: sdardis
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45760
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332439
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Wed, 16 May 2018 08:47:21 +0000 (08:47 +0000)]
[llvm-exegesis] Analysis: Display sched class for instructions.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D46883
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332437
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 16 May 2018 08:23:47 +0000 (08:23 +0000)]
[X86][SSE] Fix tests for vector rotates by splat variable.
We weren't correctly splatting the offset shift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332435
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Wed, 16 May 2018 07:50:09 +0000 (07:50 +0000)]
[AArch64][SVE] Asm: Support for contiguous PRF prefetch instructions.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332433
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Wed, 16 May 2018 06:43:27 +0000 (06:43 +0000)]
[Unix] Indent ChangeStd{in,out}ToBinary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332432
91177308-0d34-0410-b5e6-
96231b3b80d8
Mikael Holmen [Wed, 16 May 2018 06:36:11 +0000 (06:36 +0000)]
Remove unused variable introduced in r332336
The unused variable caused a compilation warning:
../lib/Target/X86/X86ISelLowering.cpp:34614:17: error: unused variable 'SMax' [-Werror,-Wunused-variable]
if (SDValue SMax = MatchMinMax(SMin, ISD::SMAX, C1))
^
1 error generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332431
91177308-0d34-0410-b5e6-
96231b3b80d8
Shoaib Meenai [Wed, 16 May 2018 04:52:18 +0000 (04:52 +0000)]
[ObjCARC] Prevent code motion into a catchswitch
A catchswitch must be the only non-phi instruction in its basic block;
attempting to move a retain or release into a catchswitch basic block
will result in invalid IR. Explicitly mark a CFG hazard in this case to
prevent the code motion.
Differential Revision: https://reviews.llvm.org/D46482
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332430
91177308-0d34-0410-b5e6-
96231b3b80d8
JF Bastien [Wed, 16 May 2018 04:36:37 +0000 (04:36 +0000)]
Revert "Signal handling should be signal-safe"
Some bots don't have double-pointer width compare-and-exchange. Revert for now.q
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332429
91177308-0d34-0410-b5e6-
96231b3b80d8
JF Bastien [Wed, 16 May 2018 04:30:00 +0000 (04:30 +0000)]
Signal handling should be signal-safe
Summary:
Before this patch, signal handling wasn't signal safe. This leads to real-world
crashes. It used ManagedStatic inside of signals, this can allocate and can lead
to unexpected state when a signal occurs during llvm_shutdown (because
llvm_shutdown destroys the ManagedStatic). It also used cl::opt without custom
backing storage. Some de-allocation was performed as well. Acquiring a lock in a
signal handler is also a great way to deadlock.
We can't just disable signals on llvm_shutdown because the signals might do
useful work during that shutdown. We also can't just disable llvm_shutdown for
programs (instead of library uses of clang) because we'd have to then mark the
pointers as not leaked and make sure all the ManagedStatic uses are OK to leak
and remain so.
Move all of the code to lock-free datastructures instead, and avoid having any
of them in an inconsistent state. I'm not trying to be fancy, I'm not using any
explicit memory order because this code isn't hot. The only purpose of the
atomics is to guarantee that a signal firing on the same or a different thread
doesn't see an inconsistent state and crash. In some cases we might miss some
state (for example, we might fail to delete a temporary file), but that's fine.
Note that I haven't touched any of the backtrace support despite it not
technically being totally signal-safe. When that code is called we know
something bad is up and we don't expect to continue execution, so calling
something that e.g. sets errno is the least of our problems.
A similar patch should be applied to lib/Support/Windows/Signals.inc, but that
can be done separately.
<rdar://problem/
28010281>
Reviewers: dexonsmith
Subscribers: aheejin, llvm-commits
Differential Revision: https://reviews.llvm.org/D46858
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332428
91177308-0d34-0410-b5e6-
96231b3b80d8
Shiva Chen [Wed, 16 May 2018 02:57:26 +0000 (02:57 +0000)]
[DebugInfo] Only handle DBG_VALUE in InlineSpiller.
The instructions using registers should be DBG_VALUE and normal
instructions. Use isDebugValue() to filter out DBG_VALUE and add
an assert to ensure there is no other kind of debug instructions
using the registers.
Differential Revision: https://reviews.llvm.org/D46739
Patch by Hsiangkai Wang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332427
91177308-0d34-0410-b5e6-
96231b3b80d8
Evgeny Stupachenko [Wed, 16 May 2018 02:48:50 +0000 (02:48 +0000)]
Fix LSR compile time hang.
Summary:
Limit number of reassociations in GenerateReassociationsImpl.
Reviewers: qcolombet, mkazantsev
Differential Revision: https://reviews.llvm.org/D46039
From: Evgeny Stupachenko <evstupac@gmail.com>
<evgeny.v.stupachenko@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332426
91177308-0d34-0410-b5e6-
96231b3b80d8
Chris Matthews [Wed, 16 May 2018 00:37:00 +0000 (00:37 +0000)]
remove output xml incase it is leftover from another run
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332424
91177308-0d34-0410-b5e6-
96231b3b80d8
Chris Matthews [Wed, 16 May 2018 00:33:29 +0000 (00:33 +0000)]
Use not to catch unexpected pass as well as remove old test results
As per review feedback, make sure we rm temp files, and make the return
code checking for lit more specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332423
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Wed, 16 May 2018 00:21:47 +0000 (00:21 +0000)]
ARM: Remove unnecessary argument. NFCI.
IsLittleEndian is already a field of ARMAsmBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332420
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Wed, 16 May 2018 00:21:31 +0000 (00:21 +0000)]
ARM: Deduplicate code and remove unnecessary declaration. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332419
91177308-0d34-0410-b5e6-
96231b3b80d8
Anastasis Grammenos [Wed, 16 May 2018 00:11:52 +0000 (00:11 +0000)]
[Debugify] Fix test failing after r332416
I missed a test that needed an update.
Failing bot: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/30071
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332418
91177308-0d34-0410-b5e6-
96231b3b80d8
Anastasis Grammenos [Tue, 15 May 2018 23:38:05 +0000 (23:38 +0000)]
[Debugfiy] Print the pass name next to the result
CheckDebugify now prints the pass name right next to the result of the check.
Differential Revision: https://reviews.llvm.org/D46908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332416
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Tue, 15 May 2018 23:36:46 +0000 (23:36 +0000)]
[MachineOutliner] Add optsize markings to outlined functions.
It doesn't matter much this late in the pipeline, but one place that
does check for it is the function alignment code.
Differential Revision: https://reviews.llvm.org/D46373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332415
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 15 May 2018 22:11:51 +0000 (22:11 +0000)]
[X86][SSE] Add tests for vector rotates by splat variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332410
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Tue, 15 May 2018 22:07:51 +0000 (22:07 +0000)]
[AMDGPU] Fix handling of void types in isLegalAddressingMode
It is legal for the type passed to isLegalAddressingMode to be
unsized or, more specifically, VoidTy. In this case, we must
check the legality of load / stores for all legal types. Directly
trying to call getTypeStoreSize is incorrect, and leads to breakage
in e.g. Loop Strength Reduction. This change guards against that
behaviour.
Differential Revision: https://reviews.llvm.org/D40405
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332409
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 15 May 2018 22:00:37 +0000 (22:00 +0000)]
[InstCombine] fix binop (shuffle X), C --> shuffle (binop X, C') to check uses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332407
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Clegg [Tue, 15 May 2018 21:49:58 +0000 (21:49 +0000)]
[WebAssembly] Provide WasmFunction content offset information.
WasmObjectWriter mostly operates with function segments offsets that do
not include their size fields. WasmObjectFile needs to have and provide
this information to the lld to maintain proper
R_WEBASSEMBLY_FUNCTION_OFFSET_I32 relocations entries.
Patch by Yury Delendik
Differential Revision: https://reviews.llvm.org/D46763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332406
91177308-0d34-0410-b5e6-
96231b3b80d8
Marek Olsak [Tue, 15 May 2018 21:41:57 +0000 (21:41 +0000)]
AMDGPU: Add a missing test for the 128-bit local addr space option
This should have been pushed with:
"AMDGPU: enable 128-bit for local addr space under an option"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332404
91177308-0d34-0410-b5e6-
96231b3b80d8
Marek Olsak [Tue, 15 May 2018 21:41:55 +0000 (21:41 +0000)]
StructurizeCFG: fix inverting conditions
Author: Samuel Pitoiset
Without this patch, it appears to me that we are selecting
the wrong operand when inverting conditions. In the attached
test, it will select %tmp3 instead of %tmp4. To fix it, just
use 'A' as everywhere.
This fixes a regression introduced by
"[PatternMatch] define m_Not using m_Xor and cst_pred_ty"
https://reviews.llvm.org/D46351
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332403
91177308-0d34-0410-b5e6-
96231b3b80d8
Evgeniy Stepanov [Tue, 15 May 2018 21:28:25 +0000 (21:28 +0000)]
[msan] Instrument masked.store, masked.load intrinsics.
Summary: Instrument masked store/load intrinsics.
Reviewers: kcc
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D46785
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332402
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Tue, 15 May 2018 21:26:47 +0000 (21:26 +0000)]
Move helper classes into anonymous namespaces. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332400
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 15 May 2018 21:23:58 +0000 (21:23 +0000)]
[InstCombine] clean up code for binop-shuffle transforms; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332399
91177308-0d34-0410-b5e6-
96231b3b80d8
Jake Ehrlich [Tue, 15 May 2018 20:53:53 +0000 (20:53 +0000)]
[llvm-objcopy] Add --only-keep-debug as a noop
This option just keeps being a problem and really needs to be implemented
in some fashion. Implementing it properly requires some kind of
"replaceSectionReference" method because all the existing links need to be
maintained. The desired behavior is just for allocated sections to become
NOBITS but actually implementing that is rather tricky due to the current
design of llvm-objcopy. However converting allocated sections to NOBITS is
just an optimization and not something debuggers need. Debuggers can debug
a stripped executable and take an unstripped executable for that stripped
executable as input. Additionally allocated sections account for a very
small part of debug binaries so this optimization is quite small. I propose
that for the time being we implement this as a NOP so that people can use
llvm-objcopy where they need to, just in a sub-optimal way.
This option has already blocked a lot of people and its currently blocking me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332396
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Tue, 15 May 2018 20:41:12 +0000 (20:41 +0000)]
[AArch64] Improve single vector lane unscaled stores
When storing the 0th lane of a vector, use a simpler and usually more
efficient scalar store instead. In this case, also using the unscaled
offset.
Differential revision: https://reviews.llvm.org/D46762
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332394
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 15 May 2018 20:34:09 +0000 (20:34 +0000)]
[InstCombine] add more tests for binop-shuffle; NFC
The splat pattern is part of PR37463:
https://bugs.llvm.org/show_bug.cgi?id=37463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332393
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Tue, 15 May 2018 20:31:53 +0000 (20:31 +0000)]
[DAGCombine] Move load checks on store of loads into candidate
search. NFCI.
Migrate single-use and non-volatility, non-indexed requirements on
stores of immediate store values to candidate collection pass from
later stage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332392
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Tue, 15 May 2018 20:21:58 +0000 (20:21 +0000)]
Nios2: Unbreak build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332391
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Davis [Tue, 15 May 2018 20:21:04 +0000 (20:21 +0000)]
[llvm-mca] Introduce a pipeline Stage class and FetchStage.
Summary:
This is just an idea, really two ideas. I expect some push-back,
but I realize that posting a diff is the most comprehensive way to express
these concepts.
This patch introduces a Stage class which represents the
various stages of an instruction pipeline. As a start, I have created a simple
FetchStage that is based on existing logic for how MCA produces
instructions, but now encapsulated in a Stage. The idea should become more concrete
once we introduce additional stages. The idea being, that when a stage completes,
the next stage in the pipeline will be executed. Stages are chained together
as a singly linked list to closely model a real pipeline. For now there is only one stage,
so the stage-to-stage flow of instructions isn't immediately obvious.
Eventually, Stage will also handle event notifications, but that functionality
is not complete, and not destined for this patch. Ideally, an interested party
can register for notifications from a particular stage. Callbacks will be issued to
these listeners at various points in the execution of the stage.
For now, eventing functionality remains similar to what it has been in mca::Backend.
We will be building-up the Stage class as we move on, such as adding debug output.
This patch also removes the unique_ptr<Instruction> return value from
InstrBuilder::createInstruction. An Instruction pointer is still produced,
but now it's up to the caller to decide how that item should be managed post-allocation
(e.g., smart pointer). This allows the Fetch stage to create instructions and
manage the lifetime of those instructions as it wishes, and not have to be bound to any
specific managed pointer type. Other callers of createInstruction might have different
requirements, and thus can manage the pointer to fit their needs. Another idea would be to push the
ownership to the RCU.
Currently, the FetchStage will wrap the Instruction
pointer in a shared_ptr. This allows us to remove the Instruction container in
Backend, which was probably going to disappear, or move, at some point anyways.
Note that I did run these changes through valgrind, to make sure we are not leaking
memory. While the shared_ptr comes with some additional overhead it relieves us
from having to manage a list of generated instructions, and/or make lookup calls
to remove the instructions.
I realize that both the Stage class and the Instruction pointer management
(mentioned directly above) are separate but related ideas, and probably should
land as separate patches; I am happy to do that if either idea is decent.
The main reason these two ideas are together is that
Stage::execute() can mutate an InstRef. For the fetch stage, the InstRef is populated
as the primary action of that stage (execute()). I didn't want to change the Stage interface
to support the idea of generating an instruction. Ideally, instructions are to
be pushed through the pipeline. I didn't want to draw too much of a
specialization just for the fetch stage. Excuse the word-salad.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb
Subscribers: llvm-commits, mgorny, javed.absar, tschuett, gbedwell
Differential Revision: https://reviews.llvm.org/D46741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332390
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Tue, 15 May 2018 20:16:57 +0000 (20:16 +0000)]
[x86][eflags] Fix PR37431 by teaching the EFLAGS copy lowering to
specially handle SETB_C* pseudo instructions.
Summary:
While the logic here is somewhat similar to the arithmetic lowering, it
is different enough that it made sense to have its own function.
I actually tried a bunch of different optimizations here and none worked
well so I gave up and just always do the arithmetic based lowering.
Looking at code from the PR test case, we actually pessimize a bunch of
code when generating these. Because SETB_C* pseudo instructions clobber
EFLAGS, we end up creating a bunch of copies of EFLAGS to feed multiple
SETB_C* pseudos from a single set of EFLAGS. This in turn causes the
lowering code to ruin all the clever code generation that SETB_C* was
hoping to achieve. None of this is needed. Whenever we're generating
multiple SETB_C* instructions from a single set of EFLAGS we should
instead generate a single maximally wide one and extract subregs for all
the different desired widths. That would result in substantially better
code generation. But this patch doesn't attempt to address that.
The test case from the PR is included as well as more directed testing
of the specific lowering pattern used for these pseudos.
Reviewers: craig.topper
Subscribers: sanjoy, mcrosier, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D46799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332389
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Tue, 15 May 2018 20:08:15 +0000 (20:08 +0000)]
Use perfect forwarding to deduplicate code in unit test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332388
91177308-0d34-0410-b5e6-
96231b3b80d8
Konstantin Zhuravlyov [Tue, 15 May 2018 19:32:47 +0000 (19:32 +0000)]
AMDGPU: Fix v_dot{4, 8}* instruction encoding
Differential Revision: https://reviews.llvm.org/D46848
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332387
91177308-0d34-0410-b5e6-
96231b3b80d8