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Igor Breger [Wed, 13 Sep 2017 09:05:23 +0000 (09:05 +0000)]
[GlobalISel][X86] support G_FPEXT operation.
Summary: Support G_FPEXT operation. Selection done via TableGen'erated code.
Reviewers: zvi, guyblank, aymanmus, m_zuckerman
Reviewed By: zvi
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313135
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Uriel Korach [Wed, 13 Sep 2017 09:02:36 +0000 (09:02 +0000)]
[X86] [PATCH] [intrinsics] Lowering X86 ABS intrinsics to IR. (llvm)
This patch, together with a matching clang patch (https://reviews.llvm.org/D37694), implements the lowering of X86 ABS intrinsics to IR.
differential revision: https://reviews.llvm.org/D37693.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313134
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Mohammed Agabaria [Wed, 13 Sep 2017 09:00:27 +0000 (09:00 +0000)]
[X86] Adding X86 Processor Families
Adding x86 Processor families to initialize several uArch properties (based on the family)
This patch shows how gather cost can be initialized based on the proc. family
Differential Revision: https://reviews.llvm.org/D35348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313132
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Uriel Korach [Wed, 13 Sep 2017 08:33:55 +0000 (08:33 +0000)]
[X86] Add explicit mc-encoding checks to X86/viabs.ll. NFC.
Add explicit mc-encoding checks showing that the AVX512VL ABS intrinsics are actually mapped to EVEX encoding.
This is a pre-commit for a soon to come patch which will lower x86 target specific ABS intrinsics to IR.
Differential Revision: https://reviews.llvm.org/D37688
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313131
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Craig Topper [Wed, 13 Sep 2017 07:53:21 +0000 (07:53 +0000)]
[X86] Make sure we emit a SUBREG_TO_REG after the MOV32ri when creating a BEXTR64rr instruction from a shift/and pair.
Fixes PR34589.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313126
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Elena Demikhovsky [Wed, 13 Sep 2017 06:40:26 +0000 (06:40 +0000)]
[X86 CodeGen] Optimization of ZeroExtendLoad for v2i8 vector
Load with zero-extend and sign-extend from v2i8 to v2i32 is "Legal" since SSE4.1 and may be performed using PMOVZXBD , PMOVSXBD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313121
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Ayal Zaks [Wed, 13 Sep 2017 06:28:37 +0000 (06:28 +0000)]
[LV] Fix PR34523 - avoid generating redundant selects
When converting a PHI into a series of 'select' instructions to combine the
incoming values together according their edge masks, initialize the first
value to the incoming value In0 of the first predecessor, instead of
generating a redundant assignment 'select(Cond[0], In0, In0)'. The latter
fails when the Cond[0] mask is null, representing a full mask, which can
happen only when there's a single incoming value.
No functional changes intended nor expected other than surviving null Cond[0]'s.
This fix follows D35725, which introduced using null to represent full masks.
Differential Revision: https://reviews.llvm.org/D37619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313119
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Aditya Kumar [Wed, 13 Sep 2017 05:28:03 +0000 (05:28 +0000)]
[GVNHoist] Factor out reachability to search for anticipable instructions quickly
Factor out the reachability such that multiple queries to find reachability of values are fast. This is based on finding
the ANTIC points
in the CFG which do not change during hoisting. The ANTIC points are basically the dominance-frontiers in the inverse
graph. So we introduce a data structure (CHI nodes)
to keep track of values flowing out of a basic block. We only do this for values with multiple occurrences in the
function as they are the potential hoistable candidates.
This patch allows us to hoist instructions to a basic block with >2 successors, as well as deal with infinite loops in a
trivial way.
Relevant test cases are added to show the functionality as well as regression fixes from PR32821.
Regression from previous GVNHoist:
We do not hoist fully redundant expressions because fully redundant expressions are already handled by NewGVN
Differential Revision: https://reviews.llvm.org/D35918
Reviewers: dberlin, sebpop, gberry,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313116
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Petr Hosek [Wed, 13 Sep 2017 03:04:50 +0000 (03:04 +0000)]
[llvm-objcopy] Add e_machine validity check for reserved section indexes
As discussed on llvm-commits it was decided it would be best to check
e_machine before declaring that a reserved section index is valid. The
only special e_machine value that matters here is EM_HEXAGON. This
change adds a special check for EM_HEXAGON.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D37767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313114
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Craig Topper [Wed, 13 Sep 2017 02:29:59 +0000 (02:29 +0000)]
[X86] Use isUInt<32> to simplify some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313112
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Reid Kleckner [Wed, 13 Sep 2017 01:50:27 +0000 (01:50 +0000)]
Fix dwarfdump cmdline test on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313110
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Leslie Zhai [Wed, 13 Sep 2017 01:49:49 +0000 (01:49 +0000)]
[ARC] Prepare the implementation of relocation for LLD
Reviewers: ruiu, kparzysz, petecoup, rafael
Reviewed By: kparzysz
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313109
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Reid Kleckner [Wed, 13 Sep 2017 01:43:25 +0000 (01:43 +0000)]
[InstCombine] Add a flag to disable LowerDbgDeclare
Summary:
This should improve optimized debug info for address-taken variables at
the cost of inaccurate debug info in some situations.
We patched this into clang and deployed this change to Chromium
developers, and this significantly improved debuggability of optimized
code. The long-term solution to PR34136 seems more and more like it's
going to take a while, so I would like to commit this change under a
flag so that it can be used as a stop-gap measure.
This flag should really help so for C++ aggregates like std::string and
std::vector, which are typically address-taken, even after inlining, and
cannot be SROA-ed.
Reviewers: aprantl, dblaikie, probinson, dberlin
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D36596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313108
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Petr Hosek [Wed, 13 Sep 2017 01:18:06 +0000 (01:18 +0000)]
[Fuchsia] Magenta -> Zircon
Fuchsia's lowest API layer has been renamed from Magenta to Zircon.
In LLVM proper, this is only mentioned in comments.
Patch by Roland McGrath
Differential Revision: https://reviews.llvm.org/D37763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313105
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Derek Schuff [Wed, 13 Sep 2017 00:29:06 +0000 (00:29 +0000)]
[WebAssembly] Add sign extend instructions from atomics proposal
Select them from ISD::SIGN_EXTEND_INREG
Differential Revision: https://reviews.llvm.org/D37603
remove spurious change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313101
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Peter Collingbourne [Tue, 12 Sep 2017 23:40:19 +0000 (23:40 +0000)]
Add Linux target triple to hopefully fix Mac bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313093
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Zachary Turner [Tue, 12 Sep 2017 23:32:34 +0000 (23:32 +0000)]
Determine up front which projects are enabled.
Some projects need to add conditional dependencies on other projects.
compiler-rt is already doing this, and I attempted to add this to
debuginfo-tests when I ran into the ordering problem, that you can't
conditionally add a dependency unless that dependency's CMakeLists.txt
has already been run (which would allow you to say if (TARGET foo).
The solution to this seems to be to determine very early on the entire
set of projects which is enabled. This is complicated by the fact that
there are multiple ways to enable projects, and different tree layouts
(e.g. mono-repo, out of -tree, external, etc). This patch attempts to
centralize all of this into one place, and then updates compiler-rt to
demonstrate as a proof of concept how this can simplify code.
Differential Revision: https://reviews.llvm.org/D37637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313091
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Sanjay Patel [Tue, 12 Sep 2017 23:28:11 +0000 (23:28 +0000)]
[SimplifyCFG] update test comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313090
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Sanjay Patel [Tue, 12 Sep 2017 23:24:05 +0000 (23:24 +0000)]
[x86] eliminate unnecessary vector compare for AVX masked store
The masked store instruction only cares about the sign-bit of each mask element,
so the compare s<0 isn't needed.
As noted in PR11210:
https://bugs.llvm.org/show_bug.cgi?id=11210
...fixing this should allow us to eliminate x86-specific masked store intrinsics in IR.
(Although more testing will be needed to confirm that.)
I filed a bug to track improvements for AVX512:
https://bugs.llvm.org/show_bug.cgi?id=34584
Differential Revision: https://reviews.llvm.org/D37446
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313089
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Adrian Prantl [Tue, 12 Sep 2017 22:32:53 +0000 (22:32 +0000)]
Clean up the --help output of llvm-dwarfdump by hiding irrelevant options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313085
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Dehao Chen [Tue, 12 Sep 2017 21:55:55 +0000 (21:55 +0000)]
Refactor the code to pass down ACT to SampleProfileLoader correctly.
Summary: This change passes down ACT to SampleProfileLoader for the new PM. Also remove the default value for SampleProfileLoader class as it is not used.
Reviewers: eraman, davidxl
Reviewed By: eraman
Subscribers: sanjoy, llvm-commits
Differential Revision: https://reviews.llvm.org/D37773
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313080
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Peter Collingbourne [Tue, 12 Sep 2017 21:50:55 +0000 (21:50 +0000)]
Remove -generate-dwarf-pub-sections flag.
This flag is unnecessary for testing because we can get the coverage
we need by adjusting CU attributes.
Differential Revision: https://reviews.llvm.org/D37725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313079
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Peter Collingbourne [Tue, 12 Sep 2017 21:50:41 +0000 (21:50 +0000)]
IR: Represent -ggnu-pubnames with a flag on the DICompileUnit.
This allows the flag to be persisted through to LTO.
Differential Revision: https://reviews.llvm.org/D37655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313078
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Petar Jovanovic [Tue, 12 Sep 2017 21:43:33 +0000 (21:43 +0000)]
[mips] handle UImm16_AltRelaxed match type
Currently, UImm16_AltRelaxed match type is not handled in
MatchAndEmitInstruction() function, which may result in
llvm_unreachable() behavior.
This patch adds necessary case for this match type.
Patch by Aleksandar Beserminji.
Differential Revision: https://reviews.llvm.org/D37682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313077
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Alina Sbirlea [Tue, 12 Sep 2017 21:18:44 +0000 (21:18 +0000)]
Make promoteLoopAccessesToScalars independent of AliasSet [NFC]
Summary:
The current promoteLoopAccessesToScalars method receives an AliasSet, but
the information used is in fact a list of Value*, known to must alias.
Create the list ahead of time to make this method independent of the AliasSet class.
While there is no functionality change, this adds overhead for creating
a set of Value*, when promotion would normally exit earlier.
This is meant to be as a first refactoring step in order to start replacing
AliasSetTracker with MemorySSA.
And while the end goal is to redesign LICM, the first few steps will focus on
adding MemorySSA as an alternative to the AliasSetTracker using most of the
existing functionality.
Reviewers: mkuper, danielcdh, dberlin
Subscribers: sanjoy, chandlerc, gberry, davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D35439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313075
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Ahmed Bougacha [Tue, 12 Sep 2017 21:04:11 +0000 (21:04 +0000)]
[AArch64][GlobalISel] Select all fpexts.
Tablegen already can select these: mark them as legal, remove the
c++ code, and add tests for all types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313074
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Ahmed Bougacha [Tue, 12 Sep 2017 21:04:10 +0000 (21:04 +0000)]
[AArch64][GlobalISel] Select all fptruncs.
We already support these in tablegen, but we're matching the wrong
operator (libm ftrunc). Fix that.
While there, drop the c++ code, support COPYs of FPR16, and add tests
for the other types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313073
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Roman Lebedev [Tue, 12 Sep 2017 18:59:21 +0000 (18:59 +0000)]
[sancov] coverage-report-server.py: ServerHandler(): open file as UTF8
Summary:
This is nessesary in Python3. Everywhere else we assume that
encoding is UTF8. If we don't specify it here, the defaults
from the environment will be used, which may result in ASCII
decoder being used. And if the file is non-ASCII, then it
will crash:
```
File "/usr/local/bin/coverage-report-server.py", line 168, in do_GET
for line_no, line in enumerate(f, start=1)])
File "/usr/local/bin/coverage-report-server.py", line 165, in <listcomp>
["<span class='{cls}'>{line} </span>".format(
File "/usr/lib/python3.5/encodings/ascii.py", line 26, in decode
return codecs.ascii_decode(input, self.errors)[0]
UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position 106: ordinal not in range(128)
```
Fixes https://bugs.llvm.org/show_bug.cgi?id=33548
Now, how would i add a testcase here?
Reviewers: m.ostapenko, kcc
Reviewed By: kcc
Subscribers: kcc, llvm-commits
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D37661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313063
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Lei Huang [Tue, 12 Sep 2017 18:39:11 +0000 (18:39 +0000)]
Update branch coalescing to be a PowerPC specific pass
Implementing this pass as a PowerPC specific pass. Branch coalescing utilizes
the analyzeBranch method which currently does not include any implicit operands.
This is not an issue on PPC but must be handled on other targets.
Pass is currently off by default. Enabled via -enable-ppc-branch-coalesce.
Differential Revision : https: // reviews.llvm.org/D32776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313061
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Sam Clegg [Tue, 12 Sep 2017 18:31:24 +0000 (18:31 +0000)]
[WebAssembly] Remove flags from MCSectionWasm
Looks like these were copied from the ELF sections but
don't apply to Wasm and were not used anywhere.
Also remove unused Wasm methods in MCContext.
Differential Revision: https://reviews.llvm.org/D37633
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313058
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Robert Lougher [Tue, 12 Sep 2017 18:23:15 +0000 (18:23 +0000)]
Revert "[DWARF] Incorrect prologue end line record."
This reverts commit r313047 as it is causing buildbot failure (lldb inline
stepping tests).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313057
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Yonghong Song [Tue, 12 Sep 2017 17:55:23 +0000 (17:55 +0000)]
bpf: Add BPF AsmParser support in LLVM
Reviewed-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313055
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Craig Topper [Tue, 12 Sep 2017 17:40:25 +0000 (17:40 +0000)]
[X86] Move matching of (and (srl/sra, C), (1<<C) - 1) to BEXTR/BEXTRI instruction to custom isel
Recognizing this pattern during DAG combine hides information about the 'and' and the shift from other combines. I think it should be recognized at isel so its as late as possible. But it can't be done with table based isel because you need to be able to look at both immediates. This patch moves it to custom isel in X86ISelDAGToDAG.cpp.
This does break a couple tests in tbm_patterns because we are now emitting an and_flag node or (cmp and, 0) that we dont' recognize yet. We already had this problem for several other TBM patterns so I think this fine and we can address of them together.
I've also fixed a bug where the combine to BEXTR was preventing us from using a trick of zero extending AH to handle extracts of bits 15:8. We might still want to use BEXTR if it enables load folding. But honestly I hope we narrowed the load instead before got to isel.
I think we should probably also support matching BEXTR from (srl/srl (and mask << C), C). But that should be a different patch.
Differential Revision: https://reviews.llvm.org/D37592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313054
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Elena Demikhovsky [Tue, 12 Sep 2017 17:27:53 +0000 (17:27 +0000)]
Added "zext" from v2i8 to v2i32. In the next patch I'll optimize the sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313052
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Robert Lougher [Tue, 12 Sep 2017 16:35:25 +0000 (16:35 +0000)]
[DWARF] Incorrect prologue end line record.
A prologue-end line record is emitted with an incorrect associated address,
which causes a debugger to show the beginning of function body to be inside
the prologue.
Patch written by Carlos Alberto Enciso.
Differential Revision: https://reviews.llvm.org/D37625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313047
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Anna Thomas [Tue, 12 Sep 2017 16:32:45 +0000 (16:32 +0000)]
[LV] Clamp the VF to the trip count
Summary:
When the MaxVectorSize > ConstantTripCount, we should just clamp the
vectorization factor to be the ConstantTripCount.
This vectorizes loops where the TinyTripCountThreshold >= TripCount < MaxVF.
Earlier we were finding the maximum vector width, which could be greater than
the trip count itself. The Loop vectorizer does all the work for generating a
vectorizable loop, but in the end we would always choose the scalar loop (since
the VF > trip count). This allows us to choose the VF keeping in mind the trip
count if available.
This is a fix on top of rL312472.
Reviewers: Ayal, zvi, hfinkel, dneilson
Reviewed by: Ayal
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313046
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Hans Wennborg [Tue, 12 Sep 2017 16:24:17 +0000 (16:24 +0000)]
Revert r313009 "[ARM] Use ADDCARRY / SUBCARRY"
This was causing PR34045 to fire again.
> This is a preparatory step for D34515 and also is being recommitted as its
> first version caused PR34045.
>
> This change:
> - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32
> - lowering is done by first converting the boolean value into the carry flag
> using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value
> using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two
> operations does the actual addition.
> - for subtraction, given that ISD::SUBCARRY second result is actually a
> borrow, we need to invert the value of the second operand and result before
> and after using ARMISD::SUBE. We need to invert the carry result of
> ARMISD::SUBE to preserve the semantics.
> - given that the generic combiner may lower ISD::ADDCARRY and
> ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering
> as well otherwise i64 operations now would require branches. This implies
> updating the corresponding test for unsigned.
> - add new combiner to remove the redundant conversions from/to carry flags
> to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C
> - fixes PR34045
>
> Differential Revision: https://reviews.llvm.org/D35192
Also revert follow-up r313010:
> [ARM] Fix typo when creating ISD::SUB nodes
>
> In D35192, I accidentally introduced a typo when creating ISD::SUB nodes,
> giving them two values instead of one.
>
> This fails when the merge_values combiner finds one of these nodes.
>
> This change fixes PR34564.
>
> Differential Revision: https://reviews.llvm.org/D37690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313044
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Alexey Bataev [Tue, 12 Sep 2017 16:15:04 +0000 (16:15 +0000)]
[SLP] Test with mutiple uses of conditional op and wrong parent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313042
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Adrian Prantl [Tue, 12 Sep 2017 16:10:24 +0000 (16:10 +0000)]
Statically assert that enum items don't overflow storage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313041
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Simon Pilgrim [Tue, 12 Sep 2017 15:52:01 +0000 (15:52 +0000)]
[X86][AVX2] Add gather/movntdqa/pmaskmov/pmovmskb/pslldq/psrldq instructions to scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313039
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Krzysztof Parzyszek [Tue, 12 Sep 2017 15:47:31 +0000 (15:47 +0000)]
Remove ancient, commented out code from TableGen, NFC
These pieces were commented out in r98534 and r129691, i.e. 6+ years ago.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313038
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Krzysztof Parzyszek [Tue, 12 Sep 2017 15:31:26 +0000 (15:31 +0000)]
Formatting changes, add LLVM_DUMP_METHOD to a dump function, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313037
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Sanjay Patel [Tue, 12 Sep 2017 15:29:28 +0000 (15:29 +0000)]
[InstCombine] move related tests together; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313036
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Alexey Bataev [Tue, 12 Sep 2017 15:13:50 +0000 (15:13 +0000)]
[SLP] Fix for PHINode during horizontal reduction scanning, NFC.
Reduces number of loops during instructions analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313035
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Simon Pilgrim [Tue, 12 Sep 2017 15:01:20 +0000 (15:01 +0000)]
[X86][AVX2] Add further instructions to scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313032
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Krzysztof Parzyszek [Tue, 12 Sep 2017 14:10:48 +0000 (14:10 +0000)]
Fix a couple of comments, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313030
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Simon Pilgrim [Tue, 12 Sep 2017 12:59:20 +0000 (12:59 +0000)]
[X86][AVX2] Add integer broadcast scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313026
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Jonas Paulsson [Tue, 12 Sep 2017 12:11:29 +0000 (12:11 +0000)]
[SystemZ] Add the CoveredBySubRegs bit to GPR64, GPR128 and FPR128 registers.
This bit is needed in order for the CalleeSavedRegs list to automatically
include the super registers if all of their subregs are present.
Thanks to Wei Mi for initially indicating this deficiency in the SystemZ
backend.
Review: Ulrich Weigand.
https://bugs.llvm.org/show_bug.cgi?id=34550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313023
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Simon Pilgrim [Tue, 12 Sep 2017 11:17:01 +0000 (11:17 +0000)]
[X86][AVX2] Add additional fp-broadcast/subvector/shuffle scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313022
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Simon Pilgrim [Tue, 12 Sep 2017 11:10:59 +0000 (11:10 +0000)]
[X86][AVX] Add vperm2f128 scheduling test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313021
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Simon Pilgrim [Tue, 12 Sep 2017 11:09:30 +0000 (11:09 +0000)]
[X86][AVX2] Remove old (unused) intrinsic declarations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313020
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Sjoerd Meijer [Tue, 12 Sep 2017 10:24:12 +0000 (10:24 +0000)]
[AArch64] ISel: Add some debug messages to LowerBUILDVECTOR. NFC.
Differential Revision: https://reviews.llvm.org/D37676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313017
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Yael Tsafrir [Tue, 12 Sep 2017 07:50:35 +0000 (07:50 +0000)]
[X86] Lower _mm[256|512]_[mask[z]]_avg_epu[8|16] intrinsics to native llvm IR
Differential Revision: https://reviews.llvm.org/D37560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313013
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Silviu Baranga [Tue, 12 Sep 2017 07:48:22 +0000 (07:48 +0000)]
[LAA] Allow more run-time alias checks by coercing pointer expressions to AddRecExprs
Summary:
LAA can only emit run-time alias checks for pointers with affine AddRec
SCEV expressions. However, non-AddRecExprs can be now be converted to
affine AddRecExprs using SCEV predicates.
This change tries to add the minimal set of SCEV predicates in order
to enable run-time alias checking.
Reviewers: anemet, mzolotukhin, mkuper, sanjoy, hfinkel
Reviewed By: hfinkel
Subscribers: mssimpso, Ayal, dorit, roman.shirokiy, mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D17080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313012
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Roger Ferrer Ibanez [Tue, 12 Sep 2017 07:42:28 +0000 (07:42 +0000)]
[ARM] Fix typo when creating ISD::SUB nodes
In D35192, I accidentally introduced a typo when creating ISD::SUB nodes,
giving them two values instead of one.
This fails when the merge_values combiner finds one of these nodes.
This change fixes PR34564.
Differential Revision: https://reviews.llvm.org/D37690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313010
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Roger Ferrer Ibanez [Tue, 12 Sep 2017 07:40:09 +0000 (07:40 +0000)]
[ARM] Use ADDCARRY / SUBCARRY
This is a preparatory step for D34515 and also is being recommitted as its
first version caused PR34045.
This change:
- makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32
- lowering is done by first converting the boolean value into the carry flag
using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value
using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two
operations does the actual addition.
- for subtraction, given that ISD::SUBCARRY second result is actually a
borrow, we need to invert the value of the second operand and result before
and after using ARMISD::SUBE. We need to invert the carry result of
ARMISD::SUBE to preserve the semantics.
- given that the generic combiner may lower ISD::ADDCARRY and
ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering
as well otherwise i64 operations now would require branches. This implies
updating the corresponding test for unsigned.
- add new combiner to remove the redundant conversions from/to carry flags
to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C
- fixes PR34045
Differential Revision: https://reviews.llvm.org/D35192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313009
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Craig Topper [Tue, 12 Sep 2017 03:50:44 +0000 (03:50 +0000)]
[X86] Add an extra instruction to TruncAssertSext.ll to prevent the 'or' from being narrowed so that the movl is really required to avoid a miscompile.
If we allow the OR to be narrowed then the upper bits really are zero and we can't tell if the zeroing movl was removed on purpose.
While here regenerate the test with update_llc_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312995
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Vlad Tsyrklevich [Tue, 12 Sep 2017 02:27:39 +0000 (02:27 +0000)]
Remove unneccessary string copies from method invocations.
Summary:
Change string parameter 'File' to be passed by const-reference to
reduce copies.
Patch by Mitch Phillips
Reviewers: vlad.tsyrklevich
Reviewed By: vlad.tsyrklevich
Subscribers: Eugene.Zelenko, llvm-commits
Differential Revision: https://reviews.llvm.org/D37652
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312994
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Craig Topper [Tue, 12 Sep 2017 01:30:10 +0000 (01:30 +0000)]
[X86] Rename TruncAssertZext.ll test to TruncAssertSext.ll. Since its testing AssertSext.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312991
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Craig Topper [Tue, 12 Sep 2017 01:30:09 +0000 (01:30 +0000)]
[X86] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312990
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Adrian Prantl [Tue, 12 Sep 2017 01:20:29 +0000 (01:20 +0000)]
Update testcases that are XFAILed on Darwin for llvm-dwarfdump changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312988
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Vlad Tsyrklevich [Tue, 12 Sep 2017 00:19:11 +0000 (00:19 +0000)]
Fix broken links to the Itanium CXX ABI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312985
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Hans Wennborg [Mon, 11 Sep 2017 23:52:02 +0000 (23:52 +0000)]
Revert r312898 "[ARM] Use ADDCARRY / SUBCARRY"
It caused PR34564.
> This is a preparatory step for D34515 and also is being recommitted as its
> first version caused PR34045.
>
> This change:
> - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32
> - lowering is done by first converting the boolean value into the carry flag
> using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value
> using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two
> operations does the actual addition.
> - for subtraction, given that ISD::SUBCARRY second result is actually a
> borrow, we need to invert the value of the second operand and result before
> and after using ARMISD::SUBE. We need to invert the carry result of
> ARMISD::SUBE to preserve the semantics.
> - given that the generic combiner may lower ISD::ADDCARRY and
> ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering
> as well otherwise i64 operations now would require branches. This implies
> updating the corresponding test for unsigned.
> - add new combiner to remove the redundant conversions from/to carry flags
> to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C
> - fixes PR34045
>
> Differential Revision: https://reviews.llvm.org/D35192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312980
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Yonghong Song [Mon, 11 Sep 2017 23:43:35 +0000 (23:43 +0000)]
bpf: add " ll" in the LD_IMM64 asmstring
This partially revert previous fix in commit
f5858045aa0b
("bpf: proper print imm64 expression in inst printer").
In that commit, the original suffix "ll" is removed from
LD_IMM64 asmstring. In the customer print method, the "ll"
suffix is printed if the rhs is an immediate. For example,
"r2 = 5ll" => "r2 = 5ll", and "r3 = varll" => "r3 = var".
This has an issue though for assembler. Since assembler
relies on asmstring to do pattern matching, it will not
be able to distiguish between "mov r2, 5" and
"ld_imm64 r2, 5" since both asmstring is "r2 = 5".
In such cases, the assembler uses 64bit load for all
"r = <val>" asm insts.
This patch adds back " ll" suffix for ld_imm64 with one
additional space for "#reg = #global_var" case.
Signed-off-by: Yonghong Song <yhs@fb.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312978
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Adrian Prantl [Mon, 11 Sep 2017 23:40:44 +0000 (23:40 +0000)]
Update testcases that are XFAILed on Darwin for llvm-dwarfdump changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312977
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Vedant Kumar [Mon, 11 Sep 2017 23:32:30 +0000 (23:32 +0000)]
[llvm-cov] Try to fix a test on Windows
Failing bot:
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/4791
This looks like another stderr redirection issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312975
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Adrian Prantl [Mon, 11 Sep 2017 23:05:20 +0000 (23:05 +0000)]
llvm-dwarfdump: Make -brief the default and add a -verbose option instead.
Differential Revision: https://reviews.llvm.org/D37717
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312972
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Eugene Zelenko [Mon, 11 Sep 2017 23:00:48 +0000 (23:00 +0000)]
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312971
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Adrian Prantl [Mon, 11 Sep 2017 22:59:45 +0000 (22:59 +0000)]
llvm-dwarfdump: Replace -debug-dump=sect option with individual options.
As discussed on llvm-dev in
http://lists.llvm.org/pipermail/llvm-dev/2017-September/117301.html
this changes the command line interface of llvm-dwarfdump to match the
one used by the dwarfdump utility shipping on macOS. In addition to
being shorter to type this format also has the advantage of allowing
more than one section to be specified at the same time.
In a nutshell, with this change
$ llvm-dwarfdump --debug-dump=info
$ llvm-dwarfdump --debug-dump=apple-objc
becomes
$ dwarfdump --debug-info --apple-objc
Differential Revision: https://reviews.llvm.org/D37714
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312970
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Eli Friedman [Mon, 11 Sep 2017 22:56:20 +0000 (22:56 +0000)]
[llvm-cov] Allow hiding instantiation/region coverage from summary tables
Region coverage is difficult to explain without going deep into how
coverage is implemented. Instantiation coverage is easier to explain,
but probably not useful in most cases (templates don't exist in C, and
most C++ code contains relatively few templates).
This patch adds the options "-show-region-summary" and
"-show-instantiation-summary" to allow hiding those columns.
"-show-instantiation-summary" is turned off by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312969
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Peter Collingbourne [Mon, 11 Sep 2017 22:49:10 +0000 (22:49 +0000)]
LowerTypeTests: Add import/export support for targets without absolute symbol constants.
The rationale is the same as for r312967.
Differential Revision: https://reviews.llvm.org/D37408
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312968
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Peter Collingbourne [Mon, 11 Sep 2017 22:34:42 +0000 (22:34 +0000)]
WholeProgramDevirt: Add import/export support for targets without absolute symbol constants.
Not all targets support the use of absolute symbols to export
constants. In particular, ARM has a wide variety of constant encodings
that cannot currently be relocated by linkers. So instead of exporting
the constants using symbols, export them directly in the summary.
The values of the constants are left as zeroes on targets that support
symbolic exports.
This may result in more cache misses when targeting those architectures
as a result of arbitrary changes in constant values, but this seems
somewhat unavoidable for now.
Differential Revision: https://reviews.llvm.org/D37407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312967
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Vedant Kumar [Mon, 11 Sep 2017 21:31:32 +0000 (21:31 +0000)]
[llvm-cov] Don't attach exec counts to lines which start a skipped region
These lines by definition don't have an execution count.
This is the final part of the fix for:
https://bugs.llvm.org/show_bug.cgi?id=34166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312955
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Sanjay Patel [Mon, 11 Sep 2017 20:38:31 +0000 (20:38 +0000)]
[InstSimplify] fix some test names; NFC
Too much division...the quotient is the answer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312943
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Sanjay Patel [Mon, 11 Sep 2017 19:42:41 +0000 (19:42 +0000)]
[InstSimplify] add tests for possible sdiv/srem simplifications; NFC
As noted in PR34517, the handling of signed div/rem is not on par with
unsigned div/rem. Signed is harder to reason about, but it should be
possible to handle at least some of these using the same technique that
we use for unsigned: use icmp logic to see if there's a relationship
between the quotient and divisor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312938
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Matt Arsenault [Mon, 11 Sep 2017 18:54:20 +0000 (18:54 +0000)]
AMDGPU: Allow coldcc calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312936
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Petar Jovanovic [Mon, 11 Sep 2017 18:34:04 +0000 (18:34 +0000)]
[mips][microMIPS] add lapc instruction
Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6.
Patch by Milos Stojanovic.
Differential Revision: https://reviews.llvm.org/D35984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312934
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Hiroshi Yamauchi [Mon, 11 Sep 2017 17:52:08 +0000 (17:52 +0000)]
Unmerge GEPs to reduce register pressure on IndirectBr edges.
Summary:
GEP merging can sometimes increase the number of live values and register
pressure across control edges and cause performance problems particularly if the
increased register pressure results in spills.
This change implements GEP unmerging around an IndirectBr in certain cases to
mitigate the issue. This is in the CodeGenPrepare pass (after all the GEP
merging has happened.)
With this patch, the Python interpreter loop runs faster by ~5%.
Reviewers: sanjoy, hfinkel
Reviewed By: hfinkel
Subscribers: eastig, junbuml, llvm-commits
Differential Revision: https://reviews.llvm.org/D36772
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312930
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Stanislav Mekhanoshin [Mon, 11 Sep 2017 17:13:57 +0000 (17:13 +0000)]
[AMDGPU] Produce madak and madmk from the two-address pass
These two instructions are normally selected, but when the
two address pass converts mac into mad we end up with the
mad where we could have one of these.
Differential Revision: https://reviews.llvm.org/D37389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312928
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Craig Topper [Mon, 11 Sep 2017 16:16:48 +0000 (16:16 +0000)]
[X86] Remove portions of r275950 that are no longer needed with i1 not being a legal type
Summary:
r275950 added support for turning (trunc (X >> N) to i1) into BT(X, N). But that's no longer necessary now that i1 isn't legal.
This patch removes the support for that, but preserves some of the refactorings done in that commit.
Reviewers: guyblank, RKSimon, spatel, zvi
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37673
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312925
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Craig Topper [Mon, 11 Sep 2017 16:15:39 +0000 (16:15 +0000)]
[SelectionDAG] Remove a check for type being a vector type after calling getShiftAmountTy. NFCI
getShiftAmountTy already returns the vector type when called for vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312924
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Zvi Rackover [Mon, 11 Sep 2017 15:54:38 +0000 (15:54 +0000)]
X86 Tests: More AVX512 conversions tests. NFC
Adding more tests for AVX512 fp<->int conversions that were missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312921
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Marcello Maggioni [Mon, 11 Sep 2017 15:44:20 +0000 (15:44 +0000)]
[ScalarEvolution] Refactor forgetLoop() to improve performance
forgetLoop() has pretty bad performance because it goes over
the same instructions over and over again in particular when
nested loop are involved.
The refactoring changes the function to a not-recursive function
and reusing the allocation for data-structures and the Visited
set.
NFCI
Differential Revision: https://reviews.llvm.org/D37659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312920
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Matt Arsenault [Mon, 11 Sep 2017 15:23:22 +0000 (15:23 +0000)]
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312919
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Simon Pilgrim [Mon, 11 Sep 2017 14:03:47 +0000 (14:03 +0000)]
[X86][SSE] Add support for X86ISD::PACKSS to ComputeNumSignBitsForTargetNode
Helps improve combineLogicBlendIntoPBLENDV support by allowing us to peek into through PACKSS truncations of vector comparison results.
Differential Revision: https://reviews.llvm.org/D37680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312916
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Tim Renouf [Mon, 11 Sep 2017 13:55:39 +0000 (13:55 +0000)]
[AMDGPU] exp should not be in WQM mode
A mrt exp with vm=1 must be in exact (non-WQM) mode, as it also exports
the exec mask as the valid mask to determine which pixels to render.
This commit marks any exp as needing to be in exact mode.
Actually, if there are multiple mrt exps, only one needs to have vm=1,
and only that one needs to be in exact mode. But that is an optimization
for another day.
Differential Revision: https://reviews.llvm.org/D36305
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312915
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Francis Ricci [Mon, 11 Sep 2017 13:50:39 +0000 (13:50 +0000)]
[TableGen] Ensure that __lsan_is_turned_off isn't removed by DCE in llvm-tblgen
Summary:
Since asan is linked dynamically on Darwin, the weak interface symbol
is removed by -Wl,-dead_strip.
Reviewers: kcc, compnerd, aaron.ballman
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37636
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312914
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Sanjay Patel [Mon, 11 Sep 2017 13:34:27 +0000 (13:34 +0000)]
[InstSimplify] reorder methods; NFC
I'm trying to refactor some shared code for integer div/rem,
but I keep having to scroll through fdiv. The FP ops have
nothing in common with the integer ops, so I'm moving FP
below everything else.
While here, improve a couple of comments and fix some formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312913
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Simon Pilgrim [Mon, 11 Sep 2017 12:18:43 +0000 (12:18 +0000)]
[X86][SSE] Add further test cases showing failure to compute sign bits through PACKSS
Suggested in D37680
Note: had to drop AVX512VL tests as there is an infinite loop in the new tests that needs further investigation (not relevant to D37680).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312910
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Gadi Haber [Mon, 11 Sep 2017 11:26:20 +0000 (11:26 +0000)]
[X86][SKX][KNL] Updating several CodeGen tests to use the attr flag instead of mcpu flag
NFC.
Updated 3 Codegen regression tests to use the -mattr flag instead of the -mcpu flags as follows:
Instead of -mcpu=skx use -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq
Instead of -mcpu=knl use -mattr=+avx512f
Reviewers: delena
Revision: https://reviews.llvm.org/D37674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312909
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Andre Vieira [Mon, 11 Sep 2017 11:11:17 +0000 (11:11 +0000)]
[ARM] Enable the use of SVC anywhere in an IT block
Differential Revision: https://reviews.llvm.org/D37374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312908
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Michael Zuckerman [Mon, 11 Sep 2017 10:57:15 +0000 (10:57 +0000)]
[Interleved][Stride 3]Adding test for case the VF=64 target with AVX512.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312907
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Simon Pilgrim [Mon, 11 Sep 2017 10:50:03 +0000 (10:50 +0000)]
[X86][SSE] Add test showing failure to compute sign bits through PACKSS
Prevents combineLogicBlendIntoPBLENDV from merging to PBLENDV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312906
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Dylan McKay [Mon, 11 Sep 2017 10:32:51 +0000 (10:32 +0000)]
[AVR] Enable the '__do_copy_data' function
Also enables '__do_clear_bss'.
These functions are automaticalled called by the CRT if they are
declared.
We need these to be called otherwise RAM will start completely
uninitialised, even though we need to copy RAM variables from progmem to
RAM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312905
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Igor Breger [Mon, 11 Sep 2017 09:41:13 +0000 (09:41 +0000)]
[GlobalISel][X86] G_ANYEXT support.
Summary: G_ANYEXT support
Reviewers: zvi, delena
Reviewed By: delena
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D37675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312903
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Ilya Biryukov [Mon, 11 Sep 2017 09:22:44 +0000 (09:22 +0000)]
Fixed a typo in llvm-cov/deferred-region.cpp test.
Input redirection was using `2&>1` instead of `2>&1`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312902
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Tim Renouf [Mon, 11 Sep 2017 08:31:32 +0000 (08:31 +0000)]
AMDGPU: trivial comment change
... to check commit access for new committer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312900
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Roger Ferrer Ibanez [Mon, 11 Sep 2017 07:38:05 +0000 (07:38 +0000)]
[ARM] Use ADDCARRY / SUBCARRY
This is a preparatory step for D34515 and also is being recommitted as its
first version caused PR34045.
This change:
- makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32
- lowering is done by first converting the boolean value into the carry flag
using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value
using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two
operations does the actual addition.
- for subtraction, given that ISD::SUBCARRY second result is actually a
borrow, we need to invert the value of the second operand and result before
and after using ARMISD::SUBE. We need to invert the carry result of
ARMISD::SUBE to preserve the semantics.
- given that the generic combiner may lower ISD::ADDCARRY and
ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering
as well otherwise i64 operations now would require branches. This implies
updating the corresponding test for unsigned.
- add new combiner to remove the redundant conversions from/to carry flags
to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C
- fixes PR34045
Differential Revision: https://reviews.llvm.org/D35192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312898
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Elena Demikhovsky [Mon, 11 Sep 2017 06:18:15 +0000 (06:18 +0000)]
Fixed a bug in splitting Scatter operation in the Type Legalizer.
After the split of the Scatter operation, the order of the new instructions is well defined - Lo goes before Hi. Otherwise the semantic of Scatter (from LSB to MSB) is broken.
I'm chaining 2 nodes to prevent reordering.
Differential Revision https://reviews.llvm.org/D37670
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312894
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Lang Hames [Mon, 11 Sep 2017 01:09:46 +0000 (01:09 +0000)]
[ORC] Kill off a dead typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312893
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