OSDN Git Service
Jim Grosbach [Mon, 19 Dec 2011 19:02:41 +0000 (19:02 +0000)]
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146887
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Jim Grosbach [Mon, 19 Dec 2011 18:57:38 +0000 (18:57 +0000)]
ARM NEON implied destination aliases for VMAX/VMIN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885
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Jim Grosbach [Mon, 19 Dec 2011 18:31:43 +0000 (18:31 +0000)]
ARM NEON relax parse time diagnostics for alignment specifiers.
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884
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Jim Grosbach [Mon, 19 Dec 2011 18:11:17 +0000 (18:11 +0000)]
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146882
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Jakob Stoklund Olesen [Mon, 19 Dec 2011 16:53:40 +0000 (16:53 +0000)]
Remove a register class that can just as well be synthesized.
Add the new TableGen register class synthesizer feature to the release
notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146875
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Jakob Stoklund Olesen [Mon, 19 Dec 2011 16:53:37 +0000 (16:53 +0000)]
Handle sub-register operands in recomputeRegClass().
Now that getMatchingSuperRegClass() returns accurate results, it can be
used to compute constraints imposed by instructions using a sub-register
of a virtual register.
This means we can recompute the register class of any virtual register
by combining the constraints from all its uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146874
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Jakob Stoklund Olesen [Mon, 19 Dec 2011 16:53:34 +0000 (16:53 +0000)]
Emit a getMatchingSuperRegClass() implementation for every target.
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().
Delete the old manual, error-prone implementations in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873
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Jakob Stoklund Olesen [Mon, 19 Dec 2011 16:53:28 +0000 (16:53 +0000)]
Synthesize register classes for TRI::getMatchingSuperRegClass().
Teach TableGen to create the missing register classes needed for
getMatchingSuperRegClass() to return maximal results. The function is
still not auto-generated, so it still returns inexact results.
This produces these new register classes:
ARM:
QQPR_with_dsub_0_in_DPR_8
QQQQPR_with_dsub_0_in_DPR_8
X86:
GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP
GR64_with_sub_16bit_in_GR16_NOREX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP
GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_with_sub_32bit_in_GR32_TC
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC
GR64_with_sub_32bit_in_GR32_AD
GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX
The other targets in the tree are not weird enough to be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146872
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Manuel Klimek [Mon, 19 Dec 2011 09:56:35 +0000 (09:56 +0000)]
Allow for benchmarking more than 4GB of memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146864
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Manuel Klimek [Mon, 19 Dec 2011 09:32:05 +0000 (09:32 +0000)]
Adds a flag to allow specifying the memory limitations of the JSON benchmark.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146863
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Jakub Staszak [Sun, 18 Dec 2011 21:52:30 +0000 (21:52 +0000)]
- Use getExitingBlock instead of getExitingBlocks.
- Remove trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146854
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Benjamin Kramer [Sun, 18 Dec 2011 20:51:31 +0000 (20:51 +0000)]
Another variadics tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146852
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Joerg Sonnenberger [Sun, 18 Dec 2011 20:35:43 +0000 (20:35 +0000)]
Allow inlining of functions with returns_twice calls, if they have the
attribute themselve.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146851
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Benjamin Kramer [Sun, 18 Dec 2011 19:59:20 +0000 (19:59 +0000)]
Use the fancy new VariadicFunction template instead of a plain variadic function.
Some compilers were complaining about passing StringRef to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146850
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Dylan Noblesmith [Sun, 18 Dec 2011 18:50:16 +0000 (18:50 +0000)]
capitalize project name, reference bugzilla
And fix the double-[]. It was including the [] as part of
the project name somehow, resulting in PACKAGE_TARNAME "-llvm-"
and a strange docdir default:
./configure --help | grep docdir
--docdir=DIR documentation root [DATAROOTDIR/doc/-llvm-]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146849
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Benjamin Kramer [Sun, 18 Dec 2011 12:00:09 +0000 (12:00 +0000)]
Hexagon: Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146846
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Chad Rosier [Sat, 17 Dec 2011 22:19:53 +0000 (22:19 +0000)]
Revert 146728 as it's causing failures on some of the external bots as well as
internal nightly testers. Original commit message:
By popular demand, link up types by name if they are isomorphic and one is an
autorenamed version of the other. This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large
app.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146838
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Kevin Enderby [Sat, 17 Dec 2011 19:48:52 +0000 (19:48 +0000)]
Revert r146822 at Pete Cooper's request as it broke clang self hosting.
Hope I did this correctly :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146834
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Craig Topper [Sat, 17 Dec 2011 19:16:44 +0000 (19:16 +0000)]
Remove an unused X86ISD node type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146833
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Benjamin Kramer [Sat, 17 Dec 2011 14:36:05 +0000 (14:36 +0000)]
X86: Factor the bswap asm matching to be slightly less horrible to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146831
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Chandler Carruth [Sat, 17 Dec 2011 10:20:15 +0000 (10:20 +0000)]
As Doug pointed out (and I really should know), it is perfectly easy to
make VariadicFunction actually be trivial. Do so, and also make it look
more like your standard trivial functor by making it a struct with no
access specifiers. The unit test is updated to initialize its functors
properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146827
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Pete Cooper [Sat, 17 Dec 2011 06:32:38 +0000 (06:32 +0000)]
SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands.
For example,
if (a == b) {
if (a > b) // this is false
Fixes some of the issues on <rdar://problem/
10554090>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146822
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Manuel Klimek [Sat, 17 Dec 2011 06:29:32 +0000 (06:29 +0000)]
Deleting the json-bench-test until I understand why it is flaky.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146821
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Evan Cheng [Sat, 17 Dec 2011 01:25:34 +0000 (01:25 +0000)]
Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146805
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Pete Cooper [Sat, 17 Dec 2011 01:20:32 +0000 (01:20 +0000)]
Refactor code used in InstCombine::FoldAndOfICmps to new file.
This will be used by SimplifyCfg in a later commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146803
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Rafael Espindola [Sat, 17 Dec 2011 01:14:52 +0000 (01:14 +0000)]
Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
asm parsing and testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146801
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Lang Hames [Sat, 17 Dec 2011 01:08:46 +0000 (01:08 +0000)]
Make sure that the lower bits on the VSELECT condition are properly set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146800
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Jakob Stoklund Olesen [Sat, 17 Dec 2011 00:07:02 +0000 (00:07 +0000)]
Preserve more memory operands in ARMExpandPseudo.
I don't think this affects anything but verbose assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146787
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Dan Gohman [Sat, 17 Dec 2011 00:04:22 +0000 (00:04 +0000)]
The powers that be have decided that LLVM IR should now support 16-bit
"half precision" floating-point with a first-class type.
This patch adds basic IR support (but not codegen support).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146786
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Eric Christopher [Fri, 16 Dec 2011 23:42:45 +0000 (23:42 +0000)]
When recursing for the original size of a type, stop if we are at a
pointer or a reference type - we actually just want the size of the
pointer then for that.
Fixes rdar://
10335756
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146785
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Eric Christopher [Fri, 16 Dec 2011 23:42:42 +0000 (23:42 +0000)]
Resolve part of a fixme and add a new one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146784
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Eric Christopher [Fri, 16 Dec 2011 23:42:38 +0000 (23:42 +0000)]
Add a fixme here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146783
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Eric Christopher [Fri, 16 Dec 2011 23:42:35 +0000 (23:42 +0000)]
Fix spacing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146782
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Eric Christopher [Fri, 16 Dec 2011 23:42:33 +0000 (23:42 +0000)]
Update documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146781
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Eric Christopher [Fri, 16 Dec 2011 23:42:31 +0000 (23:42 +0000)]
Extraneous whitespace and 80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146780
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Jakob Stoklund Olesen [Fri, 16 Dec 2011 23:00:05 +0000 (23:00 +0000)]
Fix off-by-one error in bucket sort.
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.
<rdar://problem/
10594653>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146767
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Dylan Noblesmith [Fri, 16 Dec 2011 20:36:31 +0000 (20:36 +0000)]
APInt: update asserts for base-36
Hexatridecimal was added in r139695.
And fix the unittest that now triggers the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146754
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Jakob Stoklund Olesen [Fri, 16 Dec 2011 19:10:00 +0000 (19:10 +0000)]
Don't adjust for alignment padding in OffsetIsInRange.
This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.
When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146751
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Benjamin Kramer [Fri, 16 Dec 2011 19:08:59 +0000 (19:08 +0000)]
Hexagon: Fix a nasty order-of-initialization bug.
Reenable the tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146750
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Devang Patel [Fri, 16 Dec 2011 17:51:31 +0000 (17:51 +0000)]
In DICompositeType, referenced to derived type is either metadata or null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146744
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Devang Patel [Fri, 16 Dec 2011 17:50:04 +0000 (17:50 +0000)]
Clarify and fix subprogram description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146743
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Jakob Stoklund Olesen [Fri, 16 Dec 2011 16:07:41 +0000 (16:07 +0000)]
Note ARM constant island alignment in the release notes.
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146739
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Manuel Klimek [Fri, 16 Dec 2011 13:09:10 +0000 (13:09 +0000)]
Adds a JSON parser and a benchmark (json-bench) to catch performance regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146735
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Chandler Carruth [Fri, 16 Dec 2011 09:37:55 +0000 (09:37 +0000)]
Put the '*' in the right place in the unit test. Forgot to fix up this
bit of style, sorry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146733
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Chandler Carruth [Fri, 16 Dec 2011 09:36:16 +0000 (09:36 +0000)]
Make GCC happy by using makeAraryRef instead of the implicit conversion.
I have no idea why GCC can't cope with the implicit conversion and Clang
can, or whose bug it is. Grr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146732
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Chandler Carruth [Fri, 16 Dec 2011 08:58:59 +0000 (08:58 +0000)]
Add a generic collection of class templates to ADT for building
variadic-like functions in C++98. See the comments in the header file
for a more detailed description of how these work. We plan to use these
extensively in the AST matching library. This code and idea were
originally authored by Zhanyong Wan. I've condensed it using macros
to reduce repeatition and adjusted it to fit better with LLVM's ADT.
Thanks to both David Blaikie and Doug Gregor for the review!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146729
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Chris Lattner [Fri, 16 Dec 2011 08:36:07 +0000 (08:36 +0000)]
By popular demand, link up types by name if they are isomorphic and one is an
autorenamed version of the other. This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large app.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146728
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Craig Topper [Fri, 16 Dec 2011 08:06:31 +0000 (08:06 +0000)]
Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146726
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NAKAMURA Takumi [Fri, 16 Dec 2011 06:21:08 +0000 (06:21 +0000)]
Tweak CMake build on Cygwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146725
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NAKAMURA Takumi [Fri, 16 Dec 2011 06:21:02 +0000 (06:21 +0000)]
Target/Hexagon: Fix CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146724
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Andrew Trick [Fri, 16 Dec 2011 02:03:48 +0000 (02:03 +0000)]
Avoid a confusing assert for silly options: -unroll-runtime -unroll-count=1.
No need for an explicit test case for an unsupported combination of options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146721
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Kostya Serebryany [Fri, 16 Dec 2011 01:28:19 +0000 (01:28 +0000)]
[asan] add a test for instrumenting globals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146718
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Jim Grosbach [Fri, 16 Dec 2011 00:12:22 +0000 (00:12 +0000)]
ARM NEON aliases for vmovq.f*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146714
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Jakob Stoklund Olesen [Fri, 16 Dec 2011 00:12:05 +0000 (00:12 +0000)]
Extract a method. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146713
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Daniel Dunbar [Fri, 16 Dec 2011 00:04:43 +0000 (00:04 +0000)]
llvm-config: Fix --targets-built, I changed this to use the registry but wasn't
properly initializing the target infos. I decided it wasn't worth linking them
in for this, so just switched back to using the Makefile variable for now. We
can reconsider later if we ever get pluggable targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146711
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Jim Grosbach [Thu, 15 Dec 2011 23:52:17 +0000 (23:52 +0000)]
Thumb2 ADR assembly parsing w/o the .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146710
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Eli Friedman [Thu, 15 Dec 2011 23:46:18 +0000 (23:46 +0000)]
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709
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Daniel Dunbar [Thu, 15 Dec 2011 23:43:17 +0000 (23:43 +0000)]
llvm-config: Update help text for removal of "backend" pseudo component.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146708
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Daniel Dunbar [Thu, 15 Dec 2011 23:35:08 +0000 (23:35 +0000)]
build/unittests: Fix llvm-config names for gtest libraries, and bring Makefile
library names in line with those used by CMake.
- Patch by Johannes Obermayr, with tweaks by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146706
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Nick Lewycky [Thu, 15 Dec 2011 22:58:58 +0000 (22:58 +0000)]
Move parts of lib/Target that use CodeGen into lib/CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146702
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Eli Friedman [Thu, 15 Dec 2011 22:56:53 +0000 (22:56 +0000)]
Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146700
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Jim Grosbach [Thu, 15 Dec 2011 22:56:33 +0000 (22:56 +0000)]
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699
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Kostya Serebryany [Thu, 15 Dec 2011 22:55:55 +0000 (22:55 +0000)]
[asan] add the name of the module to the description of a global variable. This improves the readability of global-buffer-overflow reports.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146698
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Tony Linthicum [Thu, 15 Dec 2011 22:29:08 +0000 (22:29 +0000)]
Add MCTargetDesc library to Hexagon target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146692
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Jim Grosbach [Thu, 15 Dec 2011 22:27:11 +0000 (22:27 +0000)]
ARM NEON VTBL/VTBX assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691
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Jakob Stoklund Olesen [Thu, 15 Dec 2011 22:14:45 +0000 (22:14 +0000)]
Enable proper constant island alignment by default.
The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146690
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Chad Rosier [Thu, 15 Dec 2011 22:11:31 +0000 (22:11 +0000)]
Add missing zmovl AVX patterns which were causing crashes.
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146689
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Kostya Serebryany [Thu, 15 Dec 2011 21:59:03 +0000 (21:59 +0000)]
[asan] fix a bug (issue 19) where dlclose and the following mmap caused a false positive. compiler part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146688
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Jim Grosbach [Thu, 15 Dec 2011 21:54:55 +0000 (21:54 +0000)]
Silence warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146686
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Jim Grosbach [Thu, 15 Dec 2011 21:44:33 +0000 (21:44 +0000)]
ARM NEON two-register double spaced register list parsing support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146685
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Chad Rosier [Thu, 15 Dec 2011 21:34:44 +0000 (21:34 +0000)]
Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146684
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Eli Friedman [Thu, 15 Dec 2011 21:11:38 +0000 (21:11 +0000)]
Zap unnecessary semicolons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146682
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Lang Hames [Thu, 15 Dec 2011 20:22:34 +0000 (20:22 +0000)]
Set specific target cpu for testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146678
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Lang Hames [Thu, 15 Dec 2011 19:56:07 +0000 (19:56 +0000)]
Added test case for r146671.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146675
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Jakob Stoklund Olesen [Thu, 15 Dec 2011 19:26:23 +0000 (19:26 +0000)]
Use the proper comparator for set_intersection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146674
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Lang Hames [Thu, 15 Dec 2011 18:57:27 +0000 (18:57 +0000)]
Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/
10559581>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146671
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Devang Patel [Thu, 15 Dec 2011 18:21:18 +0000 (18:21 +0000)]
Update DebugLoc while merging nodes at -O0.
Patch by Kyriakos Georgiou!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146670
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Hal Finkel [Thu, 15 Dec 2011 17:59:23 +0000 (17:59 +0000)]
Add a test case to make sure that the nop really does follow the bl on ppc64 elf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146666
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Devang Patel [Thu, 15 Dec 2011 17:55:56 +0000 (17:55 +0000)]
Virtual table holder field is either metadata or null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146665
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Hal Finkel [Thu, 15 Dec 2011 17:54:01 +0000 (17:54 +0000)]
Ensure that the nop that should follow a bl call in PPC64 ELF actually does
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146664
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Jakob Stoklund Olesen [Thu, 15 Dec 2011 16:48:55 +0000 (16:48 +0000)]
Synthesize missing register class intersections.
The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B. This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.
In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).
This introduces these synthetic register classes:
ARM:
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
tGPR_and_tcGPR
hGPR_and_tcGPR
X86:
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR64_NOSP_and_GR64_TC
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_TC
GR32_NOAX_and_GR32_NOSP
GR64_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_ABCD_and_GR32_NOAX
GR64_ABCD_and_GR64_TC
GR32_NOAX_and_GR32_TC
GR32_AD_and_GR32_NOAX
Other targets are unaffected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146657
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Richard Osborne [Thu, 15 Dec 2011 15:18:35 +0000 (15:18 +0000)]
Pass optLevel to XCoreDAGToDAGISel.
Patch by Kyriakos Georgiou.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146656
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Eli Friedman [Thu, 15 Dec 2011 04:52:47 +0000 (04:52 +0000)]
Fix test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146642
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Eli Friedman [Thu, 15 Dec 2011 04:33:48 +0000 (04:33 +0000)]
Make constant folding for GEPs a bit more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146639
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Eli Friedman [Thu, 15 Dec 2011 02:07:20 +0000 (02:07 +0000)]
Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146630
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Chad Rosier [Thu, 15 Dec 2011 01:16:09 +0000 (01:16 +0000)]
Use SmallVector/assign(), rather than std::vector/push_back().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146627
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Chad Rosier [Thu, 15 Dec 2011 01:02:25 +0000 (01:02 +0000)]
Add support for lowering fneg when AVX is enabled.
rdar://
10566486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146625
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Pete Cooper [Thu, 15 Dec 2011 00:56:45 +0000 (00:56 +0000)]
Added InstCombine for "select cond, ~cond, x" type patterns
These can be reduced to "~cond & x" or "~cond | x"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146624
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Owen Anderson [Thu, 15 Dec 2011 00:54:12 +0000 (00:54 +0000)]
Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. These are already marked as illegal by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146623
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Eli Friedman [Thu, 15 Dec 2011 00:50:34 +0000 (00:50 +0000)]
Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146621
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Bill Wendling [Thu, 15 Dec 2011 00:14:24 +0000 (00:14 +0000)]
Re-re-enable compact unwind after fixing a failure in SingleSource/Benchmarks/Shootout-C++/except.cpp and friends. It was encoding the stored registers in the wrong order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146617
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Kevin Enderby [Thu, 15 Dec 2011 00:00:27 +0000 (00:00 +0000)]
Another improvement to the implementation of .incbin directive by avoiding a
buffer copy. Suggestion by Chris Lattner!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146614
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Bill Wendling [Wed, 14 Dec 2011 23:53:24 +0000 (23:53 +0000)]
The saved registers weren't being processed in the correct order. This lead to
the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146612
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Dan Gohman [Wed, 14 Dec 2011 23:49:11 +0000 (23:49 +0000)]
Move Instruction::isSafeToSpeculativelyExecute out of VMCore and
into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146610
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Jakob Stoklund Olesen [Wed, 14 Dec 2011 23:48:54 +0000 (23:48 +0000)]
Consider CPE alignment in CreateNewWater().
An aligned constant pool entry may require extra alignment padding where
the new water is created. Take that into account when computing offset.
Also consider the alignment of other constant pool entries when
splitting a basic block. Alignment padding may make it necessary to
move the split point higher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146609
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Jim Grosbach [Wed, 14 Dec 2011 23:35:06 +0000 (23:35 +0000)]
ARM NEON better assembly operand range checking for lane indices of VLD/VST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146608
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Jim Grosbach [Wed, 14 Dec 2011 23:25:46 +0000 (23:25 +0000)]
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605
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Devang Patel [Wed, 14 Dec 2011 23:20:38 +0000 (23:20 +0000)]
Do not sink instruction, if it is not profitable.
On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.
Radar
10266272.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146604
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Evan Cheng [Wed, 14 Dec 2011 22:57:45 +0000 (22:57 +0000)]
Add a blurb about MachineInstr bundling support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146603
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Bill Wendling [Wed, 14 Dec 2011 22:45:33 +0000 (22:45 +0000)]
Reapply r146481 with a fix to create the Builder value in the correct place and
with the correct iterator.
<rdar://problem/
10530851>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146600
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