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Dave Airlie [Thu, 21 Mar 2019 05:22:02 +0000 (15:22 +1000)]
softpipe: fix integer texture swizzling for 1 vs 1.0f
The swizzling was putting float one in not integer 1.
This fixes a lot of arb_texture_view-rendering-formats cases.
Reviewed-by: Brian Paul <brianp@vmware.com>
Dave Airlie [Thu, 21 Mar 2019 04:27:14 +0000 (14:27 +1000)]
softpipe: remove shadow_ref assert.
I don't think this really buys us anything and TG4 with cubemap arrays
falls over because sampler == 2, but otherwise works fine.
Fixes:
./bin/textureGather fs shadow r CubeArray repeat
on softpipe with ARB_gpu_shader5 enabled.
Reviewed-by: Brian Paul <brianp@vmware.com>
Dave Airlie [Thu, 21 Mar 2019 04:15:43 +0000 (14:15 +1000)]
softpipe: handle 32-bit bitfield inserts
Fixes piglits if ARB_gpu_shader5 is enabled
Reviewed-by: Brian Paul <brianp@vmware.com>
Dave Airlie [Thu, 21 Mar 2019 04:13:48 +0000 (14:13 +1000)]
softpipe: fix 32-bit bitfield extract
These didn't deal with the width == 32 case that TGSI is defined with.
Fixes piglit tests if ARB_gpu_shader5 is enabled.
Reviewed-by: Brian Paul <brianp@vmware.com>
Timothy Arceri [Wed, 20 Mar 2019 11:59:40 +0000 (22:59 +1100)]
nir: fix opt_if_loop_last_continue()
Rather than skipping code that looked like this:
loop {
...
if (cond) {
do_work_1();
continue;
} else {
break;
}
do_work_2();
}
Previously we would turn this into:
loop {
...
if (cond) {
do_work_1();
continue;
} else {
do_work_2();
break;
}
}
This was clearly wrong. This change checks for this case and makes
sure we now leave it for nir_opt_dead_cf() to clean up.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Gurchetan Singh [Tue, 19 Mar 2019 02:06:05 +0000 (19:06 -0700)]
anv: fix build on Nougat
AHardwareBuffer is only available on O and above.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Gurchetan Singh [Wed, 20 Mar 2019 02:20:53 +0000 (19:20 -0700)]
anv: move anv_GetMemoryAndroidHardwareBufferANDROID up a bit
No functional change, just makes the next patch a little easier.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Gurchetan Singh [Fri, 15 Mar 2019 17:08:45 +0000 (10:08 -0700)]
configure.ac / meson: depend on libnativewindow when appropriate
libnativewindow is only available on O or greater, and it's
required for some features.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Anholt [Tue, 19 Mar 2019 21:05:30 +0000 (14:05 -0700)]
v3d: Remove some dead members of struct v3d_compile.
These are more vc4 leftovers.
Eric Anholt [Tue, 19 Mar 2019 16:58:14 +0000 (09:58 -0700)]
v3d: Upload all of UBO[0] if any indirect load occurs.
The idea was that we could skip uploading the constant-indexed uniform
data and just upload the uniforms that are variably-indexed. However,
since the VS bin and render shaders may have a different set of uniforms
used, this meant that we had to upload the UBO for each of them. The
first case is generally a fairly small impact (usually the uniform array
is the most space, other than a couple of FSes in shader-db), while the
second is a larger impact: 3DMMES2 was uploading 38k/frame of uniforms
instead of 18k.
Given that the optimization is of dubious value, has a big downside, and
is quite a bit of code, just drop it. No change in shader-db. No change
on 3DMMES2 (n=15).
Eric Anholt [Tue, 19 Mar 2019 18:39:58 +0000 (11:39 -0700)]
v3d: Move constant offsets to UBO addresses into the main uniform stream.
We'd end up with the constant offset in the uniform stream anyway, since
they're bigger than small immediates. Avoids the extra uniforms and adds
in the shader in favor of just adding once on the CPU.
shader-db:
total instructions in shared programs:
6496865 ->
6494851 (-0.03%)
total uniforms in shared programs:
2119511 ->
2117243 (-0.11%)
Eric Anholt [Tue, 19 Mar 2019 18:29:02 +0000 (11:29 -0700)]
v3d: Rename v3d_tmu_config_data to v3d_unit_data.
I want to reuse this for encoding small constant UBO/SSBO offsets into the
uniform stream to reduce the extra uniform loads and adds for the small
constant offsets.
Benjamin Gordon [Wed, 13 Jun 2018 22:17:32 +0000 (16:17 -0600)]
configure.ac/meson.build: Add options for library suffixes
When building the Chrome OS Android container, we need to build copies
of mesa that don't conflict with the Android system-supplied libraries.
This adds options to create suffixed versions of EGL and GLES libraries:
libEGL.so -> libEGL${egl-lib-suffix}.so
libGLESv1_CM.so -> libGLESv1_CM${gles-lib-suffix}.so
libGLESv2.so -> libGLES${gles-lib-suffix}.so
This is similar to what happens when --enable-libglvnd is specified, but
without the side effects of linking against libglvnd. To avoid
unexpected clashes with the suffixed appended by libglvnd, make it an
error to specify both --enable-libglvnd and --with-egl-lib-suffix.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Kenneth Graunke [Wed, 20 Mar 2019 04:40:51 +0000 (21:40 -0700)]
nir: Record non-vector/scalar varyings as unmovable when compacting
In some cases, we can end up with varying structs that aren't split to
their member variables. nir_compact_varyings attempted to record these
as unmovable, so it would leave them be. Unfortunately, it didn't do
it right for non-vector/scalar types. It set the mask to:
((1 << (elements * dmul)) - 1) << var->data.location_frac
where elements is the number of vector elements. For structures and
other non-vector/scalars, elements is 0...so the whole mask became 0.
This caused nir_compact_varyings to assign other varyings on top of
the structure varying's location (as it appeared to take up no space).
To combat this, we just set elements to 4 for non-vector/scalar types,
so that the entire slot gets marked as unmovable.
Fixes KHR-GL45.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_in on iris.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Rob Clark [Wed, 20 Mar 2019 14:38:01 +0000 (10:38 -0400)]
freedreno/ir3: dynamic UBO indexing vs 64b pointers
Fixes dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.uniform_fragment
and similar things with multiple UBOs
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 20 Mar 2019 12:53:44 +0000 (08:53 -0400)]
freedreno/ir3: fix bit_count
Seems like it can only work 16b at a time. Fixes
dEQP-GLES31.functional.shaders.builtin_functions.integer.bitcount.*
TODO need to check if this limitation applies to a3xx as well.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 19 Mar 2019 18:45:40 +0000 (14:45 -0400)]
freedreno/ir3: additional lowering
For some things that show up when we expose higher glsl
TODO check blob traces to see if we have instructions for some of this?
I guess we don't but worth a check..
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 19 Mar 2019 17:30:03 +0000 (13:30 -0400)]
freedreno/ir3: optimize sam.s2en to sam
Detect when sampler/texture idx are immediate and switch to non s2en
encoding.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 16 Mar 2019 14:33:26 +0000 (10:33 -0400)]
freedreno/ir3: enable indirect tex/samp (sam.s2en)
For now it uses indirect for everything. The next step is for the
ir3_cp pass to detect the case that tex and samp idx are immediate
and convert the sam instruction back to the non .s2en variant. But
doing that in a following patch so we can shake out the bugs with
.s2en more easily.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 19 Mar 2019 16:51:39 +0000 (12:51 -0400)]
freedreno/ir3: find # of samplers from uniform vars
When we have indirect samplers, we cannot tell the max sampler
referenced. Instead just refer to the number of sampler uniforms.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 19 Mar 2019 19:54:32 +0000 (15:54 -0400)]
nir: move gls_type_get_{sampler,image}_count()
I need at least the sampler variant in ir3..
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Rob Clark [Sat, 16 Mar 2019 15:45:16 +0000 (11:45 -0400)]
freedreno/ir3: fix regmask for merged regs
On a6xx+ with half-regs conflicting with full-regs, the legalize pass
needs to set appropriate sync bits, such as (sy), on writes to full regs
that conflict with half regs, and visa-versa.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 16 Mar 2019 14:29:44 +0000 (10:29 -0400)]
freedreno/ir3: fix sam.s2en encoding
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 16 Mar 2019 14:29:05 +0000 (10:29 -0400)]
freedreno/ir3: fix sam.s2en decoding
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 16 Mar 2019 14:03:12 +0000 (10:03 -0400)]
freedreno/ir3/ra: fix half-class conflicts
On a6xx, half-regs conflict with full-regs. But we were only setting up
conflicts for the first class (ie. scalar, but not hvec2/hvec3/hvec4),
resulting in higher half-reg classes getting assigned to regs that
overwrite full-regs.
Noticed while trying to enable indirect-sampler (sam.s2en) which uses an
hvec2 argument to pass the sampler/tex index.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 15 Mar 2019 14:29:10 +0000 (10:29 -0400)]
freedreno/ir3 better cat6 encoding detection
These two bits seem to be a better way to detect which encoding we are
looking at.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Samuel Pitoiset [Thu, 21 Mar 2019 11:42:44 +0000 (12:42 +0100)]
ac: fix incorrect argument type for tbuffer.{load,store} with LLVM 7
GLC/SLC are boolean.
This fixes the following LLVM error when checkir is set:
Intrinsic has incorrect argument type!
void (i32, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32)* @llvm.amdgcn.tbuffer.store.i32
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl
Samuel Pitoiset [Thu, 21 Mar 2019 10:59:37 +0000 (11:59 +0100)]
ac: fix 16-bit shifts
This fixes the following LLVM error when ckeckir is set:
Type too small for ZExt
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl
Samuel Pitoiset [Thu, 21 Mar 2019 08:19:06 +0000 (09:19 +0100)]
ac: add 16-bit support to fract
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 21 Mar 2019 09:14:30 +0000 (10:14 +0100)]
ac: add 16-bit support fo fsign
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 21 Mar 2019 09:14:29 +0000 (10:14 +0100)]
ac: add f16_0 and f16_1 constants
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Timothy Arceri [Tue, 19 Mar 2019 01:09:36 +0000 (12:09 +1100)]
nir: only override previous alu during loop analysis if supported
Users of this function expect alu to be a supported comparision
if the induction variable is not NULL. Since we attempt to
override the return values if the first limit is not a const, we
must make sure we are dealing with a valid comparision before
overriding the alu instruction.
Fixes an unreachable in inverse_comparison() with the game
Assasins Creed Odyssey.
Fixes:
3235a942c16b ("nir: find induction/limit vars in iand instructions")
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110216
Michel Dänzer [Wed, 20 Mar 2019 10:00:06 +0000 (11:00 +0100)]
gitlab-ci: Use 8 CPU cores in autotools job
This cuts down the job runtime from ~9.5 to ~7 minutes with my personal
runner on an 8-core Ryzen 7 1700.
While this might result in slightly higher load on shared runners, it
should be OK, since libtool doesn't use the CPU cores as effectively as
e.g. ninja does; a significant part of the CPU load tends to be in bash
processes at any time, which should be relatively light on memory.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Michel Dänzer [Wed, 20 Mar 2019 14:58:31 +0000 (15:58 +0100)]
gitlab-ci: List some longer-running jobs before others of the same stage
This increases the chance of them running earlier, which can have an
impact on the total duration of the pipeline.
v2:
* Minor style fix-up to moved comment (Eric Anholt)
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Eric Anholt <eric@anholt.net>
Samuel Pitoiset [Thu, 21 Mar 2019 07:59:54 +0000 (08:59 +0100)]
radv: add missing initializations since VK_EXT_pipeline_creation_feedback
This fixes the world.
Fixes:
5f5ac19f138 ("radv: Implement VK_EXT_pipeline_creation_feedback.")"
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Rhys Perry [Thu, 6 Dec 2018 13:33:48 +0000 (13:33 +0000)]
radv: enable VK_KHR_8bit_storage
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Rhys Perry [Thu, 6 Dec 2018 14:38:52 +0000 (14:38 +0000)]
ac/nir: implement 8-bit conversions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Rhys Perry [Fri, 7 Dec 2018 14:52:29 +0000 (14:52 +0000)]
ac/nir: add 8-bit types to glsl_base_to_llvm_type
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Rhys Perry [Thu, 6 Dec 2018 14:57:40 +0000 (14:57 +0000)]
ac/nir: implement 8-bit ssbo stores
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 13 Mar 2019 15:08:32 +0000 (16:08 +0100)]
ac: add ac_build_tbuffer_store_byte() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Rhys Perry [Thu, 6 Dec 2018 13:56:01 +0000 (13:56 +0000)]
ac/nir: implement 8-bit push constant, ssbo and ubo loads
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 13 Mar 2019 14:55:42 +0000 (15:55 +0100)]
ac: add ac_build_tbuffer_load_byte() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 13 Mar 2019 14:53:51 +0000 (15:53 +0100)]
ac: add various int8 definitions
Original patch by Rhys Perry.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tapani Pälli [Tue, 19 Mar 2019 09:01:53 +0000 (11:01 +0200)]
anv/radv: release memory allocated by glsl types during spirv_to_nir
Fixes leaks for each glsl_type generated:
==32470== 384 bytes in 3 blocks are possibly lost in loss record 18 of 18
==32470== at 0x483880B: malloc (vg_replace_malloc.c:309)
==32470== by 0x4C43F4A: ralloc_size (ralloc.c:119)
==32470== by 0x4C44014: rzalloc_size (ralloc.c:151)
==32470== by 0x4C44258: rzalloc_array_size (ralloc.c:215)
==32470== by 0x4D38957: glsl_type::glsl_type(glsl_struct_field const*, unsigned int, char const*) (glsl_types.cpp:114)
==32470== by 0x4D3BEED: glsl_type::get_struct_instance(glsl_struct_field const*, unsigned int, char const*) (glsl_types.cpp:1146)
==32470== by 0x4D42ECC: glsl_struct_type (nir_types.cpp:501)
==32470== by 0x4CDB5A1: vtn_handle_type (spirv_to_nir.c:1269)
==32470== by 0x4CE53DD: vtn_handle_variable_or_type_instruction (spirv_to_nir.c:4018)
==32470== by 0x4CD8CFF: vtn_foreach_instruction (spirv_to_nir.c:365)
==32470== by 0x4CE5E6B: spirv_to_nir (spirv_to_nir.c:4490)
==32470== by 0x497AF10: anv_shader_compile_to_nir (anv_pipeline.c:173)
v2: move release call to vkDestroyInstance
v3: apply fix also to radv driver
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Tue, 19 Mar 2019 19:14:17 +0000 (14:14 -0500)]
spirv: Drop inline tg4 lowering
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Jason Ekstrand [Tue, 19 Mar 2019 18:55:21 +0000 (13:55 -0500)]
anv,radv,turnip: Lower TG4 offsets with nir_lower_tex
v2: turn on for turnip as well (Karol Herbst)
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Karol Herbst [Tue, 19 Mar 2019 17:47:20 +0000 (18:47 +0100)]
nir/lower_tex: Add support for tg4 offsets lowering
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Karol Herbst [Mon, 18 Mar 2019 20:25:13 +0000 (21:25 +0100)]
nv50/ir/nir: support gather offsets
v2: only emit offsets if those are !0
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Karol Herbst [Mon, 18 Mar 2019 20:23:59 +0000 (21:23 +0100)]
nir: add support for gather offsets
Values inside the offsets parameter of textureGatherOffsets are required to be
constants in the range of [GL_MIN_PROGRAM_TEXTURE_GATHER_OFFSET,
GL_MAX_PROGRAM_TEXTURE_GATHER_OFFSET].
As this range is never outside [-32, 31] for all existing drivers inside mesa,
we can simply store the offsets as a int8_t[4][2] array inside nir_tex_instr.
Right now only Nvidia hardware supports this in hardware, so we can turn this
on inside Nouveau for the NIR path as it is already enabled with the TGSI one.
v2: use memcpy instead of for loops
add missing bits to nir_instr_set
don't show offsets if they are all 0
v3: default offsets aren't all 0
v4: rename offsets -> tg4_offsets
rename nir_tex_instr_has_explicit_offsets -> nir_tex_instr_has_explicit_tg4_offsets
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Dave Airlie [Tue, 5 Mar 2019 05:14:29 +0000 (15:14 +1000)]
nir/deref: remove casts of casts which are likely redundant (v3)
Not sure how ptr_stride should be taken into account if at all here
v2: reorder check to avoid src walking (Jason)
v3: remove is_cast_cast checks, keep going afterwards (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Tue, 19 Mar 2019 22:19:45 +0000 (08:19 +1000)]
nir/spirv: don't use bare types, remove assert in split vars for testing
For OpenCL we never want to strip the info from the types, and it makes
type comparisons easier in later stages. We might later need a nir pass to
strip this for GLSL, but so far the only regression is the assert and Jason
said removing that is fine.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Rafael Antognolli [Fri, 8 Mar 2019 18:58:41 +0000 (10:58 -0800)]
iris: Let blorp update the clear color for us.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Tue, 19 Mar 2019 19:47:58 +0000 (12:47 -0700)]
iris: Track fast clear color.
v2: Update tracked clear color when we update the surface state.
v3: Update all aux surface states when updating the clear color.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Thu, 7 Mar 2019 01:06:13 +0000 (17:06 -0800)]
iris: Stall on the CPU and resolve predication during fast clears.
Only if the clear color/depth is changing. In those cases, it's hard to
keep track of the current clear color, and aux state of some layers,
when predication is enabled. So simplify everything by stalling on the
few cases where we would have a fast clear color change with
predication.
v2:
- fix comment (Ken)
- explicitly check for predicate state after resolving it (Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Thu, 7 Mar 2019 00:59:44 +0000 (16:59 -0800)]
iris: Add iris_resolve_conditional_render().
This function can be used to stall on the CPU and resolve the predicate
for the conditional render. It will convert ice->state.predicate from
IRIS_PREDICATE_STATE_USE_BIT to either IRIS_PREDICATE_STATE_RENDER or
IRIS_PREDICATE_STATE_DONT_RENDER, depending on the result of the query.
v2:
- return void (Ken)
- update the stored condition (Ken)
- simplify the code leading to resolve the predicate (Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Wed, 20 Feb 2019 00:07:09 +0000 (16:07 -0800)]
iris: Implement fast clear color.
If all the restrictions are satisfied, do a fast clear instead of
regular clear.
v2:
- add perf_debug() when we can't fast clear (Ken)
- improve comment: s/miptree/resource/ (Ken)
- use swizzle_color_value from blorp (Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Wed, 20 Mar 2019 15:41:06 +0000 (08:41 -0700)]
intel/blorp: Make swizzle_color_value public.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Fri, 8 Mar 2019 22:01:58 +0000 (14:01 -0800)]
intel/isl: Add isl_format_has_color_component() function.
v2: Get luminance bits from luminance component (Ken).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Thu, 7 Mar 2019 16:23:08 +0000 (08:23 -0800)]
iris: Bring back check for srgb and fast clear color.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Fri, 1 Mar 2019 18:34:40 +0000 (10:34 -0800)]
iris: Add function to update clear color in surface state.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Thu, 28 Feb 2019 19:11:24 +0000 (11:11 -0800)]
iris: Add helper to convert fast clear color.
It needs to be converted to a value that can be used by ISL (and our
hardware SURFACE_STATE structure).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Tue, 26 Feb 2019 20:08:23 +0000 (12:08 -0800)]
iris: Fast clear depth buffers.
Check and do a fast clear instead of a regular clear on depth buffers.
v3:
- remove swith with some cases that we shouldn't wory about (Ken)
- more parens into the has_hiz check (Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Tue, 26 Feb 2019 20:02:35 +0000 (12:02 -0800)]
iris: Use the clear depth when emitting 3DSTATE_CLEAR_PARAMS.
Take the clear depth into account when IRIS_DIRTY_DEPTH_BUFFER is marked
as dirty.
Also update the blorp surface clear color.
v2: Use a single if (zres && zres->aux.bo) (Ken).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Fri, 15 Feb 2019 22:45:05 +0000 (14:45 -0800)]
iris: Allocate buffer space for the fast clear color.
Also store clear color in the iris_resource.
Always allocate clear color state buffer.
v2:
- Make clear_color_offset be 64 bits (Ken).
- Simplify the logic to decide when to memset the aux buffer (Ken).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bas Nieuwenhuizen [Tue, 19 Mar 2019 01:30:33 +0000 (02:30 +0100)]
radv: Implement VK_EXT_pipeline_creation_feedback.
Does what it says on the tin.
The per stage time is only an approximation due to linking and
the Vega merged stages.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Tue, 12 Mar 2019 13:07:16 +0000 (14:07 +0100)]
ac: use new LLVM 8 intrinsics in ac_build_buffer_store_dword()
New buffer intrinsics have a separate soffset parameter.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 13 Mar 2019 13:52:27 +0000 (14:52 +0100)]
ac: use new LLVM 8 intrinsic when storing 16-bit values
vindex is always 0.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 13 Mar 2019 13:48:53 +0000 (14:48 +0100)]
ac: add ac_build_{struct,raw}_tbuffer_store() helpers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 12 Mar 2019 10:18:34 +0000 (11:18 +0100)]
ac: use new LLVM 8 intrinsics in ac_build_buffer_load()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 12 Mar 2019 09:46:24 +0000 (10:46 +0100)]
ac/nir: use ac_build_buffer_store_dword() for SSBO store operations
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 12 Mar 2019 09:20:11 +0000 (10:20 +0100)]
ac/nir: use ac_build_buffer_load() for SSBO load operations
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 12 Mar 2019 08:21:59 +0000 (09:21 +0100)]
ac/nir: use new LLVM 8 intrinsics for SSBO atomic operations
Use the raw version (ie. IDXEN=0) because vindex is unused.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 12 Mar 2019 09:29:22 +0000 (10:29 +0100)]
ac/nir: remove one useless check in visit_store_ssbo()
Trivial.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 12 Mar 2019 11:13:37 +0000 (12:13 +0100)]
ac: add ac_build_buffer_store_format() helper
Similar to ac_build_buffer_load_format().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 12 Mar 2019 10:37:29 +0000 (11:37 +0100)]
ac/nir: set attrib flags for SSBO and image store operations
For consistency regarding other store operations.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 12 Mar 2019 10:27:13 +0000 (11:27 +0100)]
ac: make use of ac_get_store_intr_attribs() where possible
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dylan Baker [Wed, 20 Mar 2019 17:50:10 +0000 (10:50 -0700)]
bin/install_megadrivers.py: Correctly handle DESTDIR=''
Currently if destdir is set to '' then the resulting libdir will have
it's first character replaced by / instead of / being prepended to the
string. This was the result of ensuring that that DESTDIR wouldn't be
ignored if libdir was absolute, since the only cases that meson allows
the libdir to be absolute is if the prefix is /, this won't be a
problem.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110211
Fixes:
ae3f45c11e3f934939b90445471da8f18b057bc5
("bin/install_megadrivers: fix DESTDIR and -D*-path")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Juan A. Suarez Romero [Wed, 20 Mar 2019 19:20:27 +0000 (19:20 +0000)]
nir: deref only for OpTypePointer
Fixes dEQP-VK.binding_model.buffer_device_address.* and
dEQP-VK.ssbo.phys.layout* Vulkan CTS tests.
v2: set val->type->stride in the section below (Jason)
v3: restore val->type->type to original place (Jason)
Fixes:
d0ba326f238 ("nir/spirv: support physical pointers")
CC: Karol Herbst <kherbst@redhat.com>
CC: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Wed, 20 Mar 2019 03:11:40 +0000 (13:11 +1000)]
softpipe: fix texture view crashes
I noticed we crashed piglit arb_texture_view-rendering-formats
when run on softpipe.
This fixes the clear tiles to use the surface format not the
underlying storage format.
This fixes a bunch of srgb piglits as well.
Fixes:
396ac41fc28 (softpipe: add integer support)
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Kenneth Graunke [Wed, 20 Mar 2019 17:13:22 +0000 (10:13 -0700)]
nvc0: Skip new update barrier bits
I added new barrier bits in
220c1dce1e3194ea867e6d948fc7ff5b9ef2d3a7
and made most drivers skip them. I thought nvc0 was already skipping
those but missed the else case here, which does something. So make it
explicitly skip like I did everywhere else.
Thanks to Ilia for catching this.
Fixes:
220c1dce1e3 gallium: Add PIPE_BARRIER_UPDATE_BUFFER and UPDATE_TEXTURE bits.
Lionel Landwerlin [Tue, 19 Mar 2019 15:23:37 +0000 (15:23 +0000)]
anv: implement VK_EXT_pipeline_creation_feedback
An extension reporting cache hit in the user supplied pipeline cache
as well as timing information for creating the pipelines & stages.
v2: Don't consider no cache for cache hits (Jason)
Rework duration accumulation (Jason)
v3: Fold feedback creation writing into pipeline compile functions (Jason/Lionel)
v4: Get cache hit information from anv_device_search_for_kernel() (Jason)
Only set cache hit from the whole pipeline if all stages also have that bit (Lionel)
v5: Always user_cache_hit in anv_device_search_for_kernel() (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Wed, 20 Mar 2019 15:47:03 +0000 (11:47 -0400)]
freedreno/ir3/a6xx: fix ssbo comp_swap
One line left out of the conversion to ir3 ssbo intrinsics on a6xx.
Fixes:
2e4525883f0 ir3/compiler: Enable lower_io_offsets pass and handle new SSBO intrinsics
Signed-off-by: Rob Clark <robdclark@gmail.com>
Jason Ekstrand [Tue, 19 Mar 2019 19:14:02 +0000 (14:14 -0500)]
nir: Constant values are per-column not per-component
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Jason Ekstrand [Tue, 19 Mar 2019 15:47:34 +0000 (10:47 -0500)]
anv: Bump maxComputeWorkgroupInvocations
We initially set this lower because we didn't have SIMD32 support yet
but we've supported SIMD32 for quite some time now. We should bump it
up to the real limit.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Samuel Pitoiset [Tue, 5 Mar 2019 17:09:12 +0000 (18:09 +0100)]
radv: fix binding transform feedback buffers
The mask should be accumulated if two calls are used for
binding two buffers at different indexes. Otherwise, the
driver only accounts for the last one.
Noticed while glancing at this code.
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 19 Mar 2019 22:40:32 +0000 (23:40 +0100)]
ac: use llvm.amdgcn.fract intrinsic for nir_op_ffract
Noticed with a Doom shader.
29077 shaders in 15096 tests
Totals:
SGPRS:
1282125 ->
1282133 (0.00 %)
VGPRS: 908716 -> 908616 (-0.01 %)
Spilled SGPRs: 24811 -> 24779 (-0.13 %)
Code Size:
49048176 ->
48936488 (-0.23 %) bytes
Max Waves: 244232 -> 244226 (-0.00 %)
Totals from affected shaders:
SGPRS: 229584 -> 229592 (0.00 %)
VGPRS: 163268 -> 163168 (-0.06 %)
Spilled SGPRs: 8682 -> 8650 (-0.37 %)
Code Size:
12819572 ->
12707884 (-0.87 %) bytes
Max Waves: 24398 -> 24392 (-0.02 %)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Wed, 6 Mar 2019 04:43:11 +0000 (20:43 -0800)]
gallium: Add PIPE_BARRIER_UPDATE_BUFFER and UPDATE_TEXTURE bits.
The glMemoryBarrier() function makes shader memory stores ordered with
respect to things specified by the given bits. Until now, st/mesa has
ignored GL_TEXTURE_UPDATE_BARRIER_BIT and GL_BUFFER_UPDATE_BARRIER_BIT,
saying that drivers should implicitly perform the needed flushing.
This seems like a pretty big assumption to make. Instead, this commit
opts to translate them to new PIPE_BARRIER bits, and adjusts existing
drivers to continue ignoring them (preserving the current behavior).
The i965 driver performs actions on these memory barriers. Shader
memory stores go through a "data cache" which is separate from the
render cache and other read caches (like the texture cache). All
memory barriers need to flush the data cache (to ensure shader memory
stores are visible), and possibly invalidate read caches (to ensure
stale data is no longer visible). The driver implicitly flushes for
most caches, but not for data cache, since ARB_shader_image_load_store
introduced MemoryBarrier() precisely to order these explicitly.
I would like to follow i965's approach in iris, flushing the data cache
on any MemoryBarrier() call, so I need st/mesa to actually call the
pipe->memory_barrier() callback.
Fixes KHR-GL45.shader_image_load_store.advanced-sync-textureUpdate
and Piglit's spec/arb_shader_image_load_store/host-mem-barrier on
the iris driver.
Roland said this looks reasonable to him.
Reviewed-by: Eric Anholt <eric@anholt.net>
Tapani Pälli [Tue, 19 Mar 2019 09:30:58 +0000 (11:30 +0200)]
iris: mark switch case fallthrough
CID:
1444103
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tapani Pälli [Tue, 19 Mar 2019 09:17:18 +0000 (11:17 +0200)]
iris: initialize num_cbufs
Currently initialized only if 'ish' is non-NULL.
CID:
1444106
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Daniel Stone [Mon, 18 Mar 2019 16:07:00 +0000 (16:07 +0000)]
panfrost: Properly align stride
Handle buffers whose width is not aligned to 16px by padding the stride
and storing it accordingly.
This does not reject imports for images whose stride is not sufficiently
aligned.
v2: make sure bo->stride is set on imported buffers, and add missing
variable definition. (Tomeu)
Tested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Anuj Phogat [Thu, 24 Jan 2019 22:46:02 +0000 (14:46 -0800)]
anv/icl: Add WA_2204188704 to disable pixel shader panic dispatch
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Anuj Phogat [Thu, 24 Jan 2019 22:44:35 +0000 (14:44 -0800)]
i965/icl: Add WA_2204188704 to disable pixel shader panic dispatch
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Eric Engestrom [Fri, 8 Mar 2019 11:16:25 +0000 (11:16 +0000)]
gitlab-ci: drop most autotools builds
With autotools this close to being not supported anymore, let's not
waste half of the CI cycles on it. The default build will catch most
issues, and the rest can be tested by the old Travis.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Mon, 18 Mar 2019 20:49:08 +0000 (13:49 -0700)]
v3d: Expose the dma-buf modifiers query.
This allows DRI3 to pick between UIF and raster according to whether we're
pageflipping or not and whether the pageflipping display can do UIF,
avoiding copies for the windowed/composited case that previously was
forced to linear.
Improves windowed glmark2 -b build:use-vbo=false performance by 30.7783%
+/- 13.1719% (n=3)
Eric Anholt [Mon, 18 Mar 2019 21:19:36 +0000 (14:19 -0700)]
v3d: Allow the UIF modifier with renderonly.
We ask the other side to make a buffer with the right number of pages, and
then just store the UIF in it. This avoids an extra silent copy of the
buffer from linear to UIF if it gets used for texturing (X11 copy-based
swapbuffers, GL compositors).
Eric Anholt [Mon, 18 Mar 2019 21:25:06 +0000 (14:25 -0700)]
v3d: Always lay out shared tiled buffers with UIF_TOP set.
The samplers are already ready for this, we just needed to make sure that
layout chose UIF for level 0.
Andres Gomez [Fri, 8 Feb 2019 17:06:08 +0000 (19:06 +0200)]
Revert "glsl: relax input->output validation for SSO programs"
This reverts commit
1aa5738e666a9534c7e5b46f077327e6d647c64f.
This patch incorrectly asumed that for SSOs no inner interface
matching check was needed.
From the ARB_separate_shader_objects spec v.25:
" With separable program objects, interfaces between shader stages
may involve the outputs from one program object and the inputs
from a second program object. For such interfaces, it is not
possible to detect mismatches at link time, because the programs
are linked separately. When each such program is linked, all
inputs or outputs interfacing with another program stage are
treated as active. The linker will generate an executable that
assumes the presence of a compatible program on the other side of
the interface. If a mismatch between programs occurs, no GL error
will be generated, but some or all of the inputs on the interface
will be undefined."
This completes the fix from commit:
3be05dd2679 ("glsl/linker: don't fail non static used inputs without matching outputs")
Fixes:
1aa5738e666 ("glsl: relax input->output validation for SSO programs")
Cc: Tapani Pälli <tapani.palli@intel.com>
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Andres Gomez [Fri, 18 Jan 2019 16:33:10 +0000 (18:33 +0200)]
glsl/linker: simplify xfb_offset vs xfb_stride overflow check
Current implementation uses a complicated calculation which relies in
an implicit conversion to check the integral part of 2 division
results.
However, the calculation actually checks that the xfb_offset is
smaller or a multiplier of the xfb_stride. For example, while this is
expected to fail, it actually succeeds:
"
...
layout(xfb_buffer = 2, xfb_stride = 12) out block3 {
layout(xfb_offset = 0) vec3 c;
layout(xfb_offset = 12) vec3 d; // ERROR, requires stride of 24
};
...
"
Fixes:
2fab85aaea5 ("glsl: add xfb_stride link time validation")
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Andres Gomez [Thu, 27 Dec 2018 22:57:29 +0000 (00:57 +0200)]
glsl/linker: don't fail non static used inputs without matching outputs
If there is no Static Use of an input variable, the linker shouldn't
fail whenever there is no defined matching output variable in the
previous stage.
From page 47 (page 51 of the PDF) of the GLSL 4.60 v.5 spec:
" Only the input variables that are statically read need to be
written by the previous stage; it is allowed to have superfluous
declarations of input variables."
Now, we complete this exception whenever the input variable has an
explicit location. Previously,
18004c338f6 ("glsl: fail when a
shader's input var has not an equivalent out var in previous") took
care of the cases in which the input variable didn't have an explicit
location.
v2: do the location based interface matching check regardless on
whether it is a separable program or not (Ilia).
Fixes:
1aa5738e666 ("glsl: relax input->output validation for SSO programs")
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Cc: Iago Toral Quiroga <itoral@igalia.com>
Cc: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Cc: Ian Romanick <ian.d.romanick@intel.com>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Andres Gomez [Fri, 28 Dec 2018 10:24:53 +0000 (12:24 +0200)]
glsl/linker: always validate explicit location among inputs
Outputs are always validated when having explicit locations and we
were trusting its outcome to catch similar problems with the inputs
since, in case of having undefined outputs for existing inputs, we
would be already reporting a linker error.
However, consider this case:
" Shader stage n:
---------------
...
layout(location = 0) out float a;
...
Shader stage n+1:
-----------------
...
layout(location = 0) in float b;
layout(location = 0) in float c;
...
"
Currently, this won't report a linker error even though location
aliasing is happening for the inputs.
Therefore, we also need to validate the inputs independently from the
outcome of the outputs validation.
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Cc: Iago Toral Quiroga <itoral@igalia.com>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>