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Arnd Bergmann [Wed, 11 Jan 2017 14:29:48 +0000 (15:29 +0100)]
MIPS: Update defconfigs for NF_CT_PROTO_DCCP/UDPLITE change
In linux-4.10-rc, NF_CT_PROTO_UDPLITE and NF_CT_PROTO_DCCP are bool
symbols instead of tristate, and kernelci.org reports a bunch of
warnings for this, like:
arch/mips/configs/malta_kvm_guest_defconfig:63:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE
arch/mips/configs/malta_defconfig:62:warning: symbol value 'm' invalid for NF_CT_PROTO_DCCP
arch/mips/configs/malta_defconfig:63:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE
arch/mips/configs/ip22_defconfig:70:warning: symbol value 'm' invalid for NF_CT_PROTO_DCCP
arch/mips/configs/ip22_defconfig:71:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE
This changes all the MIPS defconfigs with these symbols to have them
built-in.
Fixes:
9b91c96c5d1f ("netfilter: conntrack: built-in support for UDPlite")
Fixes:
c51d39010a1b ("netfilter: conntrack: built-in support for DCCP")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14999/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Jaedon Shin [Tue, 10 Jan 2017 02:00:31 +0000 (11:00 +0900)]
MIPS: BMIPS: Add support SPI device nodes
Adds SPI device nodes to BCM7xxx MIPS based SoCs.
Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14990/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
James Hogan [Tue, 3 Jan 2017 14:51:20 +0000 (14:51 +0000)]
MIPS: Fix printk continuations in cpu-bugs64.c
64-bit pre-r6 kernels output the following broken printk continuation
lines during boot:
Checking for the multiply/shift bug...
no.
Checking for the daddiu bug...
no.
Checking for the daddi bug...
no.
Fix the printk continuations in cpu-bugs64.c to use pr_cont to restore
the correct output:
Checking for the multiply/shift bug... no.
Checking for the daddiu bug... no.
Checking for the daddi bug... no.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14916/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Ralf Baechle [Mon, 26 Dec 2016 18:57:52 +0000 (19:57 +0100)]
MIPS: zboot: Consolidate compiler flag filtering.
Al Viro noticed that we were using two different methods to filter out
flags from KBUILD_CFLAGS.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Reported-by: Al Viro <viro@zeniv.linux.org.uk>
Colin Ian King [Thu, 22 Dec 2016 23:52:58 +0000 (23:52 +0000)]
MIPS: ralink: Fix incorrect assignment on ralink_soc
ralink_soc sould be assigned to RT3883_SOC, replace incorrect
comparision with assignment.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Fixes:
418d29c87061 ("MIPS: ralink: Unify SoC id handling")
Cc: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14903/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Fri, 19 Aug 2016 17:13:36 +0000 (18:13 +0100)]
MIPS: sc-mips: L2 cache is inclusive of L1 dcache for CM3
In systems with CM3 & higher, the L2 cache is inclusive of the L1
dcache. Indicate this such that cpu_has_inclusive_pcaches evaluates true
and we avoid some unnecessary cache ops during DMA cache maintenance.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14018/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Fri, 19 Aug 2016 17:13:35 +0000 (18:13 +0100)]
MIPS: c-r4k: Treat physically indexed dcaches as not aliasing
Physically indexed caches cannot suffer from virtual aliasing, so clear
the MIPS_CACHE_ALIASES bit in order to ensure we don't do extra work
avoiding aliasing that cannot happen.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14017/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Fri, 19 Aug 2016 17:13:34 +0000 (18:13 +0100)]
MIPS: c-r4k: Treat I6400 dcache as though physically indexed
The L1 data cache in I6400 CPUs is indexed by physical address bits if
an entry for the address is present in the DTLB early enough in the
pipelined execution of a memory access instruction. If an entry is not
present then it's indexed by virtual address bits, but hardware will
check in a later pipeline stage when a DTLB entry has been created
whether the virtual address bits used match the physical address bits,
and if not will transparently restart the memory access instruction.
This means that although it isn't always physically indexed, it appears
so to software & we can treat the I6400 L1 data cache as being
physically indexed in order to avoid considering aliasing.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14016/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Kelvin Cheung [Fri, 12 Aug 2016 10:56:03 +0000 (18:56 +0800)]
MIPS: Loongson1B: Change the OSC clock name
This patch changes the OSC clock name to "osc_clk" as expected by all
clock users.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13903/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Fri, 2 Sep 2016 14:18:21 +0000 (15:18 +0100)]
MIPS: Netlogic: Fix assembler warning from smpboot.S
The netlogic platform can be built for either MIPS32 or MIPS64, and when
built for MIPS32 (as by nlm_xlr_defconfig) the use of the dla
pseudo-instruction leads to warnings such as the following from recent
versions of the GNU assembler:
arch/mips/netlogic/common/smpboot.S: Assembler messages:
arch/mips/netlogic/common/smpboot.S:62: Warning: dla used to load 32-bit register; recommend using la instead
arch/mips/netlogic/common/smpboot.S:63: Warning: dla used to load 32-bit register; recommend using la instead
Avoid these warnings by using the PTR_LA macro to make use of the
appropriate la or dla pseudo-instruction for the build.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes:
66d29985fab8 ("MIPS: Netlogic: Merge some of XLR/XLP wakup code")
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14185/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 11:14:16 +0000 (11:14 +0000)]
MIPS: Export {copy, clear}_page functions alongside their definitions
Now that EXPORT_SYMBOL can be used from assembly source, move the
EXPORT_SYMBOL invocations for the copy_page & clear_page functions to be
alongside their definitions.
With this change there are no longer any symbols exported from
mips_ksyms.c so remove the file.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14515/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 11:14:15 +0000 (11:14 +0000)]
MIPS: Export memcpy & memset functions alongside their definitions
Now that EXPORT_SYMBOL can be used from assembly source, move the
EXPORT_SYMBOL invocations for the memcpy & memset functions & variants
thereof to be alongside their definitions.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14514/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 11:14:14 +0000 (11:14 +0000)]
MIPS: Export string functions alongside their definitions
Now that EXPORT_SYMBOL can be used from assembly source, move the
EXPORT_SYMBOL invocations for the strlen*, strnlen* & strncpy* functions
to be alongside their definitions.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14513/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 11:14:13 +0000 (11:14 +0000)]
MIPS: Export csum functions alongside their definitions
Now that EXPORT_SYMBOL can be used from assembly source, move the
EXPORT_SYMBOL invocations for the csum_partial_* functions to be
alongside their definitions.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14512/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 11:14:12 +0000 (11:14 +0000)]
MIPS: Export invalid_pte_table alongside its definition
It's unclear to me why this wasn't always the case, but move the
EXPORT_SYMBOL invocation for invalid_pte_table to be alongside its
definition.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14511/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 11:48:04 +0000 (11:48 +0000)]
MIPS: Export _mcount alongside its definition
Now that EXPORT_SYMBOL can be used from assembly source, move the
EXPORT_SYMBOL invocation for _mcount to be alongside its definition.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14525/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 11:14:10 +0000 (11:14 +0000)]
MIPS: Export _save_fp & _save_msa alongside their definitions
Now that EXPORT_SYMBOL can be used from assembly source, move the
EXPORT_SYMBOL invocations for _save_fp & _save_msa to be alongside their
definitions.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 11:14:09 +0000 (11:14 +0000)]
MIPS: End asm function prologue macros with .insn
When building a kernel targeting a microMIPS ISA, recent GNU linkers
will fail the link if they cannot determine that the target of a branch
or jump is microMIPS code, with errors such as the following:
mips-img-linux-gnu-ld: arch/mips/built-in.o: .text+0x542c:
Unsupported jump between ISA modes; consider recompiling with
interlinking enabled.
mips-img-linux-gnu-ld: final link failed: Bad value
or:
./arch/mips/include/asm/uaccess.h:1017: warning: JALX to a
non-word-aligned address
Placing anything other than an instruction at the start of a function
written in assembly appears to trigger such errors. In order to prepare
for allowing us to follow function prologue macros with an EXPORT_SYMBOL
invocation, end the prologue macros (LEAD, NESTED & FEXPORT) with a
.insn directive. This ensures that the start of the function is marked
as code, which always makes sense for functions & safely prevents us
from hitting the link errors described above.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Maciej W. Rozycki <macro@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14508/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 11:14:08 +0000 (11:14 +0000)]
MIPS: tlbex: Clear ISA bit when writing to handle_tlb{l,m,s}
When generating TLB exception handling code we write to memory reserved
at the handle_tlbl, handle_tlbm & handle_tlbs symbols. Up until now the
ISA bit has always been clear simply because the assembly code reserving
the space for those functions places no instructions in them. In
preparation for marking all LEAF functions as containing code,
explicitly clear the ISA bit when calculating the addresses at which to
write TLB exception handling code.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14507/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 11:14:07 +0000 (11:14 +0000)]
MIPS: Use generic asm/export.h
Include export.h in the list of generic headers used by the MIPS
architecture for use by later patches.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14506/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Fri, 23 Sep 2016 15:38:27 +0000 (16:38 +0100)]
OF: Prevent unaligned access in of_alias_scan()
When allocating a struct alias_prop, of_alias_scan() only requested that
it be aligned on a 4 byte boundary. The struct contains pointers which
leads to us attempting 64 bit writes on 64 bit systems, and if the CPU
doesn't support unaligned memory accesses then this causes problems -
for example on some MIPS64r2 CPUs including the "mips64r2-generic" QEMU
emulated CPU it will trigger an address error exception.
Fix this by requesting alignment for the struct alias_prop allocation
matching that which the compiler expects, using the __alignof__ keyword.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Grant Likely <grant.likely@secretlab.ca>
Cc: Frank Rowand <frowand.list@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14306/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Ralf Baechle [Wed, 21 Dec 2016 02:32:50 +0000 (03:32 +0100)]
MIPS: IRQ: Remove useless i8259_of_init() prototype.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Tue, 13 Dec 2016 09:48:30 +0000 (10:48 +0100)]
MIPS: uprobes: Remove __weak attribute from arch_uprobe_copy_ixol.
Arch-specific implementation of arch_uprobe_copy_ixol is expected to
override the weak implementation in generic code.
As currently both implementations are marked as weak, it is up to the
linker to chose one. Remove the __weak attribute from MIPS code to make
sure the correct version is used.
Fixes:
40e084a506eb ("MIPS: Add uprobes support.")
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14660/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Tue, 20 Dec 2016 18:12:46 +0000 (19:12 +0100)]
MIPS: ralink: Cosmetic change to prom_init().
Over the years the code has been changed various times leading to
argc/argv being defined in a different function to where we actually
use the variables. Clean this up by moving them to prom_init_cmdline().
Signed-off-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14902/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Tue, 20 Dec 2016 18:12:45 +0000 (19:12 +0100)]
MIPS: ralink: Add missing symbol for highmem support.
MT7621 has highmem. this was previously not working as the required symbol
was not selected in the Kconfig file.
Signed-off-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14901/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Tue, 20 Dec 2016 18:12:44 +0000 (19:12 +0100)]
MIPS: ralink: Add missing clk_round_rate().
As we dont use the common clock api yet we need to add this stub to allow
building drivers that use the API.
Signed-off-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14900/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Tue, 20 Dec 2016 18:12:43 +0000 (19:12 +0100)]
MIPS: ralink: Fix a typo in the pinmux setup.
There is a typo inside the pinmux setup code. The function is really
called utif and not util. This was recently discovered when people were
trying to make the UTIF interface work.
Signed-off-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14899/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Tue, 20 Dec 2016 18:12:42 +0000 (19:12 +0100)]
MIPS: ralink: Add missing pinmux.
The mt7620 has a pin that can be used to generate an external reference
clock. The pinmux setup was missing the definition of said pin. This patch
adds it.
Signed-off-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14898/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Tue, 20 Dec 2016 18:12:41 +0000 (19:12 +0100)]
MIPS: ralink: Add missing I2C and I2S clocks.
This patch adds two additional clocks required by the audio interface of
the SoCs.
Signed-off-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14897/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
John Crispin [Tue, 20 Dec 2016 18:12:40 +0000 (19:12 +0100)]
MIPS: ralink: MT7621 does not set its SoC type.
The code does not set the SoC type properly. This went unnoticed until now
as the SoC does not share any of the driver code with the other SoCs, until
we made the mmc driver work.
Signed-off-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14896/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Justin Chen [Thu, 8 Dec 2016 01:16:26 +0000 (17:16 -0800)]
MIPS: Add cacheinfo support
Add cacheinfo support for MIPS architectures.
Use information from the cpuinfo_mips struct to populate the
cacheinfo struct. This allows an architecture agnostic approach,
however this also means if cache information is not properly
populated within the cpuinfo_mips struct, there is nothing
we can do. (I.E. c-r3k.c)
Signed-off-by: Justin Chen <justin.chen@broadcom.com>
Cc: f.fainelli@gmail.com
Cc: linux-mips@linux-mips.org
Cc: bcm-kernel-feedback-list@broadcom.com
Patchwork: https://patchwork.linux-mips.org/patch/14650/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Wed, 23 Nov 2016 13:43:52 +0000 (14:43 +0100)]
MIPS: generic/kexec: add support for a DTB passed in a separate buffer
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14615/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Wed, 23 Nov 2016 13:43:51 +0000 (14:43 +0100)]
MIPS: kexec: add debug info about the new kexec'ed image
Print details of the new kexec image loaded.
Based on the original code from
commit
221f2c770e10d ("arm64/kexec: Add pr_debug output")
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14614/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Wed, 23 Nov 2016 13:43:50 +0000 (14:43 +0100)]
MIPS: kexec: Do not reserve invalid crashkernel memory on boot
Do not reserve memory for the crashkernel if the commandline argument
points to a wrong location. This can happen if the location is specified
wrong or if the same commandline is reused when starting the crashkernel
- in the latter case the reserved memory would point to the location
from which the crashkernel is executing.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14612/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Wed, 23 Nov 2016 13:43:49 +0000 (14:43 +0100)]
MIPS: fix mem=X@Y commandline processing
When a memory offset is specified through the commandline, add the
memory in range PHYS_OFFSET:Y as reserved memory area.
Otherwise the bootmem allocator is initialised with low page equal to
min_low_pfn = PHYS_OFFSET, and in free_all_bootmem will process pages
starting from min_low_pfn instead of PFN(Y).
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14613/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Wed, 23 Nov 2016 13:43:48 +0000 (14:43 +0100)]
MIPS: relocate: Optionally relocate the DTB
If the DTB is located in the target memory area for the relocated kernel
it needs to be relocated as well before kernel relocation takes place.
After copying the DTB use the new plat_fdt_relocated() API from the
relocated kernel to ensure the relocated kernel updates any information
that it may have cached about the location of the DTB.
plat_fdt_relocated is declared as a weak symbol so that platforms that
do not require it do not need to implement the method.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14616/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Wed, 23 Nov 2016 13:43:47 +0000 (14:43 +0100)]
MIPS: platform: Allow for DTB to be moved during kernel relocation
Add plat_fdt_relocated(void*) API to allow the kernel relocation code to
update platform's information about the DTB location if the DTB had to
be moved due to being placed in a location used by the relocated kernel.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14611/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Wed, 23 Nov 2016 13:43:46 +0000 (14:43 +0100)]
MIPS: Use early_init_fdt_reserve_self to protect DTB location
early_init_fdt_reserve_self is used to tell the boot memory allocator
that a memory is occupied by the DTB, so add it in the MIPS init code to
ensure information about the DTB is added to the boot memory array.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14610/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Wed, 23 Nov 2016 13:43:45 +0000 (14:43 +0100)]
MIPS: init: Ensure bootmem does not corrupt reserved memory
Current init code initialises bootmem allocator with all of the low
memory that it assumes is available, but does not check for reserved
memory block, which can lead to corruption of data that may be stored
there.
Move bootmem's allocation map to a location that does not cross any
reserved regions
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14609/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Wed, 23 Nov 2016 13:43:44 +0000 (14:43 +0100)]
MIPS: init: Ensure reserved memory regions are not added to bootmem
Memories managed through boot_mem_map are generally expected to define
non-crossing areas. However, if part of a larger memory block is marked
as reserved, it would still be added to bootmem allocator as an
available block and could end up being overwritten by the allocator.
Prevent this by explicitly marking the memory as reserved it if exists
in the range used by bootmem allocator.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14608/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Wed, 23 Nov 2016 13:43:43 +0000 (14:43 +0100)]
MIPS: Do not request resources for crashkernel if one isn't defined
When KEXEC is enabled but crashkernel details are not passed through the
kernel commandline unnecessary resources are requested (start==end==0)
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14607/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Mon, 21 Nov 2016 10:23:39 +0000 (11:23 +0100)]
MIPS: elfcore: add correct copy_regs implementations
MIPS does not currently define ELF_CORE_COPY_REGS macros and as a result
the generic implementation is used. The generic version attempts to do
directly map (struct pt_regs) into (elf_gregset_t), which isn't correct
for MIPS platforms and also triggers a BUG() at runtime in
include/linux/elfcore.h:16 (BUG_ON(sizeof(*elfregs) != sizeof(*regs)))
[ralf@linux-mips.org: Add semicolons to the macro definitions as I do not
apply https://patchwork.linux-mips.org/patch/14588/ for now.]
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14586/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Mon, 21 Nov 2016 10:23:38 +0000 (11:23 +0100)]
MIPS: Move register dump routines out of ptrace code
Current register dump methods for MIPS are implemented inside ptrace
methods, but there will be other uses in the kernel for them, so keep
them separately in process.c and use those definitions for ptrace
instead.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14587/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Fri, 2 Dec 2016 08:58:29 +0000 (09:58 +0100)]
MIPS: Kconfig: Fix indentation for kexec-related entries
Kconfig entries are not aligned properly, so remove incorrect whitespace.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14631/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Marcin Nowakowski [Fri, 2 Dec 2016 08:58:28 +0000 (09:58 +0100)]
MIPS: kexec: remove SMP_DUMP
SMP_DUMP has been added as a new IPI signal when kexec support was added
for Cavium Octeon CPUs ('commit
7aa1c8f47e7e ("MIPS: kdump: Add support")'.
However, the new signal doesn't appear to ever have a proper handler
added (octeon_message_functions[] array has an empty handler for it),
and generic IPI handlers now trigger a BUG() on unhandled signal.
As the method is unused remove it completely and replace its only
invocation with a smp_call_function().
[ralf@linux-mips.org: Renumber SMP_ASK_C0COUNT to avoid numbering gaps.]
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14630/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Matt Redfearn [Thu, 24 Nov 2016 17:32:45 +0000 (17:32 +0000)]
MIPS: Add support for ARCH_MMAP_RND_{COMPAT_}BITS
arch_mmap_rnd() uses hard-coded limits of 16MB for the randomisation
of mmap within 32bit processes and 256MB in 64bit processes. Since v4.4
other arches support tuning this value in /proc/sys/vm/mmap_rnd_bits.
Add support for this to MIPS.
Set the minimum(default) number of bits randomisation for 32bit to 8 -
which with 4k pagesize is unchanged from the current 16MB total
randomness. The minimum(default) for 64bit is 12bits, again with 4k
pagesize this is the same as the current 256MB.
This patch is necessary for MIPS32 to pass the Android CTS tests, with
the number of random bits set to 15.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Daniel Cashman <dcashman@android.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: linux-mips@linux-mips.org
Cc: kernel-hardening@lists.openwall.com
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14617/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Hauke Mehrtens [Wed, 30 Nov 2016 22:58:08 +0000 (23:58 +0100)]
MIPS: Lantiq: Activate more drivers in default configuration
This activates the following functionalities:
* SMP support (used on xRX200)
* PCI support
* NAND driver
* PHY driver
* UART
* Watchdog
* USB 2.0 controller
These driver are driving different IP cores found on the supported SoCs.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14628/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Hauke Mehrtens [Wed, 30 Nov 2016 22:58:07 +0000 (23:58 +0100)]
MIPS: lantiq: Refresh default configuration
Just generate a configuration based on this default configuration and
store it again. This removed some old configuration options.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14629/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Tobias Wolf [Wed, 23 Nov 2016 09:40:07 +0000 (10:40 +0100)]
of: Add check to of_scan_flat_dt() before accessing initial_boot_params
An empty __dtb_start to __dtb_end section might result in
initial_boot_params being null for arch/mips/ralink. This showed that the
boot process hangs indefinitely in of_scan_flat_dt().
Signed-off-by: Tobias Wolf <dev-NTEO@vplace.de>
Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14605/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Tobias Wolf [Tue, 13 Dec 2016 10:46:41 +0000 (11:46 +0100)]
ralink: Introduce fw_passed_dtb to arch/mips/ralink
This patch adds fw_passed_dtb to arch/mips/ralink to support
CONFIG_MIPS_RAW_APPENDED_DTB. Furthermore it adds a check that __dtb_start is
not the same address as __dtb_end.
Signed-off-by: Tobias Wolf <dev-NTEO@vplace.de>
Acked-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14662/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Yang Ling [Sun, 4 Dec 2016 15:05:40 +0000 (23:05 +0800)]
MIPS: Loongson1: Add watchdog support for Loongson1 board
The patch adds watchdog support for Loongson1 board.
Signed-off-by: Yang Ling <gnaygnil@gmail.com>
Cc: keguang.zhang@gmail.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14644/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Yang Ling [Sun, 4 Dec 2016 14:57:03 +0000 (22:57 +0800)]
MIPS: Loongson1: Remove several redundant RTC-related macros
Move the RTC-related macros to regs-rtc.h.
Signed-off-by: Yang Ling <gnaygnil@gmail.com>
Cc: keguang.zhang@gmail.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14642/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 17 Oct 2016 14:34:38 +0000 (15:34 +0100)]
MIPS: Remove RESTORE_ALL_AND_RET
The RESTORE_ALL_AND_RET macro is never used. Remove the dead code.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14411/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 17 Oct 2016 14:34:37 +0000 (15:34 +0100)]
MIPS: Allow pre-r6 emulation on SMP MIPSr6 kernels
There's no reason for the pre-r6 instruction emulation code to be
limited to uniprocessor kernels. We already emulate atomic memory access
instructions in a way that works for SMP systems, and nothing else
should be affected. Remove the artificial limitation, allowing pre-r6
instruction emulation to be used with SMP kernels.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14410/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 17 Oct 2016 14:34:36 +0000 (15:34 +0100)]
MIPS: Cleanup LLBit handling in switch_to
Commit
7c151d3d5d7a ("MIPS: Make use of the ERETNC instruction on MIPS
R6") began clearing LLBit during context switches, but did so on all
systems where it is writable for unclear reasons & did so from a macro
with "software_ll_bit" in its name, which is intended to operate on the
ll_bit variable used by ll/sc emulation for old CPUs.
We do now need to clear LLBit on MIPSr6 systems where we'll use eretnc
to return to userland, but we don't need to do so on MIPSr5 systems with
a writable LLBit.
Move the clear to its own appropriately named macro, do it only for
MIPSr6 systems & comment about why.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14409/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 17 Oct 2016 14:34:35 +0000 (15:34 +0100)]
MIPS: Remove r2_emul_return from struct thread_info
The r2_emul_return field in struct thread_info was used in order to take
an alternate codepath when returning to userland, which (besides not
implementing certain features) effectively used the eretnc instruction
in place of eret. The difference is that eretnc doesn't clear LLBit, and
therefore doesn't cause a linked load & store sequence to fail due to
emulation like eret would.
The reason eret would usually be used to clear LLBit is so that after
context switching we ensure that a load performed by one task doesn't
influence another task. However commit
7c151d3d5d7a ("MIPS: Make use of
the ERETNC instruction on MIPS R6") which introduced the r2_emul_return
field and conditional use of eretnc also for some reason began
explicitly clearing LLBit during context switches - despite retaining
the use of eret for everything but returns from the pre-r6 instruction
emulation code.
As LLBit is cleared upon context switches anyway, simplify this by using
eretnc unconditionally for MIPSr6 kernels. This allows us to remove the
4 byte r2_emul_return boolean from struct thread_info, simplify the
return to user code in entry.S and avoid the overhead of tracking &
checking state which we don't need.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14408/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Rahul Bedarkar [Fri, 14 Oct 2016 05:55:55 +0000 (11:25 +0530)]
MIPS: DTS: img: add device tree for Marduk board
Add support for Imagination Technologies' Marduk board which is based
on Pistachio SoC. It is also known as Creator Ci40. Marduk is legacy
name and will be there for decades.
Documentation for this board can be found on
https://docs.creatordev.io/ci40/
This patch adds initial support for board with following peripherals:
* PWM based heartbeat LED
* GPIO based buttons
* SPI NOR flash on SPI1
* UART0 and UART1
* SD card
* Ethernet
* USB
* PWM
* ADC
* I2C
Signed-off-by: Rahul Bedarkar <rahul.bedarkar@imgtec.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: James Hartley <james.hartley@imgtec.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14394/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Rahul Bedarkar [Fri, 14 Oct 2016 05:55:54 +0000 (11:25 +0530)]
MIPS: DTS: Add base device tree for Pistachio SoC
Add support for the base Device Tree for Imagination Technologies'
Pistachio SoC.
This commit supports the following peripherals:
* Clocks
* Pinctrl and GPIO
* UART
* SPI
* I2C
* PWM
* ADC
* Watchdog
* Ethernet
* MMC
* DMA engine
* Crypto
* I2S
* SPDIF
* Internal DAC
* Timer
* USB
* IR
* Interrupt Controller
Signed-off-by: Rahul Bedarkar <rahul.bedarkar@imgtec.com>
Acked-by: James Hartley <james.hartley@imgtec.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14393/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 17 Oct 2016 15:01:07 +0000 (16:01 +0100)]
MIPS: traps: Ensure L1 & L2 ECC checking match for CM3 systems
On systems with CM3, we must ensure that the L1 & L2 ECC enables are set
to the same value. This is presumed by the hardware & cache corruption
can occur when it is not the case. Support enabling & disabling the L2
ECC checking on CM3 systems where this is controlled via a GCR, and
ensure that it matches the state of L1 ECC checking. Remove I6400 from
the switch statement it will no longer hit, and which was incorrect
since the L2 ECC enable bit isn't in the CP0 ErrCtl register.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14413/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Leonid Yegoshin [Thu, 25 Aug 2016 17:37:38 +0000 (10:37 -0700)]
MIPS: R2-on-R6 MULTU/MADDU/MSUBU emulation bugfix
MIPS instructions MULTU, MADDU and MSUBU emulation requires registers HI/LO
to be converted to signed 32bits before 64bit sign extension on MIPS64.
Bug was found on running MIPS32 R2 test application on MIPS64 R6 kernel.
Fixes:
b0a668fb2038 ("MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6")
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Reported-by: Nikola.Veljkovic@imgtec.com
Cc: paul.burton@imgtec.com
Cc: yamada.masahiro@socionext.com
Cc: akpm@linux-foundation.org
Cc: andrea.gelmini@gelma.net
Cc: macro@imgtec.com
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14043/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Kelvin Cheung [Tue, 9 Aug 2016 10:52:59 +0000 (18:52 +0800)]
MIPS: Loongson1B: Modify DEFAULT_MEMSIZE
This patch changes DEFAULT_MEMSIZE to 64MB
which is the memory size of latest EVB.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13856/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Kelvin Cheung [Tue, 9 Aug 2016 08:23:11 +0000 (16:23 +0800)]
MIPS: Loongson1C: Remove ARCH_WANT_OPTIONAL_GPIOLIB
This patch removes ARCH_WANT_OPTIONAL_GPIOLIB due to upstream changes.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Yang Ling <gnaygnil@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13855/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Florian Fainelli [Mon, 31 Oct 2016 21:17:36 +0000 (14:17 -0700)]
MIPS: BMIPS: Migrate interrupts during bmips_cpu_disable
While we properly disabled the per-CPU timer interrupt, we also need to
make sure that all interrupts that can possibly have this CPU in their
smp_affinity mask also have a chance to see this interrupt migrated to a
CPU not being taken offline.
[ralf@linux-mips.org: Fix merge conflict.]
Fixes:
230b6ff57552 ("MIPS: BMIPS: Mask off timer IRQs when hot-unplugging a CPU")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: cernekee@gmail.com
Cc: jaedon.shin@gmail.com
Cc: justinpopo6@gmail.com
Cc: tglx@linutronix.de
Cc: marc.zyngier@arm.com
Cc: jason@lakedaemon.net
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14488/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Zubair Lutfullah Kakakhel [Tue, 22 Nov 2016 17:52:43 +0000 (17:52 +0000)]
MIPS: xilfpga: Update defconfig
Update defconfig to enable emaclite, i2c and temp sensor on the
xilfpga platform
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14595/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Zubair Lutfullah Kakakhel [Tue, 22 Nov 2016 17:52:42 +0000 (17:52 +0000)]
MIPS: xilfpga: Add DT node for AXI emaclite
The xilfpga platform has a Xilinx AXI emaclite block.
Add the DT node to use it.
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14596/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Zubair Lutfullah Kakakhel [Tue, 22 Nov 2016 17:52:41 +0000 (17:52 +0000)]
MIPS: xilfpga: Add DT node for AXI I2C
The xilfpga platform has an AXI I2C Bus master with a temperature
sensor connected to it.
Add the device tree node to use them.
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14594/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Zubair Lutfullah Kakakhel [Tue, 22 Nov 2016 17:52:40 +0000 (17:52 +0000)]
MIPS: xilfpga: Update DT node and specify uart irq
Update the DT node with the UART irq
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14593/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Zubair Lutfullah Kakakhel [Tue, 22 Nov 2016 17:52:39 +0000 (17:52 +0000)]
MIPS: xilfpga: Use Xilinx Interrupt Controller
IRQs from peripherals such as i2c/uart/ethernet come via
the AXI Interrupt controller.
Select it in Kconfig for xilfpga and add the DT node
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14592/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Zubair Lutfullah Kakakhel [Tue, 22 Nov 2016 17:52:38 +0000 (17:52 +0000)]
MIPS: xilfpga: Use irqchip instead of the legacy way
This prepares the code to use the Xilinx Interrupt Controller
driver in drivers/irqchip/irq-xilinx-intc.c
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Cc: Zubair.Kakakhel@imgtec.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14591/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Christophe JAILLET [Sun, 30 Oct 2016 08:25:46 +0000 (09:25 +0100)]
MIPS: ath79: Fix error handling
'clk_register_fixed_rate()' returns an error pointer in case of error, not
NULL. So test it with IS_ERR.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Acked-by: Aban Bedel <albeu@free.fr>
Cc: antonynpavlov@gmail.com
Cc: hackpascal@gmail.com
Cc: amitoj1606@gmail.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: kernel-janitors@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14464/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Matt Redfearn [Fri, 4 Nov 2016 09:28:58 +0000 (09:28 +0000)]
MIPS: SMP-CPS: Don't BUG if a CPU fails to start
If there is no online CPU within a core which could receive the IPI to
start another VP in that core, a BUG() is triggered. Instead print a
warning and gracefully handle the failure such that the system remains
usable, albeit without the requested secondary CPU.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qsyousef@gmail.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14504/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Matt Redfearn [Fri, 4 Nov 2016 09:28:57 +0000 (09:28 +0000)]
MIPS: SMP: Remove cpu_callin_map
The previous commit made cpu_callin_map redundant, since it is no longer
used to signal secondary CPUs starting, or going offline. Remove it now.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: Qais Yousef <qsyousef@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Anna-Maria Gleixner <anna-maria@linutronix.de>
Cc: Adam Buchbinder <adam.buchbinder@gmail.com>
Cc: Yang Shi <yang.shi@windriver.com>
Cc: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14503/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Matt Redfearn [Fri, 4 Nov 2016 09:28:56 +0000 (09:28 +0000)]
MIPS: SMP: Use a completion event to signal CPU up
If a secondary CPU failed to start, for any reason, the CPU requesting
the secondary to start would get stuck in the loop waiting for the
secondary to be present in the cpu_callin_map.
Rather than that, use a completion event to signal that the secondary
CPU has started and is waiting to synchronise counters.
Since the CPU presence will no longer be marked in cpu_callin_map,
remove the redundant test from arch_cpu_idle_dead().
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Maciej W. Rozycki <macro@imgtec.com>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Chris Metcalf <cmetcalf@mellanox.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Qais Yousef <qsyousef@gmail.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14502/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 11:30:41 +0000 (11:30 +0000)]
MIPS: Netlogic: Exclude netlogic,xlp-pic code from XLR builds
Code in arch/mips/netlogic/common/irq.c which handles the XLP PIC fails
to build in XLR configurations due to cpu_is_xlp9xx not being defined,
leading to the following build failure:
arch/mips/netlogic/common/irq.c: In function ‘xlp_of_pic_init’:
arch/mips/netlogic/common/irq.c:298:2: error: implicit declaration
of function ‘cpu_is_xlp9xx’ [-Werror=implicit-function-declaration]
if (cpu_is_xlp9xx()) {
^
Although the code was conditional upon CONFIG_OF which is indirectly
selected by CONFIG_NLM_XLP_BOARD but not CONFIG_NLM_XLR_BOARD, the
failing XLR with CONFIG_OF configuration can be configured manually or
by randconfig.
Fix the build failure by making the affected XLP PIC code conditional
upon CONFIG_CPU_XLP which is used to guard the inclusion of
asm/netlogic/xlp-hal/xlp.h that provides the required cpu_is_xlp9xx
function.
[ralf@linux-mips.org: Fixed up as per Jayachandran's suggestion.]
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14524/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 11:28:12 +0000 (11:28 +0000)]
MIPS: Remove unused HIGHMEM_DEBUG macro
We have a HIGHMEM_DEBUG macro defined in asm/highmem.h with a comment
stating that it should be removed for production, and no users... Kill
it.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14523/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Matt Redfearn [Thu, 10 Nov 2016 10:02:13 +0000 (10:02 +0000)]
MIPS: Use Makefile.postlink to insert relocations into vmlinux
When relocatable support for MIPS was merged, there was no support for
an architecture to add a postlink step for vmlinux. This meant that only
invoking a target within the boot directory, such as uImage, caused the
relocations to be inserted into vmlinux. Building just the vmlinux
target would result in a relocatable kernel with no relocation
information present.
Commit
fbe6e37dab97 ("kbuild: add arch specific post-link Makefile")
recified this situation, so MIPS can now define a postlink step to add
relocation information into vmlinux, and remove the additional steps
tacked onto boot targets.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Tested-by: Steven J. Hill <steven.hill@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14554/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 15:07:07 +0000 (15:07 +0000)]
MIPS: Handle microMIPS jumps in the same way as MIPS32/MIPS64 jumps
is_jump_ins() checks for plain jump ("j") instructions since commit
e7438c4b893e ("MIPS: Fix sibling call handling in get_frame_info") but
that commit didn't make the same change to the microMIPS code, leaving
it inconsistent with the MIPS32/MIPS64 code. Handle the microMIPS
encoding of the jump instruction too such that it behaves consistently.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes:
e7438c4b893e ("MIPS: Fix sibling call handling in get_frame_info")
Cc: Tony Wu <tung7970@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # v3.10+
Patchwork: https://patchwork.linux-mips.org/patch/14533/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 15:07:06 +0000 (15:07 +0000)]
MIPS: Calculate microMIPS ra properly when unwinding the stack
get_frame_info() calculates the offset of the return address within a
stack frame simply by dividing a the bottom 16 bits of the instruction,
treated as a signed integer, by the size of a long. Whilst this works
for MIPS32 & MIPS64 ISAs where the sw or sd instructions are used, it's
incorrect for microMIPS where encodings differ. The result is that we
typically completely fail to unwind the stack on microMIPS.
Fix this by adjusting is_ra_save_ins() to calculate the return address
offset, and take into account the various different encodings there in
the same place as we consider whether an instruction is storing the
ra/$31 register.
With this we are now able to unwind the stack for kernels targetting the
microMIPS ISA, for example we can produce:
Call Trace:
[<
80109e1f>] show_stack+0x63/0x7c
[<
8011ea17>] __warn+0x9b/0xac
[<
8011ea45>] warn_slowpath_fmt+0x1d/0x20
[<
8013fe53>] register_console+0x43/0x314
[<
8067c58d>] of_setup_earlycon+0x1dd/0x1ec
[<
8067f63f>] early_init_dt_scan_chosen_stdout+0xe7/0xf8
[<
8066c115>] do_early_param+0x75/0xac
[<
801302f9>] parse_args+0x1dd/0x308
[<
8066c459>] parse_early_options+0x25/0x28
[<
8066c48b>] parse_early_param+0x2f/0x38
[<
8066e8cf>] setup_arch+0x113/0x488
[<
8066c4f3>] start_kernel+0x57/0x328
---[ end trace
0000000000000000 ]---
Whereas previously we only produced:
Call Trace:
[<
80109e1f>] show_stack+0x63/0x7c
---[ end trace
0000000000000000 ]---
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes:
34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.")
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # v3.10+
Patchwork: https://patchwork.linux-mips.org/patch/14532/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 15:07:05 +0000 (15:07 +0000)]
MIPS: Fix is_jump_ins() handling of 16b microMIPS instructions
is_jump_ins() checks 16b instruction fields without verifying that the
instruction is indeed 16b, as is done by is_ra_save_ins() &
is_sp_move_ins(). Add the appropriate check.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes:
34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.")
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # v3.10+
Patchwork: https://patchwork.linux-mips.org/patch/14531/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 15:07:04 +0000 (15:07 +0000)]
MIPS: Fix get_frame_info() handling of microMIPS function size
get_frame_info() is meant to iterate over up to the first 128
instructions within a function, but for microMIPS kernels it will not
reach that many instructions unless the function is 512 bytes long since
we calculate the maximum number of instructions to check by dividing the
function length by the 4 byte size of a union mips_instruction. In
microMIPS kernels this won't do since instructions are variable length.
Fix this by instead checking whether the pointer to the current
instruction has reached the end of the function, and use max_insns as a
simple constant to check the number of iterations against.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes:
34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.")
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # v3.10+
Patchwork: https://patchwork.linux-mips.org/patch/14530/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 15:07:03 +0000 (15:07 +0000)]
MIPS: Prevent unaligned accesses during stack unwinding
During stack unwinding we call a number of functions to determine what
type of instruction we're looking at. The union mips_instruction pointer
provided to them may be pointing at a 2 byte, but not 4 byte, aligned
address & we thus cannot directly access the 4 byte wide members of the
union mips_instruction. To avoid this is_ra_save_ins() copies the
required half-words of the microMIPS instruction to a correctly aligned
union mips_instruction on the stack, which it can then access safely.
The is_jump_ins() & is_sp_move_ins() functions do not correctly perform
this temporary copy, and instead attempt to directly dereference 4 byte
fields which may be misaligned and lead to an address exception.
Fix this by copying the instruction halfwords to a temporary union
mips_instruction in get_frame_info() such that we can provide a 4 byte
aligned union mips_instruction to the is_*_ins() functions and they do
not need to deal with misalignment themselves.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes:
34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.")
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # v3.10+
Patchwork: https://patchwork.linux-mips.org/patch/14529/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 15:07:02 +0000 (15:07 +0000)]
MIPS: Clear ISA bit correctly in get_frame_info()
get_frame_info() can be called in microMIPS kernels with the ISA bit
already clear. For example this happens when unwind_stack_by_address()
is called because we begin with a PC that has the ISA bit set & subtract
the (odd) offset from the preceding symbol (which does not have the ISA
bit set). Since get_frame_info() unconditionally subtracts 1 from the PC
in microMIPS kernels it incorrectly misaligns the address it then
attempts to access code at, leading to an address error exception.
Fix this by using msk_isa16_mode() to clear the ISA bit, which allows
get_frame_info() to function regardless of whether it is provided with a
PC that has the ISA bit set or not.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes:
34c2f668d0f6 ("MIPS: microMIPS: Add unaligned access support.")
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # v3.10+
Patchwork: https://patchwork.linux-mips.org/patch/14528/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 17 Oct 2016 14:56:21 +0000 (15:56 +0100)]
MIPS: Use generic asm/unaligned.h
The MIPS-specific asm/unaligned.h provides nothing that the generic
version doesn't - it simply uses MIPS-specific endianness macros in
place of generic ones & lacks support for
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS. Remove it & switch to using the
generic version to remove duplication.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14412/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Mon, 7 Nov 2016 11:52:19 +0000 (11:52 +0000)]
MIPS: Ensure bss section ends on a long-aligned address
When clearing the .bss section in kernel_entry we do so using LONG_S
instructions, and branch whilst the current write address doesn't equal
the end of the .bss section minus the size of a long integer. The .bss
section always begins at a long-aligned address and we always increment
the write pointer by the size of a long integer - we therefore rely upon
the .bss section ending at a long-aligned address. If this is not the
case then the long-aligned write address can never be equal to the
non-long-aligned end address & we will continue to increment past the
end of the .bss section, attempting to zero the rest of memory.
Despite this requirement that .bss end at a long-aligned address we pass
0 as the end alignment requirement to the BSS_SECTION macro and thus
don't guarantee any particular alignment, allowing us to hit the error
condition described above.
Fix this by instead passing 8 bytes as the end alignment argument to
the BSS_SECTION macro, ensuring that the end of the .bss section is
always at least long-aligned.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14526/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Steven J. Hill [Fri, 9 Dec 2016 08:36:22 +0000 (02:36 -0600)]
MIPS: Relocatable: Provide plat_post_relocation hook
This hook provides the platform the chance to perform any required
setup before the boot processor switches to the relocated kernel.
The relocated kernel has been copied and fixed up ready for execution
at this point. Secondary CPUs may wish to switch to it early. There
is also the opportunity for the platform to abort jumping to the
relocated kernel if there is anything wrong with the chosen offset.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14651/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Steven J. Hill [Tue, 13 Dec 2016 20:25:37 +0000 (14:25 -0600)]
MIPS: Octeon: Enable KASLR
This patch enables KASLR for Octeon systems. The SMP startup code is
such that the secondaries monitor the volatile variable
'octeon_processor_relocated_kernel_entry' for any non-zero value.
The 'plat_post_relocation hook' is used to set that value to the
kernel entry point of the relocated kernel. The secondary CPUs will
then jusmp to the new kernel, perform their initialization again
and begin waiting for the boot CPU to start them via the relocated
loop 'octeon_spin_wait_boot'. Inspired by Steven's code from Cavium.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Acked-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14669/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Steven J. Hill [Tue, 22 Nov 2016 19:44:20 +0000 (13:44 -0600)]
MIPS: Octeon: Add plat_get_fdt() function for Cavium platforms.
Add in the function needed for Octeon platforms to support KASLR.
Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Steven J. Hill [Tue, 22 Nov 2016 19:44:10 +0000 (13:44 -0600)]
MIPS: Octeon: Add fw_init_cmdline() for Cavium platforms.
Add platform-specific kernel command line processing for Octeon.
Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14599/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Matt Redfearn [Mon, 19 Dec 2016 14:21:00 +0000 (14:21 +0000)]
MIPS: Select HAVE_IRQ_EXIT_ON_IRQ_STACK
Since do_IRQ is now invoked on a separate IRQ stack, we select
HAVE_IRQ_EXIT_ON_IRQ_STACK so that softirq's may be invoked directly
from irq_exit(), rather than requiring do_softirq_own_stack.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Acked-by: Jason A. Donenfeld <jason@zx2c4.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14744/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Matt Redfearn [Mon, 19 Dec 2016 14:20:59 +0000 (14:20 +0000)]
MIPS: Switch to the irq_stack in interrupts
When enterring interrupt context via handle_int or except_vec_vi, switch
to the irq_stack of the current CPU if it is not already in use.
The current stack pointer is masked with the thread size and compared to
the base or the irq stack. If it does not match then the stack pointer
is set to the top of that stack, otherwise this is a nested irq being
handled on the irq stack so the stack pointer should be left as it was.
The in-use stack pointer is placed in the callee saved register s1. It
will be saved to the stack when plat_irq_dispatch is invoked and can be
restored once control returns here.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Acked-by: Jason A. Donenfeld <jason@zx2c4.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14743/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Matt Redfearn [Mon, 19 Dec 2016 14:20:58 +0000 (14:20 +0000)]
MIPS: Only change $28 to thread_info if coming from user mode
The SAVE_SOME macro is used to save the execution context on all
exceptions.
If an exception occurs while executing user code, the stack is switched
to the kernel's stack for the current task, and register $28 is switched
to point to the current_thread_info, which is at the bottom of the stack
region.
If the exception occurs while executing kernel code, the stack is left,
and this change ensures that register $28 is not updated. This is the
correct behaviour when the kernel can be executing on the separate irq
stack, because the thread_info will not be at the base of it.
With this change, register $28 is only switched to it's kernel
conventional usage of the currrent thread info pointer at the point at
which execution enters kernel space. Doing it on every exception was
redundant, but OK without an IRQ stack, but will be erroneous once that
is introduced.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Acked-by: Jason A. Donenfeld <jason@zx2c4.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14742/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Matt Redfearn [Mon, 19 Dec 2016 14:20:57 +0000 (14:20 +0000)]
MIPS: Stack unwinding while on IRQ stack
Within unwind stack, check if the stack pointer being unwound is within
the CPU's irq_stack and if so use that page rather than the task's stack
page.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Acked-by: Jason A. Donenfeld <jason@zx2c4.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Adam Buchbinder <adam.buchbinder@gmail.com>
Cc: Maciej W. Rozycki <macro@imgtec.com>
Cc: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
Cc: Chris Metcalf <cmetcalf@mellanox.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14741/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Matt Redfearn [Mon, 19 Dec 2016 14:20:56 +0000 (14:20 +0000)]
MIPS: Introduce irq_stack
Allocate a per-cpu irq stack for use within interrupt handlers.
Also add a utility function on_irq_stack to determine if a given stack
pointer is within the irq stack for that cpu.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Acked-by: Jason A. Donenfeld <jason@zx2c4.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Chris Metcalf <cmetcalf@mellanox.com>
Cc: Petr Mladek <pmladek@suse.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Aaron Tomlin <atomlin@redhat.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14740/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Ralf Baechle [Thu, 15 Dec 2016 11:39:22 +0000 (12:39 +0100)]
MIPS: IP22: Fix build error due to binutils 2.25 uselessnes.
Fix the following build error with binutils 2.25.
CC arch/mips/mm/sc-ip22.o
{standard input}: Assembler messages:
{standard input}:132: Error: number (0x9000000080000000) larger than 32 bits
{standard input}:159: Error: number (0x9000000080000000) larger than 32 bits
{standard input}:200: Error: number (0x9000000080000000) larger than 32 bits
scripts/Makefile.build:293: recipe for target 'arch/mips/mm/sc-ip22.o' failed
make[1]: *** [arch/mips/mm/sc-ip22.o] Error 1
MIPS has used .set mips3 to temporarily switch the assembler to 64 bit
mode in 64 bit kernels virtually forever. Binutils 2.25 broke this
behavious partially by happily accepting 64 bit instructions in .set mips3
mode but puking on 64 bit constants when generating 32 bit ELF. Binutils
2.26 restored the old behaviour again.
Fix build with binutils 2.25 by open coding the offending
dli $1, 0x9000000080000000
as
li $1, 0x9000
dsll $1, $1, 48
which is ugly be the only thing that will build on all binutils vintages.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: stable@vger.kernel.org
Ralf Baechle [Thu, 15 Dec 2016 11:27:21 +0000 (12:27 +0100)]
MIPS: IP22: Reformat inline assembler code to modern standards.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Bolle [Fri, 25 Nov 2016 12:36:18 +0000 (13:36 +0100)]
MIPS: Zboot: Don't use $(LINUXINCLUDE) twice
The make variables KBUILD_CFLAGS and KBUILD_AFLAGS both contain
$(LINUXINCLUDE). But the build already picks up $(LINUXINCLUDE) from
scripts/Makefile.lib. The net effect is that the (long) list of include
directories is used twice.
This is harmless but pointless. So stop using $(LINUXINCLUDE) twice.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14622/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Geert Uytterhoeven [Wed, 7 Dec 2016 09:05:15 +0000 (10:05 +0100)]
MIPS: TXx9: Modernize printing of kernel messages
- Convert from printk() to pr_*(),
- Add missing continuations, to fix user-visible breakage,
- Drop superfluous casts (u64 has been unsigned long long on all
architectures for many years).
On rbtx4927, this restores the kernel output like:
-TX4927 SDRAMC --
- CR0:
0000007e00000544
- TR:
32800030e
+TX4927 SDRAMC -- CR0:
0000007e00000544 TR:
32800030e
and:
-PCIC -- PCICLK:
-Internal(33.3MHz)
-
+PCIC -- PCICLK:Internal(33.3MHz)
Fixes:
4bcc595ccd80decb ("printk: reinstate KERN_CONT for printing continuation lines")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14646/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Aaro Koskinen [Sun, 27 Nov 2016 00:30:51 +0000 (02:30 +0200)]
MIPS: Octeon: Kill cvmx_helper_link_autoconf()
Kill cvmx_helper_link_autoconf(). Nobody uses this function.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14626/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Julia Lawall [Sat, 29 Oct 2016 19:36:59 +0000 (21:36 +0200)]
MIPS: TXx9: 7segled: use permission-specific DEVICE_ATTR variants
Use DEVICE_ATTR_WO for write only attributes. This simplifies the
source code, improves readbility, and reduces the chance of
inconsistencies.
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@wo@
declarer name DEVICE_ATTR;
identifier x,x_store;
@@
DEVICE_ATTR(x, \(0200\|S_IWUSR\), NULL, x_store);
@script:ocaml@
x << wo.x;
x_store << wo.x_store;
@@
if not (x^"_store" = x_store) then Coccilib.include_match false
@@
declarer name DEVICE_ATTR_WO;
identifier wo.x,wo.x_store;
@@
- DEVICE_ATTR(x, \(0200\|S_IWUSR\), NULL, x_store);
+ DEVICE_ATTR_WO(x);
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: kernel-janitors@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14463/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Maarten ter Huurne [Mon, 31 Oct 2016 14:19:55 +0000 (15:19 +0100)]
MIPS: zboot: Add "uzImage.bin" target
uzImage.bin is vmlinuz.bin wrapped in a legacy U-Boot image. Since
the extraction code is inside the image, it does not depend on the
boot loader to extract the kernel.
Signed-off-by: Maarten ter Huurne <maarten@treewalker.org>
Cc: Alban Bedel <albeu@free.fr>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14473/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>