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Treehugger Robot [Fri, 22 Jul 2016 16:53:29 +0000 (16:53 +0000)]
Merge "ARM64/x86-64: Fix mterp fill-array-data-payload pointer calculation."
Vladimir Marko [Fri, 22 Jul 2016 09:52:24 +0000 (10:52 +0100)]
ARM64/x86-64: Fix mterp fill-array-data-payload pointer calculation.
Fix the pointer calculation to sign-extend the offset
instead of zero-extending it, just like we do for the switch
table pointer calculation. Clean up comments for the switch.
Test: Additional test in 412-new-array.
Change-Id: Ibb1d2d3fcb109f59280aca08de21e42edc4ce66b
Vladimir Marko [Fri, 22 Jul 2016 09:24:41 +0000 (09:24 +0000)]
Merge "ARM64: Improve mterp cmpl/cmpg."
Treehugger Robot [Thu, 21 Jul 2016 23:58:00 +0000 (23:58 +0000)]
Merge changes I295c7876,Ib4b84b7b
* changes:
ART: Remove PACKED from ArtMethod's ptr_sized_fields_
ART: Rename ArtMethod JNI field
Hiroshi Yamauchi [Thu, 21 Jul 2016 23:24:44 +0000 (23:24 +0000)]
Merge "Use non-CAS thread flip root visitor."
Andreas Gampe [Wed, 20 Jul 2016 01:27:17 +0000 (18:27 -0700)]
ART: Remove PACKED from ArtMethod's ptr_sized_fields_
Remove the PACKED(4) hack, as it's highly annoying when debugging
a 64-bit process. Instead, fix the actual offset and size computation
for cross-size accesses.
Test: m test-art-host
Change-Id: I295c78760b74b6a62946e76856f218b4eb159cdc
Hiroshi Yamauchi [Thu, 21 Jul 2016 03:25:27 +0000 (20:25 -0700)]
Use non-CAS thread flip root visitor.
We don't need to use CAS to update the thread-local GC roots for the
thread flip.
Bug:
12687968
Bug:
29517059
Test: libartd.so boot. ART tests. Ritzperf EAAC.
Change-Id: Ia2acab824f756bd7d2ad501b2040233e0d394356
Andreas Gampe [Tue, 19 Jul 2016 15:06:07 +0000 (08:06 -0700)]
ART: Rename ArtMethod JNI field
The field is multi-purpose, rename it to data and clean up
accessors in preparation of more checks.
Test: m test-art-host
Change-Id: Ib4b84b7b1a51ca201544bc488ce8770aa858c7fd
Treehugger Robot [Thu, 21 Jul 2016 18:26:27 +0000 (18:26 +0000)]
Merge "ART: Make run-test temp dir consistent"
Andreas Gampe [Thu, 21 Jul 2016 04:09:29 +0000 (21:09 -0700)]
ART: Make run-test temp dir consistent
We use the username as a directory component in run-test. Use the
same when driven through the Makefile.
Drop the username in run-test when TMP_DIR is set.
Test: m test-art-host-run-test
Test: art/test/run-test --host 001-HelloWorld
Change-Id: I060997ffbd80cd4da30dd6ac8d3954641de3292b
Mathieu Chartier [Thu, 21 Jul 2016 16:52:44 +0000 (16:52 +0000)]
Merge "Add a way to measure read barrier slow paths"
Vladimir Marko [Thu, 21 Jul 2016 11:59:46 +0000 (12:59 +0100)]
ARM64: Improve mterp cmpl/cmpg.
Use CSET+CNEG instead of MOV+CNEG+CSEL. Prefer the
CNEG/CSET alias over the CSNEG/CSINC for readability.
Test: Run ART test suite on Nexus 9 with the interpreter.
Change-Id: I5c4fb0cf2c053904253e8e82f3e7e05c774b0583
Treehugger Robot [Thu, 21 Jul 2016 14:19:33 +0000 (14:19 +0000)]
Merge "Change return type of artIsAssignableFromCode for MIPS64"
Roland Levillain [Thu, 21 Jul 2016 14:17:40 +0000 (14:17 +0000)]
Merge "Fix the definition of MACRO_LITERAL for OS X on x86-64."
Roland Levillain [Tue, 5 Jul 2016 17:55:32 +0000 (18:55 +0100)]
Fix the definition of MACRO_LITERAL for OS X on x86-64.
Test: "ART_USE_READ_BARRIER=true mmma art" on OS X.
Change-Id: Ia2d4c7a3eb7fec346ddfa4c7b0f7b700f1137344
Goran Jakovljevic [Thu, 21 Jul 2016 12:21:46 +0000 (14:21 +0200)]
Change return type of artIsAssignableFromCode for MIPS64
This has been missed by Ic505befc6c94e2dccbc8abf2b13d4c2d662e68d1.
This fixes MIPS64 build.
Bug:
30232671
Test: make -j 32 out/target/product/generic_mips64/obj/SHARED_LIBRARIES/libart_intermediates/arch/mips64/entrypoints_init_mips64.o
Change-Id: Iec89d25e2d38c6efc0d1025767d0ac2a8bdb7dcd
Roland Levillain [Thu, 21 Jul 2016 12:11:15 +0000 (12:11 +0000)]
Merge "Move caller-saves saving/restoring to ReadBarrierMarkRegX."
Vladimir Marko [Thu, 21 Jul 2016 10:33:13 +0000 (10:33 +0000)]
Merge "Clean up Class::FindStaticField()."
Roland Levillain [Wed, 20 Jul 2016 10:32:19 +0000 (11:32 +0100)]
Move caller-saves saving/restoring to ReadBarrierMarkRegX.
Instead of saving/restoring live caller-save registers
before/after the call to read barrier mark entry points
ReadBarrierMarkRegX, have these entry points save/restore
all the caller-save registers themselves (except register
rX, which contains the return value).
Also refactor the assembly code of these entry points
using macros.
* Boot image code size variation on Nexus 5X
(aosp_bullhead-userdebug build):
- total ARM64 framework Oat files size change:
119196792 bytes ->
115575920 bytes (-3.04%)
- total ARM framework Oat files size change:
100435212 bytes ->
97621188 bytes (-2.80%)
* Benchmarks (ARM64) score variations on Nexus 5X
(aosp_bullhead-userdebug build):
- RitzPerf (lower is better)
- average score difference: -2.71%
- CaffeineMark (higher is better)
- no real difference for most tests
(absolute variation lower than 1%)
- better score on the "Method" benchmark:
score variation 41253 -> 44891 (+8.82%)
Test: ART host and target (ARM, ARM64) tests.
Bug:
29506760
Bug:
12687968
Change-Id: I881bf73139a3f1c2bee9ffc6fc8c00f9a392afa6
Vladimir Marko [Thu, 21 Jul 2016 09:17:15 +0000 (09:17 +0000)]
Merge "ARM: Port instr simplification of array accesses."
Artem Serov [Wed, 6 Jul 2016 15:23:04 +0000 (16:23 +0100)]
ARM: Port instr simplification of array accesses.
After changing the addressing mode for array accesses (in
https://android-review.googlesource.com/248406) the 'add'
instruction that calculates the base address for the array can be
shared across accesses to the same array.
Before https://android-review.googlesource.com/248406:
add IP, r[Array], r[Index0], LSL #2
ldr r0, [IP, #12]
add IP, r[Array], r[Index1], LSL #2
ldr r0, [IP, #12]
Before this CL:
add IP. r[Array], #12
ldr r0, [IP, r[Index0], LSL #2]
add IP. r[Array], #12
ldr r0, [IP, r[Index1], LSL #2]
After this CL:
add IP. r[Array], #12
ldr r0, [IP, r[Index0], LSL #2]
ldr r0, [IP, r[Index1], LSL #2]
Link to the original optimization:
https://android-review.googlesource.com/#/c/127310/
Test: Run ART test suite on Nexus 6.
Change-Id: Iee26f9a0a7ca46abb90e3f60d19d22dc8dee4d8f
Vladimir Marko [Thu, 21 Jul 2016 09:15:23 +0000 (09:15 +0000)]
Merge changes Ibcc11ce7,I9867dc11
* changes:
ARM64: Improve Mterp.
ARM64: Fix mterp switch table pointer calculation.
Mathieu Chartier [Thu, 14 Jul 2016 20:30:03 +0000 (13:30 -0700)]
Add a way to measure read barrier slow paths
If enabled, this option counts number of slow paths, measures the
total slow path time per GC and records the info into a histogram.
Also added support for systrace to see which threads are performing
slow paths.
Added runtime option -Xgc:measure to enable. The info is dumped
for SIGQUIT.
Test: Volantis boot with CC, test-art-host with CC, run EEAC with CC
and -Xgc:measure
Bug:
30162165
Change-Id: I3c2bdb4156065249c45695f13c77c0579bc8e57a
Treehugger Robot [Thu, 21 Jul 2016 00:04:52 +0000 (00:04 +0000)]
Merge "Revert "Revert "Refactor GetIMTIndex"""
Treehugger Robot [Wed, 20 Jul 2016 22:08:47 +0000 (22:08 +0000)]
Merge "Make stream tracing have a higher thread count on host"
Alex Light [Wed, 20 Jul 2016 17:43:39 +0000 (10:43 -0700)]
Make stream tracing have a higher thread count on host
Test: mma ART_TEST_TRACE_STREAM=true -j40 test-art-host-run-test-debug-prebuild-optimizing-relocate-stream-cms-checkjni-image-npictest-ndebuggable-001-HelloWorld32
Bug:
30229615
Change-Id: Id396f569b9e21ff764562005624aabc964d4e95a
Treehugger Robot [Wed, 20 Jul 2016 20:38:30 +0000 (20:38 +0000)]
Merge "Refactor register allocation to be pluggable"
Treehugger Robot [Wed, 20 Jul 2016 19:42:28 +0000 (19:42 +0000)]
Merge "Fix accidental pass-by-value"
Treehugger Robot [Wed, 20 Jul 2016 18:22:10 +0000 (18:22 +0000)]
Merge changes I328ea51d,I577c5d02
* changes:
Compute oat and odex filenames eagerly.
Make a static OatFileAssistant::DexLocationToOatFileName function.
Vladimir Marko [Wed, 20 Jul 2016 13:25:30 +0000 (14:25 +0100)]
ARM64: Improve Mterp.
Several straight-forward optimizations:
- use ubfx instead of SHR+AND,
- do not mask shifting distance,
- use 64-bit LDRSH to avoid subsequent sign extension,
- use CBNZ instead of CMP+BNE for null checks,
- style: use SXTW alias instead of explicit SBFM.
Test: Run ART test suite on Nexus 9 with the interpreter.
Change-Id: Ibcc11ce7f455432ecb789f727da21f269f8370f0
Vladimir Marko [Wed, 20 Jul 2016 16:52:51 +0000 (17:52 +0100)]
ARM64: Fix mterp switch table pointer calculation.
Do not mix 32-bit and 64-bit registers with
add x0, xPC, w0, lsl #1
that ends up compiled as
add x0, xPC, w0, uxtx #1
instead of the required sxtx. Just sing-extend the offset
correctly in previous instructions.
Test: Additional test in 501-regression-packed-switch.
Change-Id: I9867dc1180743e98f9707a312241d2f5b726ca8c
Matthew Gharrity [Wed, 20 Jul 2016 17:13:45 +0000 (10:13 -0700)]
Fix accidental pass-by-value
Change-Id: I245111eabb43368875c1215ca4f3a1f1918492fe
Matthew Gharrity [Thu, 14 Jul 2016 20:24:00 +0000 (13:24 -0700)]
Refactor register allocation to be pluggable
Allow alternate register allocation strategies to be implemented
in subclasses of a common register allocation base class.
Test: m test-art-host
Change-Id: I7c5866aa9ddff8f53fcaf721bad47654ab221b4f
Vladimir Marko [Wed, 20 Jul 2016 12:01:15 +0000 (12:01 +0000)]
Merge "ART: Change return types of field access entrypoints"
Nicolas Geoffray [Wed, 20 Jul 2016 10:53:11 +0000 (10:53 +0000)]
Merge "Fix test after rename."
Nicolas Geoffray [Wed, 20 Jul 2016 10:49:47 +0000 (11:49 +0100)]
Fix test after rename.
bug:
29964720
Change-Id: I37cebc40ca83597b159eefbc492e8cc105996306
Andreas Gampe [Wed, 20 Jul 2016 05:34:53 +0000 (22:34 -0700)]
ART: Change return types of field access entrypoints
Ensure that return types guarantee full-width data as the compiled
code and mterp expect by using size_t and ssize_t.
This fixes Clang no longer sign-/zero-extending small return types.
Bug:
30232671
Test: m ART_TEST_RUN_TEST_NDEBUG=true ART_TEST_INTERPRETER=true test-art-host-run-test
Change-Id: Ic505befc6c94e2dccbc8abf2b13d4c2d662e68d1
Nicolas Geoffray [Wed, 20 Jul 2016 10:30:09 +0000 (10:30 +0000)]
Merge "JIT: Don't update the dex cache of another class loader."
Vladimir Marko [Wed, 20 Jul 2016 09:20:55 +0000 (09:20 +0000)]
Merge "ARM: Change mem address mode for array accesses."
Artem Serov [Mon, 11 Jul 2016 13:02:34 +0000 (14:02 +0100)]
ARM: Change mem address mode for array accesses.
Switch from:
add IP, r[Array], r[Index], LSL #2
ldr r0, [IP, #12]
To:
add IP. r[Array], #12
ldr r0, [IP, r[Index], LSL #2]
These is a base for the future TryExtractArrayAccessAddress
optimization port to arm.
Test: aosp_shamu-userdebug boots and passes "m test-art-target".
Change-Id: I6ab01ba3271a8f79599ddd91a6b63cd1b37d2d67
Treehugger Robot [Wed, 20 Jul 2016 00:02:38 +0000 (00:02 +0000)]
Merge "Refactor SSA deconstruction into its own class"
Treehugger Robot [Tue, 19 Jul 2016 22:07:57 +0000 (22:07 +0000)]
Merge "Tune the GC ergnomics for the read barrier config."
Stephen Hines [Tue, 19 Jul 2016 22:02:31 +0000 (22:02 +0000)]
Merge "Disable warnings triggered in Clang r271374"
Matthew Gharrity [Tue, 19 Jul 2016 21:32:52 +0000 (21:32 +0000)]
Revert "Revert "Refactor GetIMTIndex""
Originally reverted in order to revert
https://android-review.googlesource.com/#/c/244190/
but can now be merged again.
This reverts commit
d4ceecc85a5aab2ec23ea1bd010692ba8c8aaa0c.
Test: m test-art-host
Change-Id: Id9205f2b77a378fc0f06088e78c66e81a49f712d
Matthew Gharrity [Mon, 18 Jul 2016 20:38:44 +0000 (13:38 -0700)]
Refactor SSA deconstruction into its own class
Test: m test-art-host
Change-Id: Ie82c2802f76f27512ef922ba583caeccf5675063
Pirama Arumuga Nainar [Tue, 28 Jun 2016 17:51:10 +0000 (10:51 -0700)]
Disable warnings triggered in Clang r271374
http://b/
28149048
http://b/
29823425
Disable -Wconstant-conversion and -Wundefined-var-template. The second
bug above tracks that these warnings get reenabled.
Test: Tested build, boot and common usage for Arm, Arm64, x86, x86_64,
Mips images in AOSP and internal branch.
Change-Id: Iea20cf6b5dbec3247b55cf8130f88202e786e367
Hiroshi Yamauchi [Tue, 19 Jul 2016 00:07:26 +0000 (17:07 -0700)]
Tune the GC ergnomics for the read barrier config.
Add 1.0 to the heap growth multiplier for the read barrier config, which
reduces the GC frequency down to roughly the same as CMS in one of the
jank tests.
Bug:
29517059
Bug:
12687968
Test: ART run-tests.
Change-Id: I1302a2f17e862f152d2f92bc06a65c9e6defcba0
Nicolas Geoffray [Tue, 19 Jul 2016 16:06:23 +0000 (17:06 +0100)]
JIT: Don't update the dex cache of another class loader.
This only works for properly delegating class loaders. But Java allows
non-delegating ones :(
bug:
29964720
Change-Id: I8b785e6cdfe9a2b77322521a02b8e59ec332ad83
test:612-jit-dex-cache
Richard Uhler [Tue, 19 Apr 2016 20:24:41 +0000 (13:24 -0700)]
Compute oat and odex filenames eagerly.
Because we almost always need both of them anyway, and they aren't
expensive to compute.
Test: oat file assistant tests.
Change-Id: I328ea51da6eb8700329f829a0458b02e12d1ee9e
Richard Uhler [Tue, 19 Apr 2016 20:08:04 +0000 (13:08 -0700)]
Make a static OatFileAssistant::DexLocationToOatFileName function.
So that you can figure out an oat file name without instantiating an
OatFileAssistant object.
Test: oat file assistant tests.
Change-Id: I577c5d02225f926086e9833d45b88d8a92db52fa
Vladimir Marko [Tue, 19 Jul 2016 12:37:33 +0000 (12:37 +0000)]
Merge "ARM: Fix shifted register offset mem address mode for load signed."
Artem Serov [Mon, 11 Jul 2016 13:00:46 +0000 (14:00 +0100)]
ARM: Fix shifted register offset mem address mode for load signed.
For example 'ldrsh r0, [sp, r1, LSL #2]' previously
was assembled as 'ldrh'.
Test: New test in assembler_thumb2_test.cc .
Change-Id: I1d30724f0c2745b131876bffefdc0a780d76f6a1
Treehugger Robot [Mon, 18 Jul 2016 22:53:44 +0000 (22:53 +0000)]
Merge "Do allocation fence before pushing on allocation stack"
Mathieu Chartier [Mon, 18 Jul 2016 18:11:45 +0000 (11:11 -0700)]
Do allocation fence before pushing on allocation stack
Heap::VisitObjects relies on having valid classes for objects in
the allocation stack. If the writes reorder, the thread calling
VisitObjects could see the free list pointer instead of the class
of the object. I believe this is causing crashes in VisitObjects.
Bug:
28790624
Test: Volantis booted
Change-Id: I0f2d4097de1ef3f5caf670ecc977d4d6837872ca
Treehugger Robot [Mon, 18 Jul 2016 19:35:11 +0000 (19:35 +0000)]
Merge "Rename current register allocator implementation"
Treehugger Robot [Mon, 18 Jul 2016 18:49:56 +0000 (18:49 +0000)]
Merge "ART: Fix run-test script"
Andreas Gampe [Sat, 25 Jun 2016 05:30:29 +0000 (22:30 -0700)]
ART: Fix run-test script
Don't assume out is under BUILD_TOP.
Test: run-test with OUT_DIR_COMMON_BASE set
Change-Id: Iba408e807e6a15ff60de54d6d4d653814d4b11d0
Roland Levillain [Mon, 18 Jul 2016 15:40:34 +0000 (15:40 +0000)]
Merge "MIPS64: Highest/Lowest Bit Intrinsic Support"
Roland Levillain [Mon, 18 Jul 2016 15:07:19 +0000 (15:07 +0000)]
Merge "Fix the build with respect to new VIXL."
Roland Levillain [Mon, 18 Jul 2016 15:03:05 +0000 (16:03 +0100)]
Fix the build with respect to new VIXL.
Test: Build ART for ARM64.
Change-Id: I2a9ebf145c61db9f8ceec6616963bac3ad5a7eb9
Roland Levillain [Mon, 18 Jul 2016 14:28:05 +0000 (14:28 +0000)]
Merge "Fixes to build against new VIXL interface."
Nicolas Geoffray [Mon, 18 Jul 2016 12:16:46 +0000 (12:16 +0000)]
Merge "Add a new control flow simplifier."
Treehugger Robot [Mon, 18 Jul 2016 11:19:14 +0000 (11:19 +0000)]
Merge "ARM64: Improve code generated to spill/restore for slow paths."
Alexandre Rames [Fri, 15 Jul 2016 16:41:13 +0000 (17:41 +0100)]
ARM64: Improve code generated to spill/restore for slow paths.
Aligning the accesses allows generating better code.
Before:
add x16, sp, #0x44 (68)
stp x0, x1, [x16, #-16]
After:
stp x0, x1, [sp, #56]
Change-Id: I3e20ad3fa59d00aee4b4d14ea9d59c7cd546509e
Nicolas Geoffray [Fri, 15 Jul 2016 09:46:17 +0000 (10:46 +0100)]
Add a new control flow simplifier.
Run it in the dead code elimination phase, as it relates to
creating dead branches.
From 0.04 to 0.07% less code size framework/gms/docs/fb (70K saved on fb)
3%-5% runtime performance improvements on Richards/DeltaBlue/Ritz.
Compile-time is mixed, so in the noise (from 2% slower to 1% faster).
test:611-checker-simplify-if
Change-Id: Ife8b7882d57b5481f5ca9dc163beba655d7e78bf
Treehugger Robot [Sat, 16 Jul 2016 04:46:46 +0000 (04:46 +0000)]
Merge "ART: Replace ScopedFd with FdFile"
Andreas Gampe [Sat, 16 Jul 2016 00:17:34 +0000 (17:17 -0700)]
ART: Replace ScopedFd with FdFile
FdFile can now be used like ScopedFd. Remove ScopedFd.
Bug:
21192156
Test: m test-art-host
Test: m test-art-target (shamu)
Change-Id: I32115fa8b2b8bb5aa5d1886eae63522f80ce836b
Matthew Gharrity [Thu, 14 Jul 2016 21:08:16 +0000 (14:08 -0700)]
Rename current register allocator implementation
This will allow a cleaner commit in an upcoming
refactoring of register allocation.
Test: m test-art-host
Change-Id: If420c97b088b3c934411ff83373e024003120746
Treehugger Robot [Fri, 15 Jul 2016 16:40:28 +0000 (16:40 +0000)]
Merge "ART: disassembler_x86 doesn't recognize NOPs"
Scott Wakeling [Fri, 24 Jun 2016 15:19:36 +0000 (16:19 +0100)]
Fixes to build against new VIXL interface.
- Fix namespace usage and use of deprecated functions.
- Link all dependants to new libvixl-arm64 target for now.
Change-Id: Iee6f299784fd663fc2a759f3ee816fdbc511e509
Andreas Gampe [Fri, 15 Jul 2016 00:45:22 +0000 (00:45 +0000)]
Merge changes from topic 'cherry_pinner'
* changes:
ART: Fix build break
Add API for getting location of odex or oat file
Andreas Gampe [Thu, 14 Jul 2016 23:50:52 +0000 (16:50 -0700)]
ART: Fix build break
Build break introduced by mismatch from merges.
Bug:
28251566
(cherry picked from commit
a472e4fd6260740af230bab7be5740d8c7bac360)
Test: m test-art-host
Change-Id: I83a333dd7394af630c5a79153d4838eb3a910714
Philip Cuadra [Tue, 12 Jul 2016 23:37:40 +0000 (16:37 -0700)]
Add API for getting location of odex or oat file
Add an API for getting the file path of odex or oat file given a dex
path.
Bug
28251566
(cherry picked from commit
b4827ace453b9280060a826e8f22cc8c9b6edb7d)
Change-Id: Ibebaa20f15d8135b25d9eb5927b7979801ebf0b2
Treehugger Robot [Thu, 14 Jul 2016 21:09:55 +0000 (21:09 +0000)]
Merge "Revert "Revert "Dump more dex file data in oatdump"""
Mathieu Chartier [Thu, 14 Jul 2016 17:10:44 +0000 (10:10 -0700)]
Revert "Revert "Dump more dex file data in oatdump""
Delete runtime to fix leak before callin exit.
Bug:
29462018
This reverts commit
9c05578dd2306231437bd290c0f70abc2bb3b6d8.
Change-Id: Ica23ba0f2d07496d0e4a3288329945f612ac3b20
Treehugger Robot [Thu, 14 Jul 2016 19:44:38 +0000 (19:44 +0000)]
Merge "Integer.bitCount and Long.bitCount intrinsics for ARM"
Treehugger Robot [Thu, 14 Jul 2016 18:48:03 +0000 (18:48 +0000)]
Merge "ART: Add FdFile constructors"
xueliang.zhong [Tue, 5 Jul 2016 14:28:19 +0000 (15:28 +0100)]
Integer.bitCount and Long.bitCount intrinsics for ARM
Change-Id: I4ed3e779415be026c7d090b61a3e356b37c418e5
Roland Levillain [Thu, 14 Jul 2016 09:32:34 +0000 (09:32 +0000)]
Merge "Introduce more compact ReadBarrierMark slow-paths."
Nicolas Geoffray [Thu, 14 Jul 2016 09:24:45 +0000 (09:24 +0000)]
Merge "Revert "Dump more dex file data in oatdump""
Nicolas Geoffray [Thu, 14 Jul 2016 09:24:30 +0000 (09:24 +0000)]
Revert "Dump more dex file data in oatdump"
Breaks valgrind.
Bug:
29462018
This reverts commit
8e2c56252aa9527bd9a82bdd147fdc46cf5deb9c.
Change-Id: If58cedcee75dd0eda8571e90d63e080a4709d773
Nicolas Geoffray [Thu, 14 Jul 2016 07:56:16 +0000 (07:56 +0000)]
Merge "Fix a bug in ClassTableGet code generation for IMTs."
Andreas Gampe [Thu, 13 Aug 2015 23:44:54 +0000 (16:44 -0700)]
ART: Add FdFile constructors
Make Open protected, and expose constructors instead. Add a move
constructor and move assignment operator.
Add OS functions that return the FdFile non-pointer version.
Add tests.
Bug:
21192156
Test: m test-art-host
Test: m test-art-target (shamu)
Change-Id: I83e390edde7cd37c900e9d5c3e4d21da22981b3f
Treehugger Robot [Wed, 13 Jul 2016 21:35:59 +0000 (21:35 +0000)]
Merge "Dump more dex file data in oatdump"
Mathieu Chartier [Tue, 21 Jun 2016 22:14:20 +0000 (15:14 -0700)]
Dump more dex file data in oatdump
Dump some statistics for each dex file along side with strings loaded
from code and dex code bytes.
Sample output:
Cumulative dex file data
Num string ids: 202809
Num method ids: 320464
Num field ids: 162822
Num type ids: 68151
Num class defs: 48061
Unique strings loaded from dex code: 51049
Total strings loaded from dex code: 106651
Number of unique dex code items: 247929
Total number of dex code bytes:
11090574
Added content testing to oat dump test. No significant slowdown.
TEST: test-art-host
Bug:
29462018
Change-Id: I60effd3087d8c427eda4ee26431d5d77165b3939
Treehugger Robot [Wed, 13 Jul 2016 18:07:04 +0000 (18:07 +0000)]
Merge "Improve search for available spill slots in RA"
Treehugger Robot [Wed, 13 Jul 2016 17:55:52 +0000 (17:55 +0000)]
Merge "Refactored a few dexdump alloc/free into unique_ptr"
Vladimir Marko [Wed, 13 Jul 2016 16:37:34 +0000 (16:37 +0000)]
Merge "X86: Use memory to do array range checks"
Treehugger Robot [Wed, 13 Jul 2016 15:42:18 +0000 (15:42 +0000)]
Merge changes I91249ba8,Ic93812d9
* changes:
Use "" to indicate the oat filename could not be computed.
Compute and cache oat file status in OatFileAssistant.
Nicolas Geoffray [Wed, 13 Jul 2016 13:13:48 +0000 (14:13 +0100)]
Fix a bug in ClassTableGet code generation for IMTs.
Introduced by:
https://android-review.googlesource.com/#/c/244980/
test:566-polymorphic-inling for fixing x86 crash. Also
fixes a performance regression.
bug:
29188168
Change-Id: Id90cb819c88e7ba3db1cb3c50c517a112ab7d784
Mark Mendell [Tue, 12 Jul 2016 15:13:15 +0000 (11:13 -0400)]
X86: Use memory to do array range checks
Currently, an HBoundsCheck is fed by an HArrayLength, causing a load of
the array length, followed by a register compare.
Avoid the load when we can by comparing directly with the array length
in memory. Implement this by marking the HArrayLength as 'emitted at
use site', and then generating the code in the HBoundsCheck.
Only do this replacement when we are the only user of the ArrayLength
and it isn't visible to the environment.
Handle the special case where the array is 'null' and where an implicit
null check can't be eliminated.
This code moves the load of the length to the slow code for the failed
check, which is what we want.
Test: 609-checker-x86-bounds-check
Change-Id: I9cdb183301e048234bb0ffeda940eedcf4a655bd
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Roland Levillain [Wed, 13 Jul 2016 10:54:35 +0000 (11:54 +0100)]
Introduce more compact ReadBarrierMark slow-paths.
Replace entry point ReadBarrierMark with 32
ReadBarrierMarkRegX entry points, using register
number X as input and output (instead of the standard
runtime calling convention) to save two moves in Baker's
read barrier mark slow-path code.
Test: ART host and target (ARM, ARM64) tests.
Bug:
29506760
Bug:
12687968
Change-Id: I73cfb82831cf040b8b018e984163c865cc44ed87
Nicolas Geoffray [Wed, 13 Jul 2016 09:19:45 +0000 (09:19 +0000)]
Merge "Blacklist flaky test."
Nicolas Geoffray [Wed, 13 Jul 2016 09:18:48 +0000 (10:18 +0100)]
Blacklist flaky test.
bug:
30107038
Change-Id: Id976c6c7d764a44c1b30155714fb64b4441cdac2
Treehugger Robot [Wed, 13 Jul 2016 00:35:48 +0000 (00:35 +0000)]
Merge "Update the get_process_name call."
Aart Bik [Tue, 12 Jul 2016 22:53:13 +0000 (15:53 -0700)]
Refactored a few dexdump alloc/free into unique_ptr
Rationale: easier to read
Test: dexdump's output is well-tested
Change-Id: Ib5b36dce68d442e555599f9427bd9bfa7c6f3831
Treehugger Robot [Tue, 12 Jul 2016 18:32:29 +0000 (18:32 +0000)]
Merge changes Iafd12677,I40595d15
* changes:
profile_changed should not effect GetBestOatFile.
Make OpenImageSpace static and ArtFileName internal.
Matthew Gharrity [Mon, 11 Jul 2016 21:45:01 +0000 (14:45 -0700)]
Improve search for available spill slots in RA
Previously we always searched for two adjacent spill slots, even if
we only needed one. This small change fixes that.
Test: m test-art-host
Change-Id: I021d355e6602ffee687c8537a959232b1504dcf1
Vladimir Marko [Tue, 12 Jul 2016 15:02:31 +0000 (15:02 +0000)]
Merge "ARM64: Shorter fast-path for read barrier field load."
Vladimir Marko [Tue, 12 Jul 2016 14:14:26 +0000 (14:14 +0000)]
Merge "Two more patterns for instruction simplifier"