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Yonghong Song [Mon, 11 Sep 2017 23:43:35 +0000 (23:43 +0000)]
bpf: add " ll" in the LD_IMM64 asmstring
This partially revert previous fix in commit
f5858045aa0b
("bpf: proper print imm64 expression in inst printer").
In that commit, the original suffix "ll" is removed from
LD_IMM64 asmstring. In the customer print method, the "ll"
suffix is printed if the rhs is an immediate. For example,
"r2 = 5ll" => "r2 = 5ll", and "r3 = varll" => "r3 = var".
This has an issue though for assembler. Since assembler
relies on asmstring to do pattern matching, it will not
be able to distiguish between "mov r2, 5" and
"ld_imm64 r2, 5" since both asmstring is "r2 = 5".
In such cases, the assembler uses 64bit load for all
"r = <val>" asm insts.
This patch adds back " ll" suffix for ld_imm64 with one
additional space for "#reg = #global_var" case.
Signed-off-by: Yonghong Song <yhs@fb.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312978
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Adrian Prantl [Mon, 11 Sep 2017 23:40:44 +0000 (23:40 +0000)]
Update testcases that are XFAILed on Darwin for llvm-dwarfdump changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312977
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Vedant Kumar [Mon, 11 Sep 2017 23:32:30 +0000 (23:32 +0000)]
[llvm-cov] Try to fix a test on Windows
Failing bot:
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/4791
This looks like another stderr redirection issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312975
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Adrian Prantl [Mon, 11 Sep 2017 23:05:20 +0000 (23:05 +0000)]
llvm-dwarfdump: Make -brief the default and add a -verbose option instead.
Differential Revision: https://reviews.llvm.org/D37717
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312972
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Eugene Zelenko [Mon, 11 Sep 2017 23:00:48 +0000 (23:00 +0000)]
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312971
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Adrian Prantl [Mon, 11 Sep 2017 22:59:45 +0000 (22:59 +0000)]
llvm-dwarfdump: Replace -debug-dump=sect option with individual options.
As discussed on llvm-dev in
http://lists.llvm.org/pipermail/llvm-dev/2017-September/117301.html
this changes the command line interface of llvm-dwarfdump to match the
one used by the dwarfdump utility shipping on macOS. In addition to
being shorter to type this format also has the advantage of allowing
more than one section to be specified at the same time.
In a nutshell, with this change
$ llvm-dwarfdump --debug-dump=info
$ llvm-dwarfdump --debug-dump=apple-objc
becomes
$ dwarfdump --debug-info --apple-objc
Differential Revision: https://reviews.llvm.org/D37714
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312970
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Eli Friedman [Mon, 11 Sep 2017 22:56:20 +0000 (22:56 +0000)]
[llvm-cov] Allow hiding instantiation/region coverage from summary tables
Region coverage is difficult to explain without going deep into how
coverage is implemented. Instantiation coverage is easier to explain,
but probably not useful in most cases (templates don't exist in C, and
most C++ code contains relatively few templates).
This patch adds the options "-show-region-summary" and
"-show-instantiation-summary" to allow hiding those columns.
"-show-instantiation-summary" is turned off by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312969
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Peter Collingbourne [Mon, 11 Sep 2017 22:49:10 +0000 (22:49 +0000)]
LowerTypeTests: Add import/export support for targets without absolute symbol constants.
The rationale is the same as for r312967.
Differential Revision: https://reviews.llvm.org/D37408
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312968
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Peter Collingbourne [Mon, 11 Sep 2017 22:34:42 +0000 (22:34 +0000)]
WholeProgramDevirt: Add import/export support for targets without absolute symbol constants.
Not all targets support the use of absolute symbols to export
constants. In particular, ARM has a wide variety of constant encodings
that cannot currently be relocated by linkers. So instead of exporting
the constants using symbols, export them directly in the summary.
The values of the constants are left as zeroes on targets that support
symbolic exports.
This may result in more cache misses when targeting those architectures
as a result of arbitrary changes in constant values, but this seems
somewhat unavoidable for now.
Differential Revision: https://reviews.llvm.org/D37407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312967
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Vedant Kumar [Mon, 11 Sep 2017 21:31:32 +0000 (21:31 +0000)]
[llvm-cov] Don't attach exec counts to lines which start a skipped region
These lines by definition don't have an execution count.
This is the final part of the fix for:
https://bugs.llvm.org/show_bug.cgi?id=34166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312955
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Sanjay Patel [Mon, 11 Sep 2017 20:38:31 +0000 (20:38 +0000)]
[InstSimplify] fix some test names; NFC
Too much division...the quotient is the answer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312943
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Sanjay Patel [Mon, 11 Sep 2017 19:42:41 +0000 (19:42 +0000)]
[InstSimplify] add tests for possible sdiv/srem simplifications; NFC
As noted in PR34517, the handling of signed div/rem is not on par with
unsigned div/rem. Signed is harder to reason about, but it should be
possible to handle at least some of these using the same technique that
we use for unsigned: use icmp logic to see if there's a relationship
between the quotient and divisor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312938
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Matt Arsenault [Mon, 11 Sep 2017 18:54:20 +0000 (18:54 +0000)]
AMDGPU: Allow coldcc calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312936
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Petar Jovanovic [Mon, 11 Sep 2017 18:34:04 +0000 (18:34 +0000)]
[mips][microMIPS] add lapc instruction
Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6.
Patch by Milos Stojanovic.
Differential Revision: https://reviews.llvm.org/D35984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312934
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Hiroshi Yamauchi [Mon, 11 Sep 2017 17:52:08 +0000 (17:52 +0000)]
Unmerge GEPs to reduce register pressure on IndirectBr edges.
Summary:
GEP merging can sometimes increase the number of live values and register
pressure across control edges and cause performance problems particularly if the
increased register pressure results in spills.
This change implements GEP unmerging around an IndirectBr in certain cases to
mitigate the issue. This is in the CodeGenPrepare pass (after all the GEP
merging has happened.)
With this patch, the Python interpreter loop runs faster by ~5%.
Reviewers: sanjoy, hfinkel
Reviewed By: hfinkel
Subscribers: eastig, junbuml, llvm-commits
Differential Revision: https://reviews.llvm.org/D36772
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312930
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Stanislav Mekhanoshin [Mon, 11 Sep 2017 17:13:57 +0000 (17:13 +0000)]
[AMDGPU] Produce madak and madmk from the two-address pass
These two instructions are normally selected, but when the
two address pass converts mac into mad we end up with the
mad where we could have one of these.
Differential Revision: https://reviews.llvm.org/D37389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312928
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Craig Topper [Mon, 11 Sep 2017 16:16:48 +0000 (16:16 +0000)]
[X86] Remove portions of r275950 that are no longer needed with i1 not being a legal type
Summary:
r275950 added support for turning (trunc (X >> N) to i1) into BT(X, N). But that's no longer necessary now that i1 isn't legal.
This patch removes the support for that, but preserves some of the refactorings done in that commit.
Reviewers: guyblank, RKSimon, spatel, zvi
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37673
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312925
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Craig Topper [Mon, 11 Sep 2017 16:15:39 +0000 (16:15 +0000)]
[SelectionDAG] Remove a check for type being a vector type after calling getShiftAmountTy. NFCI
getShiftAmountTy already returns the vector type when called for vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312924
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Zvi Rackover [Mon, 11 Sep 2017 15:54:38 +0000 (15:54 +0000)]
X86 Tests: More AVX512 conversions tests. NFC
Adding more tests for AVX512 fp<->int conversions that were missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312921
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Marcello Maggioni [Mon, 11 Sep 2017 15:44:20 +0000 (15:44 +0000)]
[ScalarEvolution] Refactor forgetLoop() to improve performance
forgetLoop() has pretty bad performance because it goes over
the same instructions over and over again in particular when
nested loop are involved.
The refactoring changes the function to a not-recursive function
and reusing the allocation for data-structures and the Visited
set.
NFCI
Differential Revision: https://reviews.llvm.org/D37659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312920
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Matt Arsenault [Mon, 11 Sep 2017 15:23:22 +0000 (15:23 +0000)]
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312919
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Simon Pilgrim [Mon, 11 Sep 2017 14:03:47 +0000 (14:03 +0000)]
[X86][SSE] Add support for X86ISD::PACKSS to ComputeNumSignBitsForTargetNode
Helps improve combineLogicBlendIntoPBLENDV support by allowing us to peek into through PACKSS truncations of vector comparison results.
Differential Revision: https://reviews.llvm.org/D37680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312916
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Tim Renouf [Mon, 11 Sep 2017 13:55:39 +0000 (13:55 +0000)]
[AMDGPU] exp should not be in WQM mode
A mrt exp with vm=1 must be in exact (non-WQM) mode, as it also exports
the exec mask as the valid mask to determine which pixels to render.
This commit marks any exp as needing to be in exact mode.
Actually, if there are multiple mrt exps, only one needs to have vm=1,
and only that one needs to be in exact mode. But that is an optimization
for another day.
Differential Revision: https://reviews.llvm.org/D36305
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312915
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Francis Ricci [Mon, 11 Sep 2017 13:50:39 +0000 (13:50 +0000)]
[TableGen] Ensure that __lsan_is_turned_off isn't removed by DCE in llvm-tblgen
Summary:
Since asan is linked dynamically on Darwin, the weak interface symbol
is removed by -Wl,-dead_strip.
Reviewers: kcc, compnerd, aaron.ballman
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37636
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312914
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Sanjay Patel [Mon, 11 Sep 2017 13:34:27 +0000 (13:34 +0000)]
[InstSimplify] reorder methods; NFC
I'm trying to refactor some shared code for integer div/rem,
but I keep having to scroll through fdiv. The FP ops have
nothing in common with the integer ops, so I'm moving FP
below everything else.
While here, improve a couple of comments and fix some formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312913
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Simon Pilgrim [Mon, 11 Sep 2017 12:18:43 +0000 (12:18 +0000)]
[X86][SSE] Add further test cases showing failure to compute sign bits through PACKSS
Suggested in D37680
Note: had to drop AVX512VL tests as there is an infinite loop in the new tests that needs further investigation (not relevant to D37680).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312910
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Gadi Haber [Mon, 11 Sep 2017 11:26:20 +0000 (11:26 +0000)]
[X86][SKX][KNL] Updating several CodeGen tests to use the attr flag instead of mcpu flag
NFC.
Updated 3 Codegen regression tests to use the -mattr flag instead of the -mcpu flags as follows:
Instead of -mcpu=skx use -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq
Instead of -mcpu=knl use -mattr=+avx512f
Reviewers: delena
Revision: https://reviews.llvm.org/D37674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312909
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Andre Vieira [Mon, 11 Sep 2017 11:11:17 +0000 (11:11 +0000)]
[ARM] Enable the use of SVC anywhere in an IT block
Differential Revision: https://reviews.llvm.org/D37374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312908
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Michael Zuckerman [Mon, 11 Sep 2017 10:57:15 +0000 (10:57 +0000)]
[Interleved][Stride 3]Adding test for case the VF=64 target with AVX512.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312907
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Simon Pilgrim [Mon, 11 Sep 2017 10:50:03 +0000 (10:50 +0000)]
[X86][SSE] Add test showing failure to compute sign bits through PACKSS
Prevents combineLogicBlendIntoPBLENDV from merging to PBLENDV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312906
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Dylan McKay [Mon, 11 Sep 2017 10:32:51 +0000 (10:32 +0000)]
[AVR] Enable the '__do_copy_data' function
Also enables '__do_clear_bss'.
These functions are automaticalled called by the CRT if they are
declared.
We need these to be called otherwise RAM will start completely
uninitialised, even though we need to copy RAM variables from progmem to
RAM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312905
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Igor Breger [Mon, 11 Sep 2017 09:41:13 +0000 (09:41 +0000)]
[GlobalISel][X86] G_ANYEXT support.
Summary: G_ANYEXT support
Reviewers: zvi, delena
Reviewed By: delena
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D37675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312903
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Ilya Biryukov [Mon, 11 Sep 2017 09:22:44 +0000 (09:22 +0000)]
Fixed a typo in llvm-cov/deferred-region.cpp test.
Input redirection was using `2&>1` instead of `2>&1`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312902
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Tim Renouf [Mon, 11 Sep 2017 08:31:32 +0000 (08:31 +0000)]
AMDGPU: trivial comment change
... to check commit access for new committer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312900
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Roger Ferrer Ibanez [Mon, 11 Sep 2017 07:38:05 +0000 (07:38 +0000)]
[ARM] Use ADDCARRY / SUBCARRY
This is a preparatory step for D34515 and also is being recommitted as its
first version caused PR34045.
This change:
- makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32
- lowering is done by first converting the boolean value into the carry flag
using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value
using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two
operations does the actual addition.
- for subtraction, given that ISD::SUBCARRY second result is actually a
borrow, we need to invert the value of the second operand and result before
and after using ARMISD::SUBE. We need to invert the carry result of
ARMISD::SUBE to preserve the semantics.
- given that the generic combiner may lower ISD::ADDCARRY and
ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering
as well otherwise i64 operations now would require branches. This implies
updating the corresponding test for unsigned.
- add new combiner to remove the redundant conversions from/to carry flags
to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C
- fixes PR34045
Differential Revision: https://reviews.llvm.org/D35192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312898
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Elena Demikhovsky [Mon, 11 Sep 2017 06:18:15 +0000 (06:18 +0000)]
Fixed a bug in splitting Scatter operation in the Type Legalizer.
After the split of the Scatter operation, the order of the new instructions is well defined - Lo goes before Hi. Otherwise the semantic of Scatter (from LSB to MSB) is broken.
I'm chaining 2 nodes to prevent reordering.
Differential Revision https://reviews.llvm.org/D37670
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312894
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Lang Hames [Mon, 11 Sep 2017 01:09:46 +0000 (01:09 +0000)]
[ORC] Kill off a dead typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312893
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Simon Pilgrim [Sun, 10 Sep 2017 18:42:23 +0000 (18:42 +0000)]
Use llvm_unreachable for unknown TargetCostKind.
TargetTransformInfo::getInstructionCost's switch covers all TargetCostKind cases so we shouldn't return for a default case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312888
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Simon Pilgrim [Sun, 10 Sep 2017 18:18:45 +0000 (18:18 +0000)]
[X86][SSE] Tidyup + clang-format combineX86ShuffleChain call. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312887
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Simon Pilgrim [Sun, 10 Sep 2017 18:10:49 +0000 (18:10 +0000)]
[X86][SSE] Move combineTo call out of combineX86ShufflesConstants. NFCI.
Move towards making it possible to use the shuffle combines for cases where we don't want to call DCI.CombineTo() with the result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312886
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Sanjay Patel [Sun, 10 Sep 2017 17:55:08 +0000 (17:55 +0000)]
[InstSimplify] refactor udiv/urem code and add tests; NFCI
This removes some duplicated code and makes it easier to support signed div/rem
in a similar way if we want to do that. Note that the existing comments were not
accurate - we don't need a constant divisor to simplify; icmp simplification does
more than that. But as the added tests show, it could go even further.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312885
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Simon Pilgrim [Sun, 10 Sep 2017 14:06:41 +0000 (14:06 +0000)]
[X86][SSE] Move combineTo call out of combineX86ShuffleChain. NFCI.
First step towards making it possible to use the shuffle combines for cases where we don't want to call DCI.CombineTo() with the result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312884
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Elena Demikhovsky [Sun, 10 Sep 2017 13:20:42 +0000 (13:20 +0000)]
Added a test that demonstrates a ug in Scatter scheduling.
The bug is going to be fixed in an upcomming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312883
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Coby Tayree [Sun, 10 Sep 2017 12:21:24 +0000 (12:21 +0000)]
[X86][X86AsmParser] adding const on InlineAsmIdentifierInfo in CreateMemForInlineAsm. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312881
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Uriel Korach [Sun, 10 Sep 2017 09:07:21 +0000 (09:07 +0000)]
Revert "adding autoUpgrade support to broadcast[f|i]32x2 intrinsics"
This reverts commit r312879 - An accidental partial commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312880
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Uriel Korach [Sun, 10 Sep 2017 08:40:13 +0000 (08:40 +0000)]
adding autoUpgrade support to broadcast[f|i]32x2 intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312879
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Uriel Korach [Sun, 10 Sep 2017 08:31:22 +0000 (08:31 +0000)]
Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312878
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Sanjoy Das [Sun, 10 Sep 2017 03:54:22 +0000 (03:54 +0000)]
[SCEV] Re-arrange public and private sections to be contiguous; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312876
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Simon Pilgrim [Sat, 9 Sep 2017 20:28:50 +0000 (20:28 +0000)]
[X86] Add v2i4 store test case (PR20012)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312874
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Simon Pilgrim [Sat, 9 Sep 2017 20:22:35 +0000 (20:22 +0000)]
[X86] Add v2i2 test case (PR20011)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312873
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Simon Pilgrim [Sat, 9 Sep 2017 19:25:59 +0000 (19:25 +0000)]
[X86][FMA] Regenerate FMA tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312871
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Nuno Lopes [Sat, 9 Sep 2017 18:23:11 +0000 (18:23 +0000)]
Merge isKnownNonNull into isKnownNonZero
It now knows the tricks of both functions.
Also, fix a bug that considered allocas of non-zero address space to be always non null
Differential Revision: https://reviews.llvm.org/D37628
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312869
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Simon Pilgrim [Sat, 9 Sep 2017 18:18:17 +0000 (18:18 +0000)]
[X86][SSE] i32 vector multiplications test cases from PR6399
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312868
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Simon Pilgrim [Sat, 9 Sep 2017 17:52:44 +0000 (17:52 +0000)]
[X86][MOVBE] Fix typo in MOVBE scheduling test names
Copy+paste is not your friend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312867
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Craig Topper [Sat, 9 Sep 2017 17:11:59 +0000 (17:11 +0000)]
[X86] Don't disable slow INC/DEC if optimizing for size
Summary:
Just because INC/DEC is a little slow on some processors doesn't mean we shouldn't prefer it when optimizing for size.
This appears to match gcc behavior.
Reviewers: chandlerc, zvi, RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37177
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312866
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MinSeong Kim [Sat, 9 Sep 2017 14:17:52 +0000 (14:17 +0000)]
[CMake] Update GetSVN.cmake to handle repo
Summary:
When repo is used with git, 'clang --version' option does not display
the correct revision information (i.e. git hash on TOP) as the following:
clang version 6.0.0 --->
clang version 6.0.0 (clang version) (llvm version)
This is because repo also creates .git/svn folder as git-svn does and
this makes repo with git uses "git svn info" command, which is only for
git-svn, to retrieve its revision information, making null for the info.
To correctly distinguish between git-svn and repo with git, the folder
hierarchy to specify for git-svn should be .git/svn/refs as the "git svn
info" command depends on the revision data in .git/svn/refs. This patch
in turn makes repo with git passes through to the third macro,
get_source_info_git, in get_source_info function, resulting in correctly
retrieving the revision information for repo with git using "git log ..."
command.
This patch is tested with git, svn, git-svn, and repo with git.
Reviewers: llvm-commits, probinson, rnk
Reviewed By: rnk
Subscribers: rnk, mehdi_amini, beanz, mgorny
Differential Revision: https://reviews.llvm.org/D35532
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312864
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Sanjay Patel [Sat, 9 Sep 2017 14:10:59 +0000 (14:10 +0000)]
[DivRemPairs] split tests per target to account for bots that don't build for all targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312863
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Sanjay Patel [Sat, 9 Sep 2017 13:38:18 +0000 (13:38 +0000)]
[DivRempairs] add a pass to optimize div/rem pairs (PR31028)
This is intended to be a superset of the functionality from D31037 (EarlyCSE) but implemented
as an independent pass, so there's no stretching of scope and feature creep for an existing pass.
I also proposed a weaker version of this for SimplifyCFG in D30910. And I initially had almost
this same functionality as an addition to CGP in the motivating example of PR31028:
https://bugs.llvm.org/show_bug.cgi?id=31028
The advantage of positioning this ahead of SimplifyCFG in the pass pipeline is that it can allow
more flattening. But it needs to be after passes (InstCombine) that could sink a div/rem and
undo the hoisting that is done here.
Decomposing remainder may allow removing some code from the backend (PPC and possibly others).
Differential Revision: https://reviews.llvm.org/D37121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312862
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NAKAMURA Takumi [Sat, 9 Sep 2017 06:19:53 +0000 (06:19 +0000)]
CoverageMappingTest.cpp: Suppress warnings. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312861
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Craig Topper [Sat, 9 Sep 2017 05:57:20 +0000 (05:57 +0000)]
[X86] Call removeDeadNode when we're done doing custom isel for mul, div and test
Summary:
Once we've done our custom isel for these nodes, I think we should be calling removeDeadNode to prune them out of the DAG. Table driven isel ultimately either calls morphNodeTo which modifies a node and doesn't leave dead nodes. Or it emits new nodes and then calls removeDeadNode as part of Opc_CompleteMatch.
If you run a simple multiply test case like this through llc with -debug you'll see a umul_lohi node get printed as part of the dump for Instruction Selection ends.
```
define i64 @foo(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%conv = zext i64 %a to i128
%conv1 = zext i64 %b to i128
%mul = mul nuw nsw i128 %conv1, %conv
%shr = lshr i128 %mul, 64
%conv2 = trunc i128 %shr to i64
ret i64 %conv2
}
```
Reviewers: RKSimon, spatel, zvi, guyblank, niravd
Reviewed By: niravd
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312857
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Craig Topper [Sat, 9 Sep 2017 05:57:19 +0000 (05:57 +0000)]
[X86] Use ReplaceNode instead of ReplaceUses when converting X86ISD::SHRUNKBLEND to ISD::VSELECT during isel.
This ensures that the SHRUNKBLEND node gets erased immediately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312856
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Kostya Serebryany [Sat, 9 Sep 2017 05:30:13 +0000 (05:30 +0000)]
[sanitizer-coverage] call appendToUsed once per module, not once per function (which is too slow)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312855
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Alexey Bataev [Sat, 9 Sep 2017 02:08:45 +0000 (02:08 +0000)]
[SLP] Fix buildbots, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312853
91177308-0d34-0410-b5e6-
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Matthias Braun [Sat, 9 Sep 2017 01:16:59 +0000 (01:16 +0000)]
RegAllocFast: Fix warning; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312852
91177308-0d34-0410-b5e6-
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Matthias Braun [Sat, 9 Sep 2017 00:52:46 +0000 (00:52 +0000)]
RegAllocFast: Cleanup; NFC
- Use range based for
- Variable names should start with upper case
- Add `const`
- Change class name to match filename
- Fix doxygen comments
- Use MCPhysReg instead of unsigned
- Use references instead of pointers where things cannot be nullptr
- Misc coding style improvements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312846
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Matthias Braun [Sat, 9 Sep 2017 00:52:45 +0000 (00:52 +0000)]
RegAllocFast: Move vector to class level to avoid reallocation; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312845
91177308-0d34-0410-b5e6-
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Matthias Braun [Sat, 9 Sep 2017 00:52:42 +0000 (00:52 +0000)]
RegAllocFast: Remove write-only set; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312844
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Kyle Butt [Sat, 9 Sep 2017 00:37:56 +0000 (00:37 +0000)]
PPC: Don't select lxv/stxv for insufficiently aligned stack slots.
The lxv/stxv instructions require an offset that is 0 % 16. Previously we were
selecting lxv/stxv for loads and stores to the stack where the offset from the
slot was a multiple of 16, but the stack slot was not 16 or more byte aligned.
When the frame gets lowered these transform to r(1|31) + slot + offset.
If slot is not aligned, slot + offset may not be 0 % 16.
Now we require 16 byte or more alignment for select lxv/stxv to stack slots.
Includes a testcase that shows both sufficiently and insufficiently aligned
stack slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312843
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Yonghong Song [Sat, 9 Sep 2017 00:11:13 +0000 (00:11 +0000)]
bpf: fix test failures due to previous bpf change of assembly code syntax
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312840
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Davide Italiano [Fri, 8 Sep 2017 23:54:11 +0000 (23:54 +0000)]
[AMDGPU] Remove unused function. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312836
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Guozhi Wei [Fri, 8 Sep 2017 23:34:28 +0000 (23:34 +0000)]
[TargetTransformInfo] Remove the extra "default" in a switch that all enum values has been covered.
In function TargetTransformInfo::getInstructionCost, all enum values in the switch statement has been covered, so the default is unnecessary, and may cause error with option -Werror,-Wcovered-switch-default, so remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312834
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Yonghong Song [Fri, 8 Sep 2017 23:32:38 +0000 (23:32 +0000)]
bpf: proper print imm64 expression in inst printer
Fixed an issue in printImm64Operand where if the value is
an expression, print out the expression properly. Currently,
it will print
r1 = <MCOperand Expr:(tx_port)>ll
With the patch, the printout will be
r1 = tx_port
Suggested-by: Jiong Wang <jiong.wang@netronome.com>
Signed-off-by: Yonghong Song <yhs@fb.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312833
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Guozhi Wei [Fri, 8 Sep 2017 22:29:17 +0000 (22:29 +0000)]
[TargetTransformInfo] Add a new public interface getInstructionCost
Current TargetTransformInfo can support throughput cost model and code size model, but sometimes we also need instruction latency cost model in different optimizations. Hal suggested we need a single public interface to query the different cost of an instruction. So I proposed following interface:
enum TargetCostKind {
TCK_RecipThroughput, ///< Reciprocal throughput.
TCK_Latency, ///< The latency of instruction.
TCK_CodeSize ///< Instruction code size.
};
int getInstructionCost(const Instruction *I, enum TargetCostKind kind) const;
All clients should mainly use this function to query the cost of an instruction, parameter <kind> specifies the desired cost model.
This patch also provides a simple default implementation of getInstructionLatency.
The default getInstructionLatency provides latency numbers for only small number of instruction classes, those latency numbers are only reasonable for modern OOO processors. It can be extended in following ways:
Add more detail into this function.
Add getXXXLatency function and call it from here.
Implement target specific getInstructionLatency function.
Differential Revision: https://reviews.llvm.org/D37170
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312832
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Petr Hosek [Fri, 8 Sep 2017 22:26:50 +0000 (22:26 +0000)]
[CMake][runtimes] Use the same configuration for non-target and "default" target
The default host target for builtins and runtimes has special behavior
on some platforms, e.g. on Linux both i386 and x86_64 targets are being
built. Specifying "default" as a target name should lead to the same
behavior, which wasn't the case in the past. This patch unifies the
configuration between the non-target and "default" target to produce the
same behavior by moving the default configuration into a function that
can be used from both paths.
Differential Revision: https://reviews.llvm.org/D37450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312831
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David Blaikie [Fri, 8 Sep 2017 21:10:01 +0000 (21:10 +0000)]
Migrate llvm-symbolizer tests to not use %T
(context around the %T removal here: https://reviews.llvm.org/D35396 )
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312828
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Vedant Kumar [Fri, 8 Sep 2017 20:24:23 +0000 (20:24 +0000)]
[llvm-cov] Use portable output redirection in a test
A follow-up to a test fix (r312825).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312826
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Vedant Kumar [Fri, 8 Sep 2017 20:18:17 +0000 (20:18 +0000)]
[llvm-cov] Try to appease a Windows bot
On a Windows bot, I see a FileCheck error where the source being matched
over no longer exists, i.e it seems like it's FileCheck'ing some stale
output:
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/4747
You can see "// CHECK: [[@LINE]]|{{ +}Marker at 19:3 = 1" in the
FileCheck stderr, but that CHECK line doesn't exist.
Remove the input file to FileCheck before running the test, to try and
appease the bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312825
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Matt Arsenault [Fri, 8 Sep 2017 19:09:13 +0000 (19:09 +0000)]
AMDGPU: Start using !con operator
We have a lot of operand definition work essentially producing
every valid permutation of operands to workaround builiding
operand lists based on the instruction features. Apparently tablegen
already has a mostly undocumented operator to concat dags which
simplies this.
Convert one simple place to use this. The BUF instruction definitions
have much more complicated logic that can be totally rewritten now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312822
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Vedant Kumar [Fri, 8 Sep 2017 19:08:39 +0000 (19:08 +0000)]
[llvm-cov] Disable name-compression in a test binary
This should fix the lld bot:
The Buildbot has detected a new failure on builder llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast while building cfe.
Full details are available at:
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/16993
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312821
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Matt Arsenault [Fri, 8 Sep 2017 18:51:26 +0000 (18:51 +0000)]
AMDGPU: Recompute scc liveness
The various scalar bit operations set SCC,
so one is erased or moved it needs to be recomputed.
Not sure why the existing tests don't fail on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312819
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Vedant Kumar [Fri, 8 Sep 2017 18:44:50 +0000 (18:44 +0000)]
[Coverage] Build sorted and unique segments
A coverage segment contains a starting line and column, an execution
count, and some other metadata. Clients of the coverage library use
segments to prepare line-oriented reports.
Users of the coverage library depend on segments being unique and sorted
in source order. Currently this is not guaranteed (this is why the clang
change which introduced deferred regions was reverted).
This commit documents the "unique and sorted" condition and asserts that
it holds. It also fixes the SegmentBuilder so that it produces correct
output in some edge cases.
Testing: I've added unit tests for some edge cases. I've also checked
that the new SegmentBuilder implementation is fully covered. Apart from
running check-profile and the llvm-cov tests, I've successfully used a
stage1 llvm-cov to prepare a coverage report for an instrumented clang
binary.
Differential Revision: https://reviews.llvm.org/D36813
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312817
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Vedant Kumar [Fri, 8 Sep 2017 18:44:49 +0000 (18:44 +0000)]
[llvm-cov] Fix a lifetime issue
This fixes an issue where a std::string was moved to a constructor
which accepted a StringRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312816
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Vedant Kumar [Fri, 8 Sep 2017 18:44:48 +0000 (18:44 +0000)]
[Coverage] Define LineColPair for convenience. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312815
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Vedant Kumar [Fri, 8 Sep 2017 18:44:47 +0000 (18:44 +0000)]
[Coverage] Report errors when reading malformed source regions
Each source region has a start and end location. Report an error when
the end location does not precede the begin location.
The old lineExecutionCounts.covmapping test actually had a buggy source
region in it. This commit introduces a regenerated copy of the coverage
and moves the old copy to malformedRegions.covmapping, for a test.
Differential Revision: https://reviews.llvm.org/D37387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312814
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Vedant Kumar [Fri, 8 Sep 2017 18:44:46 +0000 (18:44 +0000)]
[llvm-cov] Unify region marker placement between text/html modes
Make sure that the text and html emitters always emit the same set of
region markers, and avoid emitting redundant markers for line segments
which don't end on the line they start on.
This is related to D35925, and depends on D36014
Differential Revision: https://reviews.llvm.org/D36020
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312813
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Chandler Carruth [Fri, 8 Sep 2017 18:23:42 +0000 (18:23 +0000)]
[x86] Fix GCC pedantic warnings about default arguments for lambdas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312809
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Craig Topper [Fri, 8 Sep 2017 17:33:54 +0000 (17:33 +0000)]
[X86] Simplify the slow-incdec test and add test cases with optsize.
I think we want to consider using inc/dec with optsize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312804
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Dinar Temirbulatov [Fri, 8 Sep 2017 17:08:17 +0000 (17:08 +0000)]
[SLPVectorizer] Add struct InstructionsState that holds information about analysis of vector to be vectorized.
Reviewers: spatel, mzolotukhin, mkuper, hfinkel, RKSimon, filcab, ABataev, davide
Subscribers: llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D37212
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312802
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Wei Mi [Fri, 8 Sep 2017 16:44:52 +0000 (16:44 +0000)]
Fix a bug for rL312641.
rL312641 Allowed llvm.memcpy/memset/memmove to be tail calls when parent
function return the intrinsics's first argument. However on arm-none-eabi
platform, llvm.memcpy will be expanded to __aeabi_memcpy which doesn't
have return value. The fix is to check the libcall name after expansion
to match "memcpy/memset/memmove" before allowing those intrinsic to be
tail calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312799
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Krzysztof Parzyszek [Fri, 8 Sep 2017 16:29:50 +0000 (16:29 +0000)]
Preserve existing regs when adding pristines to LivePhysRegs/LiveRegUnits
Differential Revision: https://reviews.llvm.org/D37600
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312797
91177308-0d34-0410-b5e6-
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Alexey Bataev [Fri, 8 Sep 2017 14:32:20 +0000 (14:32 +0000)]
[SLP] Fix the warning about paths not returning the value, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312793
91177308-0d34-0410-b5e6-
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Alexey Bataev [Fri, 8 Sep 2017 13:49:36 +0000 (13:49 +0000)]
[SLP] Support for horizontal min/max reduction.
SLP vectorizer supports horizontal reductions for Add/FAdd binary
operations. Patch adds support for horizontal min/max reductions.
Function getReductionCost() is split to getArithmeticReductionCost() for
binary operation reductions and getMinMaxReductionCost() for min/max
reductions.
Patch fixes PR26956.
Differential revision: https://reviews.llvm.org/D27846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312791
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Simon Pilgrim [Fri, 8 Sep 2017 10:49:11 +0000 (10:49 +0000)]
[X86] Added PR31045 test case
Reduced version of 'addr-calc-crash.ll' that was included in D27044, that had been fixed already by D31286/rL298633
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312786
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Max Kazantsev [Fri, 8 Sep 2017 10:15:05 +0000 (10:15 +0000)]
Re-enable "[IRCE] Identify loops with latch comparison against current IV value"
Re-applying after the found bug was fixed.
Differential Revision: https://reviews.llvm.org/D36215
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312783
91177308-0d34-0410-b5e6-
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Jonas Devlieghere [Fri, 8 Sep 2017 09:48:51 +0000 (09:48 +0000)]
[dwarfdump] Verify line table prologue
This patch adds prologue verification, which is already present in
Apple's dwarfdump. It checks for invalid directory indices and warns
about duplicate file paths.
Differential revision: https://reviews.llvm.org/D37511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312782
91177308-0d34-0410-b5e6-
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Jatin Bhateja [Fri, 8 Sep 2017 09:15:36 +0000 (09:15 +0000)]
[X86] Adding a test point for PR34149 'Suboptimal codegen for "fast" minnum and maxnum'
Differential Revision: https://reviews.llvm.org/D37614
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312778
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Martin Storsjo [Fri, 8 Sep 2017 06:49:46 +0000 (06:49 +0000)]
[llvm-dlltool] Mention arm64 in the lists of architecture alternatives
This was missed in SVN r310223 when arm64 support was added.
Differential Revision: https://reviews.llvm.org/D37588
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312776
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Max Kazantsev [Fri, 8 Sep 2017 04:26:41 +0000 (04:26 +0000)]
diff --git a/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp b/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
index
f72a808..
9fa49fd 100644
--- a/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
+++ b/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
@@ -450,20 +450,10 @@ struct LoopStructure {
// equivalent to:
//
// intN_ty inc = IndVarIncreasing ? 1 : -1;
- // pred_ty predicate = IndVarIncreasing
- // ? IsSignedPredicate ? ICMP_SLT : ICMP_ULT
- // : IsSignedPredicate ? ICMP_SGT : ICMP_UGT;
+ // pred_ty predicate = IndVarIncreasing ? ICMP_SLT : ICMP_SGT;
//
- //
- // for (intN_ty iv = IndVarStart; predicate(IndVarBase, LoopExitAt);
- // iv = IndVarNext)
+ // for (intN_ty iv = IndVarStart; predicate(iv, LoopExitAt); iv = IndVarBase)
// ... body ...
- //
- // Here IndVarBase is either current or next value of the induction variable.
- // in the former case, IsIndVarNext = false and IndVarBase points to the
- // Phi node of the induction variable. Otherwise, IsIndVarNext = true and
- // IndVarBase points to IV increment instruction.
- //
Value *IndVarBase;
Value *IndVarStart;
@@ -471,13 +461,12 @@ struct LoopStructure {
Value *LoopExitAt;
bool IndVarIncreasing;
bool IsSignedPredicate;
- bool IsIndVarNext;
LoopStructure()
: Tag(""), Header(nullptr), Latch(nullptr), LatchBr(nullptr),
LatchExit(nullptr), LatchBrExitIdx(-1), IndVarBase(nullptr),
IndVarStart(nullptr), IndVarStep(nullptr), LoopExitAt(nullptr),
- IndVarIncreasing(false), IsSignedPredicate(true), IsIndVarNext(false) {}
+ IndVarIncreasing(false), IsSignedPredicate(true) {}
template <typename M> LoopStructure map(M Map) const {
LoopStructure Result;
@@ -493,7 +482,6 @@ struct LoopStructure {
Result.LoopExitAt = Map(LoopExitAt);
Result.IndVarIncreasing = IndVarIncreasing;
Result.IsSignedPredicate = IsSignedPredicate;
- Result.IsIndVarNext = IsIndVarNext;
return Result;
}
@@ -841,42 +829,21 @@ LoopStructure::parseLoopStructure(ScalarEvolution &SE,
return false;
};
- // `ICI` can either be a comparison against IV or a comparison of IV.next.
- // Depending on the interpretation, we calculate the start value differently.
+ // `ICI` is interpreted as taking the backedge if the *next* value of the
+ // induction variable satisfies some constraint.
- // Pair {IndVarBase; IsIndVarNext} semantically designates whether the latch
- // comparisons happens against the IV before or after its value is
- // incremented. Two valid combinations for them are:
- //
- // 1) { phi [ iv.start, preheader ], [ iv.next, latch ]; false },
- // 2) { iv.next; true }.
- //
- // The latch comparison happens against IndVarBase which can be either current
- // or next value of the induction variable.
const SCEVAddRecExpr *IndVarBase = cast<SCEVAddRecExpr>(LeftSCEV);
bool IsIncreasing = false;
bool IsSignedPredicate = true;
- bool IsIndVarNext = false;
ConstantInt *StepCI;
if (!IsInductionVar(IndVarBase, IsIncreasing, StepCI)) {
FailureReason = "LHS in icmp not induction variable";
return None;
}
- const SCEV *IndVarStart = nullptr;
- // TODO: Currently we only handle comparison against IV, but we can extend
- // this analysis to be able to deal with comparison against sext(iv) and such.
- if (isa<PHINode>(LeftValue) &&
- cast<PHINode>(LeftValue)->getParent() == Header)
- // The comparison is made against current IV value.
- IndVarStart = IndVarBase->getStart();
- else {
- // Assume that the comparison is made against next IV value.
- const SCEV *StartNext = IndVarBase->getStart();
- const SCEV *Addend = SE.getNegativeSCEV(IndVarBase->getStepRecurrence(SE));
- IndVarStart = SE.getAddExpr(StartNext, Addend);
- IsIndVarNext = true;
- }
+ const SCEV *StartNext = IndVarBase->getStart();
+ const SCEV *Addend = SE.getNegativeSCEV(IndVarBase->getStepRecurrence(SE));
+ const SCEV *IndVarStart = SE.getAddExpr(StartNext, Addend);
const SCEV *Step = SE.getSCEV(StepCI);
ConstantInt *One = ConstantInt::get(IndVarTy, 1);
@@ -1060,7 +1027,6 @@ LoopStructure::parseLoopStructure(ScalarEvolution &SE,
Result.IndVarIncreasing = IsIncreasing;
Result.LoopExitAt = RightValue;
Result.IsSignedPredicate = IsSignedPredicate;
- Result.IsIndVarNext = IsIndVarNext;
FailureReason = nullptr;
@@ -1350,9 +1316,8 @@ LoopConstrainer::RewrittenRangeInfo LoopConstrainer::changeIterationSpaceEnd(
BranchToContinuation);
NewPHI->addIncoming(PN->getIncomingValueForBlock(Preheader), Preheader);
- auto *FixupValue =
- LS.IsIndVarNext ? PN->getIncomingValueForBlock(LS.Latch) : PN;
- NewPHI->addIncoming(FixupValue, RRI.ExitSelector);
+ NewPHI->addIncoming(PN->getIncomingValueForBlock(LS.Latch),
+ RRI.ExitSelector);
RRI.PHIValuesAtPseudoExit.push_back(NewPHI);
}
@@ -1735,10 +1700,7 @@ bool InductiveRangeCheckElimination::runOnLoop(Loop *L, LPPassManager &LPM) {
}
LoopStructure LS = MaybeLoopStructure.getValue();
const SCEVAddRecExpr *IndVar =
- cast<SCEVAddRecExpr>(SE.getSCEV(LS.IndVarBase));
- if (LS.IsIndVarNext)
- IndVar = cast<SCEVAddRecExpr>(SE.getMinusSCEV(IndVar,
- SE.getSCEV(LS.IndVarStep)));
+ cast<SCEVAddRecExpr>(SE.getMinusSCEV(SE.getSCEV(LS.IndVarBase), SE.getSCEV(LS.IndVarStep)));
Optional<InductiveRangeCheck::Range> SafeIterRange;
Instruction *ExprInsertPt = Preheader->getTerminator();
diff --git a/test/Transforms/IRCE/latch-comparison-against-current-value.ll b/test/Transforms/IRCE/latch-comparison-against-current-value.ll
deleted file mode 100644
index
afea0e6..
0000000
--- a/test/Transforms/IRCE/latch-comparison-against-current-value.ll
+++ /dev/null
@@ -1,182 +0,0 @@
-; RUN: opt -verify-loop-info -irce-print-changed-loops -irce -S < %s 2>&1 | FileCheck %s
-
-; Check that IRCE is able to deal with loops where the latch comparison is
-; done against current value of the IV, not the IV.next.
-
-; CHECK: irce: in function test_01: constrained Loop at depth 1 containing: %loop<header><exiting>,%in.bounds<latch><exiting>
-; CHECK: irce: in function test_02: constrained Loop at depth 1 containing: %loop<header><exiting>,%in.bounds<latch><exiting>
-; CHECK-NOT: irce: in function test_03: constrained Loop at depth 1 containing: %loop<header><exiting>,%in.bounds<latch><exiting>
-; CHECK-NOT: irce: in function test_04: constrained Loop at depth 1 containing: %loop<header><exiting>,%in.bounds<latch><exiting>
-
-; SLT condition for increasing loop from 0 to 100.
-define void @test_01(i32* %arr, i32* %a_len_ptr) #0 {
-
-; CHECK: test_01
-; CHECK: entry:
-; CHECK-NEXT: %exit.mainloop.at = load i32, i32* %a_len_ptr, !range !0
-; CHECK-NEXT: [[COND2:%[^ ]+]] = icmp slt i32 0, %exit.mainloop.at
-; CHECK-NEXT: br i1 [[COND2]], label %loop.preheader, label %main.pseudo.exit
-; CHECK: loop:
-; CHECK-NEXT: %idx = phi i32 [ %idx.next, %in.bounds ], [ 0, %loop.preheader ]
-; CHECK-NEXT: %idx.next = add nuw nsw i32 %idx, 1
-; CHECK-NEXT: %abc = icmp slt i32 %idx, %exit.mainloop.at
-; CHECK-NEXT: br i1 true, label %in.bounds, label %out.of.bounds.loopexit1
-; CHECK: in.bounds:
-; CHECK-NEXT: %addr = getelementptr i32, i32* %arr, i32 %idx
-; CHECK-NEXT: store i32 0, i32* %addr
-; CHECK-NEXT: %next = icmp slt i32 %idx, 100
-; CHECK-NEXT: [[COND3:%[^ ]+]] = icmp slt i32 %idx, %exit.mainloop.at
-; CHECK-NEXT: br i1 [[COND3]], label %loop, label %main.exit.selector
-; CHECK: main.exit.selector:
-; CHECK-NEXT: %idx.lcssa = phi i32 [ %idx, %in.bounds ]
-; CHECK-NEXT: [[COND4:%[^ ]+]] = icmp slt i32 %idx.lcssa, 100
-; CHECK-NEXT: br i1 [[COND4]], label %main.pseudo.exit, label %exit
-; CHECK-NOT: loop.preloop:
-; CHECK: loop.postloop:
-; CHECK-NEXT: %idx.postloop = phi i32 [ %idx.copy, %postloop ], [ %idx.next.postloop, %in.bounds.postloop ]
-; CHECK-NEXT: %idx.next.postloop = add nuw nsw i32 %idx.postloop, 1
-; CHECK-NEXT: %abc.postloop = icmp slt i32 %idx.postloop, %exit.mainloop.at
-; CHECK-NEXT: br i1 %abc.postloop, label %in.bounds.postloop, label %out.of.bounds.loopexit
-
-entry:
- %len = load i32, i32* %a_len_ptr, !range !0
- br label %loop
-
-loop:
- %idx = phi i32 [ 0, %entry ], [ %idx.next, %in.bounds ]
- %idx.next = add nsw nuw i32 %idx, 1
- %abc = icmp slt i32 %idx, %len
- br i1 %abc, label %in.bounds, label %out.of.bounds
-
-in.bounds:
- %addr = getelementptr i32, i32* %arr, i32 %idx
- store i32 0, i32* %addr
- %next = icmp slt i32 %idx, 100
- br i1 %next, label %loop, label %exit
-
-out.of.bounds:
- ret void
-
-exit:
- ret void
-}
-
-; ULT condition for increasing loop from 0 to 100.
-define void @test_02(i32* %arr, i32* %a_len_ptr) #0 {
-
-; CHECK: test_02
-; CHECK: entry:
-; CHECK-NEXT: %exit.mainloop.at = load i32, i32* %a_len_ptr, !range !0
-; CHECK-NEXT: [[COND2:%[^ ]+]] = icmp ult i32 0, %exit.mainloop.at
-; CHECK-NEXT: br i1 [[COND2]], label %loop.preheader, label %main.pseudo.exit
-; CHECK: loop:
-; CHECK-NEXT: %idx = phi i32 [ %idx.next, %in.bounds ], [ 0, %loop.preheader ]
-; CHECK-NEXT: %idx.next = add nuw nsw i32 %idx, 1
-; CHECK-NEXT: %abc = icmp ult i32 %idx, %exit.mainloop.at
-; CHECK-NEXT: br i1 true, label %in.bounds, label %out.of.bounds.loopexit1
-; CHECK: in.bounds:
-; CHECK-NEXT: %addr = getelementptr i32, i32* %arr, i32 %idx
-; CHECK-NEXT: store i32 0, i32* %addr
-; CHECK-NEXT: %next = icmp ult i32 %idx, 100
-; CHECK-NEXT: [[COND3:%[^ ]+]] = icmp ult i32 %idx, %exit.mainloop.at
-; CHECK-NEXT: br i1 [[COND3]], label %loop, label %main.exit.selector
-; CHECK: main.exit.selector:
-; CHECK-NEXT: %idx.lcssa = phi i32 [ %idx, %in.bounds ]
-; CHECK-NEXT: [[COND4:%[^ ]+]] = icmp ult i32 %idx.lcssa, 100
-; CHECK-NEXT: br i1 [[COND4]], label %main.pseudo.exit, label %exit
-; CHECK-NOT: loop.preloop:
-; CHECK: loop.postloop:
-; CHECK-NEXT: %idx.postloop = phi i32 [ %idx.copy, %postloop ], [ %idx.next.postloop, %in.bounds.postloop ]
-; CHECK-NEXT: %idx.next.postloop = add nuw nsw i32 %idx.postloop, 1
-; CHECK-NEXT: %abc.postloop = icmp ult i32 %idx.postloop, %exit.mainloop.at
-; CHECK-NEXT: br i1 %abc.postloop, label %in.bounds.postloop, label %out.of.bounds.loopexit
-
-entry:
- %len = load i32, i32* %a_len_ptr, !range !0
- br label %loop
-
-loop:
- %idx = phi i32 [ 0, %entry ], [ %idx.next, %in.bounds ]
- %idx.next = add nsw nuw i32 %idx, 1
- %abc = icmp ult i32 %idx, %len
- br i1 %abc, label %in.bounds, label %out.of.bounds
-
-in.bounds:
- %addr = getelementptr i32, i32* %arr, i32 %idx
- store i32 0, i32* %addr
- %next = icmp ult i32 %idx, 100
- br i1 %next, label %loop, label %exit
-
-out.of.bounds:
- ret void
-
-exit:
- ret void
-}
-
-; Same as test_01, but comparison happens against IV extended to a wider type.
-; This test ensures that IRCE rejects it and does not falsely assume that it was
-; a comparison against iv.next.
-; TODO: We can actually extend the recognition to cover this case.
-define void @test_03(i32* %arr, i64* %a_len_ptr) #0 {
-
-; CHECK: test_03
-
-entry:
- %len = load i64, i64* %a_len_ptr, !range !1
- br label %loop
-
-loop:
- %idx = phi i32 [ 0, %entry ], [ %idx.next, %in.bounds ]
- %idx.next = add nsw nuw i32 %idx, 1
- %idx.ext = sext i32 %idx to i64
- %abc = icmp slt i64 %idx.ext, %len
- br i1 %abc, label %in.bounds, label %out.of.bounds
-
-in.bounds:
- %addr = getelementptr i32, i32* %arr, i32 %idx
- store i32 0, i32* %addr
- %next = icmp slt i32 %idx, 100
- br i1 %next, label %loop, label %exit
-
-out.of.bounds:
- ret void
-
-exit:
- ret void
-}
-
-; Same as test_02, but comparison happens against IV extended to a wider type.
-; This test ensures that IRCE rejects it and does not falsely assume that it was
-; a comparison against iv.next.
-; TODO: We can actually extend the recognition to cover this case.
-define void @test_04(i32* %arr, i64* %a_len_ptr) #0 {
-
-; CHECK: test_04
-
-entry:
- %len = load i64, i64* %a_len_ptr, !range !1
- br label %loop
-
-loop:
- %idx = phi i32 [ 0, %entry ], [ %idx.next, %in.bounds ]
- %idx.next = add nsw nuw i32 %idx, 1
- %idx.ext = sext i32 %idx to i64
- %abc = icmp ult i64 %idx.ext, %len
- br i1 %abc, label %in.bounds, label %out.of.bounds
-
-in.bounds:
- %addr = getelementptr i32, i32* %arr, i32 %idx
- store i32 0, i32* %addr
- %next = icmp ult i32 %idx, 100
- br i1 %next, label %loop, label %exit
-
-out.of.bounds:
- ret void
-
-exit:
- ret void
-}
-
-!0 = !{i32 0, i32 50}
-!1 = !{i64 0, i64 50}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312775
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Fri, 8 Sep 2017 02:31:37 +0000 (02:31 +0000)]
Fix a crash when emitting debug info for multi-reg function arguments
by reusing more of the existing machinery
This is a follow-up to r312169.
Thanks to Björn Pettersson for the testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312773
91177308-0d34-0410-b5e6-
96231b3b80d8
Dean Michael Berris [Fri, 8 Sep 2017 01:47:56 +0000 (01:47 +0000)]
[XRay][CodeGen][PowerPC] Fix tail exit codegen for XRay in PPC
Summary:
This fixes code-gen for XRay in PPC. The regression wasn't caught by
codegen tests which we add in this change.
What happened was the following:
- For tail exits, we used to unconditionally prepend the returns/exits
with a pseudo-instruction that gets lowered to the instrumentation
sled (and leave the actual return/exit instruction as-is).
- Changes to the XRay instrumentation pass caused the tail exits to
suddenly also emit the tail exit pseudo-instruction, since the check
for whether a return instruction was also a call instruction meant it
was a tail exit instruction.
- None of the tests caught the regression either due to non-existent
tests, or the tests being disabled/removed for continuous breakage.
This change re-introduces some of the basic tests and verifies that
we're back to a state that allows the back-end to generate appropriate
XRay instrumented binaries for PPC in the presence of tail exits.
Reviewers: echristo, timshen
Subscribers: nemanjai, kbarton, llvm-commits
Differential Revision: https://reviews.llvm.org/D37570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312772
91177308-0d34-0410-b5e6-
96231b3b80d8