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Dmitry Preobrazhensky [Wed, 21 Jun 2017 14:41:34 +0000 (14:41 +0000)]
[AMDGPU][MC] Corrected V_*QSAD* instructions to check that dest register is different than any of the src
See Bug 33279: https://bugs.llvm.org//show_bug.cgi?id=33279
Reviewers: artem.tamazov, vpykhtin
Differential Revision: https://reviews.llvm.org/D34003
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305915
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Sanjay Patel [Wed, 21 Jun 2017 14:27:11 +0000 (14:27 +0000)]
[x86] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305914
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Simon Pilgrim [Wed, 21 Jun 2017 14:23:02 +0000 (14:23 +0000)]
[X86][SSE] Dropped -mcpu from 128-bit vector shuffle tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305913
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Simon Pilgrim [Wed, 21 Jun 2017 13:46:42 +0000 (13:46 +0000)]
[X86][SSE] Regenerate merge store tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305910
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Simon Pilgrim [Wed, 21 Jun 2017 13:45:33 +0000 (13:45 +0000)]
[X86][SSE] Dropped -mcpu from vector blend shuffle tests and regenerate
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305909
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Simon Pilgrim [Wed, 21 Jun 2017 13:26:52 +0000 (13:26 +0000)]
[X86][SSE] Dropped -mcpu from vector shuffle tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305908
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Simon Pilgrim [Wed, 21 Jun 2017 13:17:14 +0000 (13:17 +0000)]
[X86][SSE] Dropped -mcpu from vector zero extend tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305907
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Simon Pilgrim [Wed, 21 Jun 2017 13:15:41 +0000 (13:15 +0000)]
[X86][SSE] Dropped -mcpu from variable shuffle tests
Use triple and attribute only for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305906
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Simon Pilgrim [Wed, 21 Jun 2017 12:58:56 +0000 (12:58 +0000)]
[X86][AVX] Add AVX1 shuffle truncation tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305905
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Simon Pilgrim [Wed, 21 Jun 2017 12:58:19 +0000 (12:58 +0000)]
[X86][SSE] Add SSE2/SSE42 shuffle truncation tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305904
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Zvi Rackover [Wed, 21 Jun 2017 11:21:43 +0000 (11:21 +0000)]
[X86] Rerun the update_llc_test_checks tool on test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305897
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Pavel Labath [Wed, 21 Jun 2017 11:10:02 +0000 (11:10 +0000)]
Fix build after r305892
Make sure to #include <cerrno> in Support/Errno.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305895
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Christof Douma [Wed, 21 Jun 2017 10:58:31 +0000 (10:58 +0000)]
[AARCH64][LSE] Preliminary support for ARMv8.1 LSE Atomics.
Implemented support to AArch64 codegen for ARMv8.1 Large System
Extensions atomic instructions. Where supported, these instructions can
provide atomic operations with higher performance.
Currently supported operations include: fetch_add, fetch_or, fetch_xor,
fetch_smin, fetch_min/max (signed and unsigned), swap, and
compare_exchange.
This implementation implies sequential-consistency ordering, more
relaxed ordering is under development.
Subtarget->hasLSE is currently supported for Cavium ThunderX2T99.
Patch by Ananth Jasty.
Differential Revision: https://reviews.llvm.org/D33586
Change-Id: I82f6d3d64255622791ceb0715b7ab9f4dc4d4b2c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305893
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Pavel Labath [Wed, 21 Jun 2017 10:55:34 +0000 (10:55 +0000)]
[Support] Add RetryAfterSignal helper function
Summary:
This function retries an operation if it was interrupted by a signal
(failed with EINTR). It's inspired by the TEMP_FAILURE_RETRY macro in
glibc, but I've turned that into a template function. I've also added a
fail-value argument, to enable the function to be used with e.g.
fopen(3), which is documented to fail for any reason that open(2) can
fail (which includes EINTR).
The main user of this function will be lldb, but there were also a
couple of uses within llvm that I could simplify using this function.
Reviewers: zturner, silvas, joerg
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D33895
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305892
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Florian Hahn [Wed, 21 Jun 2017 09:51:52 +0000 (09:51 +0000)]
[AArch64] Add early exit to promoteLoadFromStore.
There should be at most a single kill flag for the
promoted operand between the store/load pair.
Discussed in https://reviews.llvm.org/D34402.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305889
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Strahinja Petrovic [Wed, 21 Jun 2017 09:25:51 +0000 (09:25 +0000)]
[MIPS] Fix for selecting of DINS/INS instruction
This patch adds one more condition in selection DINS/INS
instruction, which fixes MultiSource/Applications/JM/ldecod/
for mips32r2 (and mips64r2 n32 abi).
Differential Revision: https://reviews.llvm.org/D33725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305888
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Javed Absar [Wed, 21 Jun 2017 09:10:10 +0000 (09:10 +0000)]
Use range-loop in machine-scheduler. NFCI.
Converts to range-loop usage in machine scheduler.
This makes the code neater and easier to read,
and also keeps pace of the machine scheduler
implementation with C++11 features.
Reviewed by: Matthias Braun
Differential Revision: https://reviews.llvm.org/D34320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305887
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Sam Kolton [Wed, 21 Jun 2017 08:53:38 +0000 (08:53 +0000)]
[AMDGPU] SDWA: merge VI and GFX9 pseudo instructions
Summary: Previously there were two separate pseudo instruction for SDWA on VI and on GFX9. Created one pseudo instruction that is union of both of them. Added verifier to check that operands conform either VI or GFX9.
Reviewers: dp, arsenm, vpykhtin
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, artem.tamazov
Differential Revision: https://reviews.llvm.org/D34026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305886
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Florian Hahn [Wed, 21 Jun 2017 08:47:23 +0000 (08:47 +0000)]
[AArch64] Preserve register flags when promoting a load from store.
Summary:
This patch updates promoteLoadFromStore to use the store MachineOperand as the
source operand of the of the new instruction instead of creating a new
register MachineOperand. This way, the existing register flags are
preserved.
This fixes PR33468 (https://bugs.llvm.org/show_bug.cgi?id=33468).
Reviewers: MatzeB, t.p.northover, junbuml
Reviewed By: MatzeB
Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34402
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305885
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Guy Blank [Wed, 21 Jun 2017 07:38:41 +0000 (07:38 +0000)]
[DAGCombiner] Add another combine from build vector to shuffle
Add support for combining a build vector to a shuffle.
When the build vector is of extracted elements from 2 vectors (vec1, vec2) where vec2 is 2 times smaller than vec1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305883
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Max Kazantsev [Wed, 21 Jun 2017 07:28:13 +0000 (07:28 +0000)]
[SCEV] Make MulOpsInlineThreshold lower to avoid excessive compilation time
MulOpsInlineThreshold option of SCEV is defaulted to 1000, which is inadequately high.
When constructing SCEVs of expressions like:
x1 = a * a
x2 = x1 * x1
x3 = x2 * x2
...
We actually have huge SCEVs with max allowed amount of operands inlined.
Such expressions are easy to get from unrolling of loops looking like
x = a
for (i = 0; i < n; i++)
x = x * x
Or more tricky cases where big powers are involved. If some non-linear analysis
tries to work with a SCEV that has 1000 operands, it may lead to excessively long
compilation. The attached test does not pass within 1 minute with default threshold.
This patch decreases its default value to 32, which looks much more reasonable if we
use analyzes with complexity O(N^2) or O(N^3) working with SCEV.
Differential Revision: https://reviews.llvm.org/D34397
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305882
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Rafael Espindola [Wed, 21 Jun 2017 06:42:56 +0000 (06:42 +0000)]
Simplify test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305881
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Dean Michael Berris [Wed, 21 Jun 2017 06:39:42 +0000 (06:39 +0000)]
[XRay] Reduce synthetic references emitted by XRay
Summary:
When we're building with XRay instrumentation, we use a trick that
preserves references from the function to a function sled index. This
index table lives in a separate section, and without this trick the
linker is free to garbage-collect this section and all the segments it
refers to. Until we're able to tell the linkers to preserve these
sections, we use this reference trick to keep around both the index and
the entries in the instrumentation map.
Before this change we emitted both a synthetic reference to the label in
the instrumentation map, and to the entry in the function map index.
This change removes the first synthetic reference and only emits one
synthetic reference to the index -- the index entry has the references
to the labels in the instrumentation map, so the linker will still
preserve those if the function itself is preserved.
This reduces the amount of synthetic references we emit from 16 bytes to
just 8 bytes in x86_64, and similarly to other platforms.
Reviewers: dblaikie
Subscribers: javed.absar, kpw, pelikan, llvm-commits
Differential Revision: https://reviews.llvm.org/D34340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305880
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Serguei Katkov [Wed, 21 Jun 2017 06:38:23 +0000 (06:38 +0000)]
[ImplicitNullChecks] Uphold an invariant in areMemoryOpsAliased
Right now areMemoryOpsAliased has an assertion justified as:
MMO1 should have a value due it comes from operation we'd like to use
as implicit null check.
assert(MMO1->getValue() && "MMO1 should have a Value!");
However, it is possible for that invariant to not be upheld in the
following situation (conceptually):
Null check %RAX
NotNullSucc:
%RAX = LEA %RSP, 16 // I0
%RDX = MOV64rm %RAX // I1
With the current code, we will have an early exit from
ImplicitNullChecks::isSuitableMemoryOp on I0 with SR_Unsuitable.
However, I1 will look plausible (since it loads from %RAX) and
will go ahead and call areMemoryOpsAliased(I1, I0). This will cause
us to fail the assert mentioned above since I1 does not load from an
IR level value and thus is allowed to have a non-Value base address.
The fix is to bail out earlier whenever we see an unsuitable
instruction overwrite PointerReg. This would guarantee that when we
call areMemoryOpsAliased, we're guaranteed to be looking at an
instruction that loads from or stores to an IR level value.
Original Patch Author: sanjoy
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D34385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305879
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Davide Italiano [Tue, 20 Jun 2017 22:57:40 +0000 (22:57 +0000)]
[NewGVN] Fix a bug that made the store verifier less effective.
We weren't actually checking for duplicated stores, as the condition
was always actually false. This was found by Coverity, and I have
no clue how to trigger this in real-world code (although I
tried for a bit).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305867
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Kevin Enderby [Tue, 20 Jun 2017 22:55:11 +0000 (22:55 +0000)]
Updated llvm-objdump with Mach-O files and the -objc-meta-data option so
that it symbolically prints the superclass when it has dyld bind info for it.
rdar://
7638823
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305866
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Rafael Espindola [Tue, 20 Jun 2017 22:53:29 +0000 (22:53 +0000)]
clang-format a region.
It will make a followup patch easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305865
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Lang Hames [Tue, 20 Jun 2017 22:18:02 +0000 (22:18 +0000)]
Add a cantFail overload for Expected-reference (Expected<T&>) types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305863
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Reid Kleckner [Tue, 20 Jun 2017 21:19:22 +0000 (21:19 +0000)]
[codeview] YAMLize all section offsets and indices in symbol records
We forgot to serialize these because llvm-readobj didn't dump them. They
are typically all zeros in an object file. The linker fills them in with
relocations before adding them to the PDB. Now we can properly round
trip these symbols through pdb2yaml -> yaml2pdb.
I made these fields optional with a zero default so that we can elide
them from our test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305857
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Adrian Prantl [Tue, 20 Jun 2017 21:14:29 +0000 (21:14 +0000)]
Revert "Add previously accidentally uncommitted testcase for r305599."
This reverts commit r305852.
The testcase already exists but I moved it to the X86 directory on a
using a different machine and got confused...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305856
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Rafael Espindola [Tue, 20 Jun 2017 21:11:58 +0000 (21:11 +0000)]
Make this test a bit more strict. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305855
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Adrian Prantl [Tue, 20 Jun 2017 21:08:52 +0000 (21:08 +0000)]
Fix a crash in DwarfDebug::validThroughout.
The instruction it falls over on is an IMPLICT_DEF that also happens
to be the only instruction in its lexical scope. That LexicalScope has
never been created because its range is empty. This patch skips over
all meta-instructions instead of just DBG_VALUEs.
Thanks to David Blaikie for providing a testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305853
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Adrian Prantl [Tue, 20 Jun 2017 21:08:19 +0000 (21:08 +0000)]
Add previously accidentally uncommitted testcase for r305599.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305852
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Kevin Enderby [Tue, 20 Jun 2017 21:00:25 +0000 (21:00 +0000)]
Change llvm-objdump with Mach-O files and the -info-plist option with the
-no-leading-headers option so that it does not print the leading header.
rdar://
27378808
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305849
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Anna Thomas [Tue, 20 Jun 2017 20:54:57 +0000 (20:54 +0000)]
[Statepoint] Add helper functions for GCRelocate and GCResult
These functions isGCRelocate and isGCResult are
similar to isStatepoint(const Value*).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305847
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Saleem Abdulrasool [Tue, 20 Jun 2017 20:51:51 +0000 (20:51 +0000)]
Support: chunk writing on Linux
This is a workaround for large file writes. It has been witnessed that
write(2) failing with EINVAL (22) due to a large value (>2G). Thanks to
James Knight for the help with coming up with a sane test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305846
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Matt Arsenault [Tue, 20 Jun 2017 20:38:06 +0000 (20:38 +0000)]
AMDGPU: Allow vectorization of packed types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305844
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Reid Kleckner [Tue, 20 Jun 2017 20:34:37 +0000 (20:34 +0000)]
[codeview] Fully initialize DataSym when mapping from YAML
In the object file, the section index and relative offset are typically
zero, so make these YAML fields optional with a default.
It looks like there may be more partially initialized symbol records,
but this should fix the msan bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305842
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Stanislav Mekhanoshin [Tue, 20 Jun 2017 20:33:44 +0000 (20:33 +0000)]
[AMDGPU] Fix illegal shrink of V_SUBB_U32 and V_ADDC_U32
If there is an immediate operand we shall not shrink V_SUBB_U32
and V_ADDC_U32, it does not fit e32 encoding.
Differential Revison: https://reviews.llvm.org/D34291
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305840
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Michael Gottesman [Tue, 20 Jun 2017 20:28:07 +0000 (20:28 +0000)]
[cmake] Add support for using the standalone leaks sanitizer with LLVM.
This commit causes LLVM_USE_SANITIZER to now accept the "Leaks" option. This
will cause cmake to pass in -fsanitize=leak in all of the appropriate places.
I am making this change so that I can setup a linux bot that only detects
leaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305839
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Matt Arsenault [Tue, 20 Jun 2017 19:54:14 +0000 (19:54 +0000)]
AMDGPU: Start adding global_* instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305838
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Aditya Nandakumar [Tue, 20 Jun 2017 19:52:29 +0000 (19:52 +0000)]
[GISel]: NFC. Add comment to G_FMA opcode as requested in rL305824
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305837
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Aditya Nandakumar [Tue, 20 Jun 2017 19:25:23 +0000 (19:25 +0000)]
[GISel]: Add G_FMA opcode for fused multiply adds
https://reviews.llvm.org/D34372
Reviewed by dsanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305824
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Matt Arsenault [Tue, 20 Jun 2017 18:56:32 +0000 (18:56 +0000)]
AMDGPU: Do operand folding in program order
Before it was possible to partially fold use instructions
before the defs. After the xor is folded into a copy, the same
mov can end up in the fold list twice, so on the second attempt
it will fail expecting to see a register to fold.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305821
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Zachary Turner [Tue, 20 Jun 2017 18:50:55 +0000 (18:50 +0000)]
[PDB] Don't write uninitialized bytes to a PDB file.
There were certain fields that we didn't know how to write, as
well as various padding bytes that we would ignore. This leads
to garbage data in the PDB. While not strictly necessary, we
should initialize these bytes to something meaningful, as it
makes for easier binary comparison between PDBs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305819
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Zachary Turner [Tue, 20 Jun 2017 18:50:30 +0000 (18:50 +0000)]
Remove diff pedantic mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305818
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Matthias Braun [Tue, 20 Jun 2017 18:43:14 +0000 (18:43 +0000)]
RegisterScavenging: Followup to r305625
This does some improvements/cleanup to the recently introduced
scavengeRegisterBackwards() functionality:
- Rewrite findSurvivorBackwards algorithm to use the existing
LiveRegUnit::accumulateBackward() code. This also avoids the Available
and Candidates bitset and just need 1 LiveRegUnit instance
(= 1 bitset).
- Pick registers in allocation order instead of register number order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305817
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Matt Arsenault [Tue, 20 Jun 2017 18:41:31 +0000 (18:41 +0000)]
AMDGPU: Preserve undef when folding register operands
If the source was a copy of an undef register, this would
produce a read of an undefined register which is a verifier
error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305816
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Stanislav Mekhanoshin [Tue, 20 Jun 2017 18:32:42 +0000 (18:32 +0000)]
[AMDGPU] Eliminate SGPR to VGPR copy when possible
SGPRs are generally cheaper, so try to use them over VGPRs.
Differential Revision: https://reviews.llvm.org/D34130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305815
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Matt Arsenault [Tue, 20 Jun 2017 18:28:02 +0000 (18:28 +0000)]
AMDGPU: Fix crash with undef vreg input operand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305814
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Hiroshi Inoue [Tue, 20 Jun 2017 17:53:33 +0000 (17:53 +0000)]
[PowerPC] fix trivial typos in comment, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305813
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Simon Pilgrim [Tue, 20 Jun 2017 17:10:27 +0000 (17:10 +0000)]
[CostModel][X86] Add scalar arithmetic cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305810
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Simon Pilgrim [Tue, 20 Jun 2017 17:04:46 +0000 (17:04 +0000)]
[CostModel][X86] Declare costs variables based on type
The alphabetical progression isn't that useful
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305808
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Craig Topper [Tue, 20 Jun 2017 16:34:37 +0000 (16:34 +0000)]
[TableGen] Take a parameter by reference instead of pointer so we don't have to add & on both callers. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305807
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Craig Topper [Tue, 20 Jun 2017 16:34:35 +0000 (16:34 +0000)]
[TableGen] Use range based for loop. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305806
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Yuka Takahashi [Tue, 20 Jun 2017 16:31:31 +0000 (16:31 +0000)]
[GSoC] Flag value completion for clang
This is patch for GSoC project, bash-completion for clang.
To use this on bash, please run `source clang/utils/bash-autocomplete.sh`.
bash-autocomplete.sh is code for bash-completion.
In this patch, Options.td was mainly changed in order to add value class
in Options.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305805
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Sanjay Patel [Tue, 20 Jun 2017 15:58:30 +0000 (15:58 +0000)]
[x86] enable CGP memcmp() expansion for 2/4/8 byte sizes
There are a couple of potential improvements as seen in the IR and asm:
1. We're unnecessarily extending to a larger type to compare values.
2. The codegen for (select cond, 1, -1) could avoid a cmov.
(or we could change the order of the compares, so we have a select with 0 operand)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305802
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Simon Pilgrim [Tue, 20 Jun 2017 15:19:02 +0000 (15:19 +0000)]
[X86][SSE] Relax 0/-1 vector element insertion to work for any vector with >=16bit elements
Shuffle lowering/combining now does a good job for 256/512-bit vectors - we don't need to prevent this
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305801
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Tim Northover [Tue, 20 Jun 2017 15:01:38 +0000 (15:01 +0000)]
DAG: correctly legalize UMULO.
We were incorrectly sign extending into the high word (as you would for
SMULO) when legalizing UMULO in terms of a wider full multiplication.
Patch by James Duley.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305800
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Vassil Vassilev [Tue, 20 Jun 2017 14:20:48 +0000 (14:20 +0000)]
D33466: Make file non-executable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305795
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Sanjay Patel [Tue, 20 Jun 2017 12:45:46 +0000 (12:45 +0000)]
[InstCombine] fix code/test comments for r305792; NFC
These diffs were in the last version of the patch in D33342,
but I accidentally committed the previous rev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305793
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Sanjay Patel [Tue, 20 Jun 2017 12:40:55 +0000 (12:40 +0000)]
[InstCombine] try to canonicalize xor-of-icmps to and-of-icmps
We have a large portfolio of folds for and-of-icmps and or-of-icmps in InstSimplify and InstCombine,
but hardly anything for xor-of-icmps. Rather than trying to rethink and translate all of those folds,
we can use the truth table definition of xor:
X ^ Y --> (X | Y) & !(X & Y)
...to see if we can convert the xor to and/or and then use the existing folds.
http://rise4fun.com/Alive/J9v
Differential Revision: https://reviews.llvm.org/D33342
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305792
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Daniel Sanders [Tue, 20 Jun 2017 12:36:34 +0000 (12:36 +0000)]
[globalisel][tablegen] Add support for COPY_TO_REGCLASS.
Summary:
As part of this
* Emitted instructions now have named MachineInstr variables associated
with them. This isn't particularly important yet but it's a small step
towards multiple-insn emission.
* constrainSelectedInstRegOperands() is no longer hardcoded. It's now added
as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses
an alternate constraint mechanism ConstrainOperandToRegClassAction() which
supports arbitrary constraints such as that defined by COPY_TO_REGCLASS.
Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar
Reviewed By: ab
Subscribers: javed.absar, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D33590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305791
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Simon Pilgrim [Tue, 20 Jun 2017 12:28:33 +0000 (12:28 +0000)]
Fix Wdocumentation warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305790
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Simon Pilgrim [Tue, 20 Jun 2017 10:33:34 +0000 (10:33 +0000)]
[X86][SSE] Dropped old INSERT_VECTOR_ELT lowering TODO
Target shuffle combining now supports the matching of INSERT_VECTOR_ELT/PINSRW/PINSRB for merging multiple insertions into shuffles/bitmasks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305788
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Simon Pilgrim [Tue, 20 Jun 2017 10:24:06 +0000 (10:24 +0000)]
Fixed test name. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305787
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Igor Breger [Tue, 20 Jun 2017 09:40:57 +0000 (09:40 +0000)]
[GlobalISel][X86] fix compilation error ( -Werror=unused-function )
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305786
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Haojian Wu [Tue, 20 Jun 2017 09:29:43 +0000 (09:29 +0000)]
[SelectionDAG] Fix an use-after-free issue introduced in r305775.
vector.back() will be invalidated when memory reallocation happens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305785
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Igor Breger [Tue, 20 Jun 2017 09:15:10 +0000 (09:15 +0000)]
[GlobalISel][X86] Get correct RegClass for given RegBank.
Summary:
In some cases RegClass depends on target feature. Hight (16-31) vector registers exist only if AVX512f available.
Split from https://reviews.llvm.org/D33665
Reviewers: qcolombet, t.p.northover, zvi, guyblank
Reviewed By: t.p.northover, guyblank
Subscribers: guyblank, rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D33952
Conflicts:
test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305784
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Igor Breger [Tue, 20 Jun 2017 08:54:17 +0000 (08:54 +0000)]
[GlobalISel] combine not symmetric merge/unmerge nodes.
Summary:
In some cases legalization ends up with not symmetric merge/unmerge nodes.
Transform it to merge/unmerge nodes.
Reviewers: t.p.northover, qcolombet, zvi
Reviewed By: t.p.northover
Subscribers: rovka, kristof.beyls, guyblank, llvm-commits
Differential Revision: https://reviews.llvm.org/D33626
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305783
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Max Kazantsev [Tue, 20 Jun 2017 08:37:31 +0000 (08:37 +0000)]
[SCEV][NFC] Fix a misleading description of AddOpsInlineThreshold
The description of this option was copy-pasted from another one and does not
correspond to reality.
Differential Revision: https://reviews.llvm.org/D34390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305782
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Igor Breger [Tue, 20 Jun 2017 08:30:48 +0000 (08:30 +0000)]
[GlobalISel][X86] add legalizer mir tests. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305781
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NAKAMURA Takumi [Tue, 20 Jun 2017 07:21:19 +0000 (07:21 +0000)]
WasmObjectWriter.cpp: Tweak a comment line. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305777
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Alexandros Lamprineas [Tue, 20 Jun 2017 07:20:52 +0000 (07:20 +0000)]
[ARM] Support constant pools in data when generating execute-only code.
Resubmission of r305387, which was reverted at r305390. The Address
Sanitizer caught a stack-use-after-scope of a Twine variable. This
is now fixed by passing the Twine directly as a function parameter.
The ARM backend asserts against constant pool lowering when it generates
execute-only code in order to prevent the generation of constant pools in
the text section. It appears that target independent optimizations might
generate DAG nodes that represent constant pools. By lowering such nodes
as global addresses we don't violate the semantics of execute-only code
and also it is guaranteed that execute-only behaves correct with the
position-independent addressing modes that support execute-only code.
Differential Revision: https://reviews.llvm.org/D33773
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305776
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Max Kazantsev [Tue, 20 Jun 2017 07:07:09 +0000 (07:07 +0000)]
[SelectionDAG] Get rid of recursion in CalcNodeSethiUllmanNumber
The recursive implementation of CalcNodeSethiUllmanNumber may
overflow stack on extremely long pred chains. This patch replaces it
with an equivalent iterative implementation.
Differential Revision: https://reviews.llvm.org/D33769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305775
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Sam Clegg [Tue, 20 Jun 2017 05:05:10 +0000 (05:05 +0000)]
Fix unused function build error in lld
The lld-x86_64-darwin13 is failing with:
error: unused function 'operator<<'
Wrap the declation in ifndef NDEBUG, which matches
what is done in MipsELFObjectWriter.cpp.
Differential Revision: https://reviews.llvm.org/D34384
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305771
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Sam Clegg [Tue, 20 Jun 2017 04:47:58 +0000 (04:47 +0000)]
[WebAssembly] Fix build failures introduced in r305769
This fixes two build failures that only occur in certain
configurations:
- error: unused function 'operator<<'
- error: control reaches end of non-void function
Differential Revision: https://reviews.llvm.org/D34382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305770
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Sam Clegg [Tue, 20 Jun 2017 04:04:59 +0000 (04:04 +0000)]
[WebAssembly] Add support for weak symbols in the binary format
This also introduces the updated format for the
"linking" section which can represent extra
symbol information. See:
https://github.com/WebAssembly/tool-conventions/pull/10
Differential Revision: https://reviews.llvm.org/D34019
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305769
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Nirav Dave [Tue, 20 Jun 2017 02:48:39 +0000 (02:48 +0000)]
[DAG] Simplify BaseIndexOffset. NFCI.
Remove tail calls and cleanup codeflow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305768
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Vedant Kumar [Tue, 20 Jun 2017 02:05:35 +0000 (02:05 +0000)]
[Coverage] PR33517: Check for failure to load func records
With PR33517, it became apparent that symbol table creation can fail
when presented with malformed inputs. This patch makes that sort of
error detectable, so llvm-cov etc. can fail more gracefully.
Specifically, we now check that function records loaded from corrupted coverage
mapping data are rejected, e.g when the recorded function name is garbage.
Testing: check-{llvm,clang,profile}, some unit test updates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305767
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Vedant Kumar [Tue, 20 Jun 2017 01:38:56 +0000 (01:38 +0000)]
[ProfileData] PR33517: Check for failure of symtab creation
With PR33517, it became apparent that symbol table creation can fail
when presented with malformed inputs. This patch makes that sort of
error detectable, so llvm-cov etc. can fail more gracefully.
Specifically, we now check that function names within the symbol table
aren't empty.
Testing: check-{llvm,clang,profile}, some unit test updates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305765
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Pengxuan Zheng [Tue, 20 Jun 2017 01:04:25 +0000 (01:04 +0000)]
[test-release.sh] Enable Polly by default
Reviewers: grosser, hans, zinob, bollu
Reviewed By: grosser, hans
Subscribers: tstellar, llvm-commits
Differential Revision: https://reviews.llvm.org/D34306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305763
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Kevin Enderby [Tue, 20 Jun 2017 00:41:04 +0000 (00:41 +0000)]
The change to llvm-nm in r305733 added fields to the struct NMSymbol
that are not set on the main path. This diff does a memset to 0 the structs
so this change is to hopefully fix the sanitizer-x86_64-linux-fast bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305762
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Matt Arsenault [Mon, 19 Jun 2017 23:47:21 +0000 (23:47 +0000)]
AMDGPU: Fix scratch wave offset relative FI expansion
The offset may not be an inline immediate, so this needs
to be materialized into a register. The post-RA run of
SIShrinkInstructions is able to fold it later if it can.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305761
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Eugene Zelenko [Mon, 19 Jun 2017 23:37:52 +0000 (23:37 +0000)]
[ExecutionEngine] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305760
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Stanislav Mekhanoshin [Mon, 19 Jun 2017 23:17:36 +0000 (23:17 +0000)]
[AMDGPU] Add infer address spaces pass before SROA
It adds it for the target after inlining but before SROA where
we can get most out of it.
Differential Revision: https://reviews.llvm.org/D34366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305759
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Eugene Zelenko [Mon, 19 Jun 2017 22:43:19 +0000 (22:43 +0000)]
[Target] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305757
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Sanjoy Das [Mon, 19 Jun 2017 22:35:48 +0000 (22:35 +0000)]
Fix machine instruction in test case
The AMD64rm instruction used in the test case was incorrect. Since
the first input register to AND64rm is tied to output register, they
must be the same.
Thanks for Jesper Antonsson for pointing this out!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305756
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Eugene Zelenko [Mon, 19 Jun 2017 22:05:08 +0000 (22:05 +0000)]
[IR] Fix some Clang-tidy modernize-use-using warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305755
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Zachary Turner [Mon, 19 Jun 2017 22:01:50 +0000 (22:01 +0000)]
Mark LLVMTestingSupport as not installed in LLVMBuild.
This is causing downstream issues with llvm-config.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305754
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Zachary Turner [Mon, 19 Jun 2017 21:59:09 +0000 (21:59 +0000)]
Try to fix uninitialized read in unit test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305753
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Geoff Berry [Mon, 19 Jun 2017 21:57:44 +0000 (21:57 +0000)]
[AArch64][Falkor] Fix MOVZ sched predicate to not assert on non-imm operands (e.g. blockaddress).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305752
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Geoff Berry [Mon, 19 Jun 2017 21:57:42 +0000 (21:57 +0000)]
[AArch64][Kryo] Add missing write latency for LDAXP, LDXP second destination.
Fixes PR33491 and PR33512.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305751
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Geoff Berry [Mon, 19 Jun 2017 21:56:21 +0000 (21:56 +0000)]
[AArch64][Falkor] Refine load/store increment latencies.
Also fix LDXP & LDAXP write latency to avoid similar assert as PR33491 and PR33512.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305750
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Matt Arsenault [Mon, 19 Jun 2017 21:54:25 +0000 (21:54 +0000)]
Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305749
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Matt Arsenault [Mon, 19 Jun 2017 21:52:45 +0000 (21:52 +0000)]
AMDGPU: Cleanup CreateLiveInRegister
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305748
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Kevin Enderby [Mon, 19 Jun 2017 21:23:07 +0000 (21:23 +0000)]
Fix a FIXME in llvm-objdump for the -exports-trie option that was not adding
in the base address.
Without this Mach-O files, like 64-bit executables, don’t have the correct
addresses printed for their exports. As the default is to link at address
0x100000000 not zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305744
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Peter Collingbourne [Mon, 19 Jun 2017 20:43:09 +0000 (20:43 +0000)]
Revert r305598, "utils: Add a git-r utility for mapping svn revisions to git revisions in the monorepo."
$ git revert `git r 305598`
We need to decide whether we want development tools to be written in
Go first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305741
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Xin Tong [Mon, 19 Jun 2017 20:10:41 +0000 (20:10 +0000)]
[BDCE] Add comments. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305739
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Ana Pazos [Mon, 19 Jun 2017 20:04:33 +0000 (20:04 +0000)]
[PATCH] [PGO] Fixed cast operation in emIntrinsicVisitor::instrumentOneMemIntrinsic.
Reviewers: xur, efriedma, davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D34293
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305737
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