OSDN Git Service
Peter Collingbourne [Tue, 29 Nov 2016 02:27:04 +0000 (02:27 +0000)]
Bitcode: Change expected layout of module blocks.
We now expect each module's identification block to appear immediately before
the module block. Any module block that appears without an identification block
immediately before it is interpreted as if it does not have a module block.
Also change the interpretation of VST and function offsets in bitcode.
The offset is always taken as relative to the start of the identification
(or module if not present) block, minus one word. This corresponds to the
historical interpretation of offsets, i.e. relative to the start of the file.
These changes allow for bitcode modules to be concatenated by copying bytes.
Differential Revision: https://reviews.llvm.org/D27184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288098
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Tue, 29 Nov 2016 01:32:21 +0000 (01:32 +0000)]
[asan/win] Align global registration metadata to its size
This way, when the linker adds padding between globals, we can skip over
the zero padding bytes and reliably find the start of the next metadata
global.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288096
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Tue, 29 Nov 2016 00:46:46 +0000 (00:46 +0000)]
AMDGPU/SI: Avoid moving PHIs to VALU when phi values are defined in scalar branches
Reviewers: arsenm
Subscribers: arsenm, llvm-commits, kzhuravl
Differential Revision: https://reviews.llvm.org/D23417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288095
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Tue, 29 Nov 2016 00:29:27 +0000 (00:29 +0000)]
Recognize ${:uid} escapes in intel syntax inline asm
It looks like this logic was duplicated long ago and the GCC side of
things has grown additional functionality. We need ${:uid} at least to
generate unique MS inline asm labels (PR23715), so expose these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288092
91177308-0d34-0410-b5e6-
96231b3b80d8
Adam Nemet [Tue, 29 Nov 2016 00:09:22 +0000 (00:09 +0000)]
[GVN, OptDiag] Print the interesting instructions involved in missed load-elimination
This includes the intervening store and the load/store that we're trying
to forward from in the optimization remark for the missed load
elimination.
This is hooked up under a new mode in ORE that allows for compile-time
budget for a bit more analysis to print more insightful messages. This
mode is currently enabled for -fsave-optimization-record (-Rpass is
trickier since it is controlled in the front-end).
With this we can now print the red remark in http://lab.llvm.org:8080/artifacts/opt-view_test-suite/build/SingleSource/Benchmarks/Dhrystone/CMakeFiles/dry.dir/html/_org_test-suite_SingleSource_Benchmarks_Dhrystone_dry.c.html#L446
Differential Revision: https://reviews.llvm.org/D26490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288090
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Mon, 28 Nov 2016 23:05:55 +0000 (23:05 +0000)]
[DAG] clean up foldSelectCCToShiftAnd(); NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288088
91177308-0d34-0410-b5e6-
96231b3b80d8
Mehdi Amini [Mon, 28 Nov 2016 22:57:11 +0000 (22:57 +0000)]
Put ABI breaking test in Error checking behind LLVM_ENABLE_ABI_BREAKING_CHECKS
This macro is supposed to be the one controlling the compatibility
of ABI breaks induced when enabling or disabling assertions in LLVM.
The macro is enabled by default in assertions build, so this commit
won't disable the tests.
Differential Revision: https://reviews.llvm.org/D26700
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288087
91177308-0d34-0410-b5e6-
96231b3b80d8
Kevin Enderby [Mon, 28 Nov 2016 22:40:50 +0000 (22:40 +0000)]
Add error checking for Mach-O universal files.
Add the checking for both the MachO::fat_header and the
MachO::fat_arch struct values in the constructor for
MachOUniversalBinary. Such that when the constructor
for ObjectForArch is called it can assume the values in
the MachO::fat_arch for the offset and size are contained
in the file after the MachOUniversalBinary constructor
is called for the Parent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288084
91177308-0d34-0410-b5e6-
96231b3b80d8
Mehdi Amini [Mon, 28 Nov 2016 22:23:53 +0000 (22:23 +0000)]
Add link-time detection of LLVM_ABI_BREAKING_CHECKS mismatch
The macro LLVM_ENABLE_ABI_BREAKING_CHECKS is moved to a new header
abi-breaking.h, from llvm-config.h. Only headers that are using the
macro are including this new header.
LLVM will define a symbol, either EnableABIBreakingChecks or
DisableABIBreakingChecks depending on the configuration setting for
LLVM_ABI_BREAKING_CHECKS.
The abi-breaking.h header will add weak references to these symbols in
every clients that includes this header. This should ensure that
a mismatch triggers a link failure (or a load time failure for DSO).
On MSVC, the pragma "detect_mismatch" is used instead.
Differential Revision: https://reviews.llvm.org/D26876
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288082
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Mon, 28 Nov 2016 22:04:31 +0000 (22:04 +0000)]
[PM] Extend the explicit 'invalidate' method API on analysis results to
accept an Invalidator that allows them to invalidate themselves if their
dependencies are in turn invalidated.
Rather than recording the dependency graph ahead of time when analysis
get results from other analyses, this simply lets each result trigger
the immediate invalidation of any analyses they actually depend on. They
do this in a way that has three nice properties:
1) They don't have to handle transitive dependencies because the
infrastructure will recurse for them.
2) The invalidate methods are still called only once. We just
dynamically discover the necessary topological ordering, everything
is memoized nicely.
3) The infrastructure still provides a default implementation and can
access it so that only analyses which have dependencies need to do
anything custom.
To make this work at all, the invalidation logic also has to defer the
deletion of the result objects themselves so that they can remain alive
until we have collected the complete set of results to invalidate.
A unittest is added here that has exactly the dependency pattern we are
concerned with. It hit the use-after-free described by Sean in much
detail in the long thread about analysis invalidation before this
change, and even in an intermediate form of this change where we failed
to defer the deletion of the result objects.
There is an important problem with doing dependency invalidation that
*isn't* solved here: we don't *enforce* that results correctly
invalidate all the analyses whose results they depend on.
I actually looked at what it would take to do that, and it isn't as hard
as I had thought but the complexity it introduces seems very likely to
outweigh the benefit. The technique would be to provide a base class for
an analysis result that would be populated with other results, and
automatically provide the invalidate method which immediately does the
correct thing. This approach has some nice pros IMO:
- Handles the case we care about and nothing else: only *results*
that depend on other analyses trigger extra invalidation.
- Localized to the result rather than centralized in the analysis
manager.
- Ties the storage of the reference to another result to the triggering
of the invalidation of that analysis.
- Still supports extending invalidation in customized ways.
But the down sides here are:
- Very heavy-weight meta-programming is needed to provide this base
class.
- Requires a pretty awful API for accessing the dependencies.
Ultimately, I fear it will not pull its weight. But we can re-evaluate
this at any point if we start discovering consistent problems where the
invalidation and dependencies get out of sync. It will fit as a clean
layer on top of the facilities in this patch that we can add if and when
we need it.
Note that I'm not really thrilled with the names for these APIs... The
name "Invalidator" seems ok but not great. The method name "invalidate"
also. In review some improvements were suggested, but they really need
*other* uses of these terms to be updated as well so I'm going to do
that in a follow-up commit.
I'm working on the actual fixes to various analyses that need to use
these, but I want to try to get tests for each of them so we don't
regress. And those changes are seperable and obvious so once this goes
in I should be able to roll them out throughout LLVM.
Many thanks to Sean, Justin, and others for help reviewing here.
Differential Revision: https://reviews.llvm.org/D23738
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288077
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Mon, 28 Nov 2016 21:59:14 +0000 (21:59 +0000)]
cmake: Set rpath for loadable modules as well as shared libraries.
This fixes a regression introduced by r285714: we weren't setting the
rpath on LLVMgold.so correctly.
Spotted by mark@chromium.org!
Differential Revision: https://reviews.llvm.org/D27176
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288076
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Mon, 28 Nov 2016 21:50:34 +0000 (21:50 +0000)]
[SROA] Drop lifetime.start/end intrinsics when they block promotion.
Preserving lifetime markers isn't as important as allowing promotion,
so just drop the lifetime markers if necessary.
This also fixes an assertion failure where other parts of SROA assumed
that lifetime markers never block promotion.
Fixes https://llvm.org/bugs/show_bug.cgi?id=29139.
Differential Revision: https://reviews.llvm.org/D24854
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288074
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Mon, 28 Nov 2016 21:47:41 +0000 (21:47 +0000)]
[DAG] add helper function for selectcc --> and+shift transforms; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288073
91177308-0d34-0410-b5e6-
96231b3b80d8
Mehdi Amini [Mon, 28 Nov 2016 21:38:52 +0000 (21:38 +0000)]
Improve error handling in YAML parsing
Some scanner errors were not checked and reported by the parser.
Fix PR30934. Recommit r288014 after fixing unittest.
Patch by: Serge Guelton <serge.guelton@telecom-bretagne.eu>
Differential Revision: https://reviews.llvm.org/D26419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288071
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Mon, 28 Nov 2016 21:32:19 +0000 (21:32 +0000)]
[DebugInfo] Add support for DW_AT_main_subprogram on subprograms
Patch by Tom Tromey! (for use with Rust)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288068
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Mon, 28 Nov 2016 20:11:54 +0000 (20:11 +0000)]
MachineScheduler: Export function to construct "default" scheduler.
This makes the createGenericSchedLive() function that constructs the
default scheduler available for the public API. This should help when
you want to get a scheduler and the default list of DAG mutations.
This also shrinks the list of default DAG mutations:
{Load|Store}ClusterDAGMutation and MacroFusionDAGMutation are no longer
added by default. Targets can easily add them if they need them. It also
makes it easier for targets to add alternative/custom macrofusion or
clustering mutations while staying with the default
createGenericSchedLive(). It also saves the callback back and forth in
TargetInstrInfo::enableClusterLoads()/enableClusterStores().
Differential Revision: https://reviews.llvm.org/D26986
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288057
91177308-0d34-0410-b5e6-
96231b3b80d8
Artem Belevich [Mon, 28 Nov 2016 19:55:46 +0000 (19:55 +0000)]
Revert r287637 "[wasm] hack around test failure after r287553."
-cgp-freq-ratio-to-skip-merge option was removed by rollback in r288052.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288055
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Mon, 28 Nov 2016 18:58:49 +0000 (18:58 +0000)]
[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies
Codegen prepare sinks comparisons close to a user is we have only one register
for conditions. For AMDGPU we have many SGPRs capable to hold vector conditions.
Changed BE to report we have many condition registers. That way IR LICM pass
would hoist an invariant comparison out of a loop and codegen prepare will not
sink it.
With that done a condition is calculated in one block and used in another.
Current behavior is to store workitem's condition in a VGPR using v_cndmask_b32
and then restore it with yet another v_cmp instruction from that v_cndmask's
result. To mitigate the issue a propagation of source SGPR pair in place of v_cmp
is implemented. Additional side effect of this is that we may consume less VGPRs
at a cost of more SGPRs in case if holding of multiple conditions is needed, and
that is a clear win in most cases.
Differential Revision: https://reviews.llvm.org/D26114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288053
91177308-0d34-0410-b5e6-
96231b3b80d8
Joerg Sonnenberger [Mon, 28 Nov 2016 18:56:54 +0000 (18:56 +0000)]
Revert r287553: [CodeGenPrep] Skip merging empty case blocks
It results in assertions in lib/Analysis/BlockFrequencyInfoImpl.cpp line
670 ("Expected irreducible CFG").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288052
91177308-0d34-0410-b5e6-
96231b3b80d8
Justin Lebar [Mon, 28 Nov 2016 18:50:03 +0000 (18:50 +0000)]
[StructurizeCFG] Use range-based for loops.
Reviewers: arsenm
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D27000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288051
91177308-0d34-0410-b5e6-
96231b3b80d8
Justin Lebar [Mon, 28 Nov 2016 18:49:59 +0000 (18:49 +0000)]
[StructurizeCFG] Refactor NearestCommonDominator.
Summary:
As far as I can tell, doing our own computations in
NearestCommonDominator is a false optimization -- DomTree will build up
what appears to be exactly this data when it decides it's worthwhile.
Moreover, by building the cache ourselves, we cannot take advantage of
the cache that the domtree might have available.
In addition, I am not convinced of the correctness of the original code.
In particular, setting ResultIndex = 1 on the first addBlock instead of
setting it to 0 is quite fishy. Similarly, it's not clear to me that
setting IndexMap[Node] = 0 for every node as we walk up the tree finding
a common parent is correct. But rather than ponder over these
questions, I'd rather just make the code do the obviously-correct thing.
This patch also changes the NearestCommonDominator API a bit, improving
the names and getting rid of the boolean parameter in addBlock -- see
http://jlebar.com/2011/12/16/Boolean_parameters_to_API_functions_considered_harmful..html
Reviewers: arsenm
Subscribers: aemerson, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D26998
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288050
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Mon, 28 Nov 2016 17:58:19 +0000 (17:58 +0000)]
[X86][SSE] Add initial support for combining (V)PMOVZX with shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288049
91177308-0d34-0410-b5e6-
96231b3b80d8
Adam Nemet [Mon, 28 Nov 2016 17:45:34 +0000 (17:45 +0000)]
[GVN, OptDiag] Include the value that is forwarded in load elimination
This requires some changes to the opt-diag API. Hal and I have
discussed this at the Dev Meeting and came up with a streaming delimiter
(setExtraArgs) to solve this.
Arguments after this delimiter are only included in the optimization
records and not in the remarks printed in the compiler output. (Note,
how in the test the content of the YAML file changes but the remarks on
the compiler output don't.)
This implements the green GVN message with a bug fix at line
http://lab.llvm.org:8080/artifacts/opt-view_test-suite/build/SingleSource/Benchmarks/Dhrystone/CMakeFiles/dry.dir/html/_org_test-suite_SingleSource_Benchmarks_Dhrystone_dry.c.html#L446
The fix is that now we properly include the constant value in the
message: "load of type i32 eliminated in favor of 7"
Differential Revision: https://reviews.llvm.org/D26489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288047
91177308-0d34-0410-b5e6-
96231b3b80d8
Adam Nemet [Mon, 28 Nov 2016 17:45:28 +0000 (17:45 +0000)]
[GVN] Basic optimization remark support
Follow-on patches will add more interesting cases.
The goal of this patch-set is to get the GVN messages printed in
opt-viewer from Dhrystone as was presented in my Dev Meeting talk. This
is the optimization view for the function (the last remark in the
function has a bug which is fixed in this series):
http://lab.llvm.org:8080/artifacts/opt-view_test-suite/build/SingleSource/Benchmarks/Dhrystone/CMakeFiles/dry.dir/html/_org_test-suite_SingleSource_Benchmarks_Dhrystone_dry.c.html#L430
Differential Revision: https://reviews.llvm.org/D26488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288046
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Mon, 28 Nov 2016 17:39:21 +0000 (17:39 +0000)]
[x86] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288045
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniil Fukalov [Mon, 28 Nov 2016 17:12:09 +0000 (17:12 +0000)]
[CMAKE] fix LLVM_OPTIMIZED_TABLEGEN for Visual Studio
At the moment optimized tablegen is generated by LLVM_USE_HOST_TOOLS variable that is not set for Visual Sudio since LLVM_ENABLE_ASSERTIONS depends on CMAKE_BUILD_TYPE value that is not equal to "DEBUG" in case of Visual Studio soltion generation.
Modified to do not depend on LLVM_ENABLE_ASSERTIONS value in VS and Xcode cases
Reviewers: beanz
Subscribers: RKSimon, llvm-commits, mgorny
Differential Revision: https://reviews.llvm.org/D27135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288042
91177308-0d34-0410-b5e6-
96231b3b80d8
Adam Nemet [Mon, 28 Nov 2016 16:51:49 +0000 (16:51 +0000)]
[LTO] Move finishOptimizationRemarks after codegen
This addresses the comment D26832.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288041
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Mon, 28 Nov 2016 16:25:01 +0000 (16:25 +0000)]
[X86][SSE] Added support for combining bit-shifts with shuffles.
Bit-shifts by a whole number of bytes can be represented as a shuffle mask suitable for combining.
Added a 'getFauxShuffleMask' function to allow us to create shuffle masks from other suitable operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288040
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Mon, 28 Nov 2016 15:50:39 +0000 (15:50 +0000)]
[X86][SSE] Added tests showing missed combines of shifts with shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288037
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Cederman [Mon, 28 Nov 2016 15:33:03 +0000 (15:33 +0000)]
Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288036
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Mon, 28 Nov 2016 14:30:29 +0000 (14:30 +0000)]
Revert "[DAG] Improve loads-from-store forwarding to handle TokenFactor"
This reverts commit r287773 which caused issues with ppc64le builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288035
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Mon, 28 Nov 2016 14:24:14 +0000 (14:24 +0000)]
[SystemZ] Fix build bot fallout from r288030
Remove unused variable that came in due to a copy-and-paste bug
and caused build bot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288033
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Mon, 28 Nov 2016 14:01:51 +0000 (14:01 +0000)]
[SystemZ] Support execution hint instructions
This adds assembler support for the instructions provided by the
execution-hint facility (NIAI and BP(R)P). This required adding
support for the new relocation types for 12-bit and 24-bit PC-
relative offsets used by the BP(R)P instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288031
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Mon, 28 Nov 2016 13:59:22 +0000 (13:59 +0000)]
[SystemZ] Support load-and-trap instructions
This adds support for the instructions provided with the
load-and-trap facility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288030
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Mon, 28 Nov 2016 13:40:08 +0000 (13:40 +0000)]
[SystemZ] Add remaining branch instructions
This patch adds assembler support for the remaining branch instructions:
the non-relative branch on count variants, and all variants of branch
on index.
The only one of those that can be readily exploited for code generation
is BRCTH (branch on count using a high 32-bit register as count). Do
use it, however, it is necessary to also introduce a hew CHIMux pseudo
to allow comparisons of a 32-bit value agains a short immediate to go
into a high register as well (implemented via CHI/CIH).
This causes a bit of codegen changes overall, but those have proven to
be neutral (or even beneficial) in performance measurements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288029
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Mon, 28 Nov 2016 13:34:08 +0000 (13:34 +0000)]
[SystemZ] Improve use of conditional instructions
This patch moves formation of LOC-type instructions from (late)
IfConversion to the early if-conversion pass, and in some cases
additionally creates them directly from select instructions
during DAG instruction selection.
To make early if-conversion work, the patch implements the
canInsertSelect / insertSelect callbacks. It also implements
the commuteInstructionImpl and FoldImmediate callbacks to
enable generation of the full range of LOC instructions.
Finally, the patch adds support for all instructions of the
load-store-on-condition-2 facility, which allows using LOC
instructions also for high registers.
Due to the use of the GRX32 register class to enable high registers,
we now also have to handle the cases where there are still no single
hardware instructions (conditional move from a low register to a high
register or vice versa). These are converted back to a branch sequence
after register allocation. Since the expandRAPseudos callback is not
allowed to create new basic blocks, this requires a simple new pass,
modelled after the ARM/AArch64 ExpandPseudos pass.
Overall, this patch causes significantly more LOC-type instructions
to be used, and results in a measurable performance improvement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288028
91177308-0d34-0410-b5e6-
96231b3b80d8
James Molloy [Mon, 28 Nov 2016 11:07:37 +0000 (11:07 +0000)]
[InlineCost] Reduce inline thresholds to compensate for cost changes
In r286814, the algorithm for calculating inline costs changed. This
caused more inlining to take place which is especially apparent
in optsize and minsize modes.
As the cost calculation removed a skewed behaviour (we were inconsistent
about the cost of calls) it isn't possible to update the thresholds to
get exactly the same behaviour as before. However, this threshold change
accounts for the very common case where an inline candidate has no
calls within it. In this case, r286814 would inline around 5-6 more (IR)
instructions.
The changes to -Oz have been heavily benchmarked. The "obvious" value
for the inline threshold at -Oz is zero, but due to inaccuracies in the
inline heuristics this can actually cause code size increases due to
not inlining key thunk functions (that then disappear). Experimentally,
5 was the sweet spot for code size over the test-suite.
For -Os, this change removes the outlier results shown up by green dragon
(http://104.154.54.203/db_default/v4/nts/13248).
Fixes D26848.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288024
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Mon, 28 Nov 2016 10:42:21 +0000 (10:42 +0000)]
[PM] Remove weird marking of invalidated analyses as "preserved".
This never made a lot of sense. They've been invalidated for one IR unit
but they aren't really preserved in any normal sense. It seemed like it
would be an elegant way of communicating to outer IR units that pass
managers and adaptors had already handled invalidation, but we've since
ended up adding sets that model this more clearly: we're now using
the 'AllAnalysesOn<IRUnitT>' set to handle cases where the trick of
"preserving" invalidated analyses didn't work.
This patch moves to rely on that technique exclusively and removes the
cumbersome API aspect of updating the preserved set when doing
invalidation. This in turn will simplify a *number* of upcoming patches.
This has a side benefit of exposing a number of places where we were
failing to mark the 'AllAnalysesOn<IRUnitT>' set as preserved. This
patch fixes those, and with those fixes shouldn't change any observable
behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288023
91177308-0d34-0410-b5e6-
96231b3b80d8
Davide Italiano [Mon, 28 Nov 2016 09:17:12 +0000 (09:17 +0000)]
[ThreadPool] Rollback recent changes until I figure out the breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288018
91177308-0d34-0410-b5e6-
96231b3b80d8
Davide Italiano [Mon, 28 Nov 2016 08:57:05 +0000 (08:57 +0000)]
[ThreadPool] Remove outdated comment after r288016.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288017
91177308-0d34-0410-b5e6-
96231b3b80d8
Davide Italiano [Mon, 28 Nov 2016 08:53:41 +0000 (08:53 +0000)]
[ThreadPool] Simplify the interface. NFCI.
The callers don't use the return value. Found by Michael
Spencer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288016
91177308-0d34-0410-b5e6-
96231b3b80d8
Mehdi Amini [Mon, 28 Nov 2016 04:57:04 +0000 (04:57 +0000)]
Revert "Improve error handling in YAML parsing"
This reverts commit r288014, the unittest isn't passing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288015
91177308-0d34-0410-b5e6-
96231b3b80d8
Mehdi Amini [Mon, 28 Nov 2016 04:44:13 +0000 (04:44 +0000)]
Improve error handling in YAML parsing
Some scanner errors were not checked and reported by the parser.
Fix PR30934
Patch by: Serge Guelton <serge.guelton@telecom-bretagne.eu>
Differential Revision: https://reviews.llvm.org/D26419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288014
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Mon, 28 Nov 2016 03:40:33 +0000 (03:40 +0000)]
[PM] Add an ASCII-art diagram for the call graph in the CGSCC unit test.
No functionality changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288013
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 27 Nov 2016 21:37:04 +0000 (21:37 +0000)]
[X86][FMA4] Remove isCommutable from FMA4 scalar intrinsics. They aren't commutable as operand 0 should pass its upper bits through to the output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288011
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 27 Nov 2016 21:37:02 +0000 (21:37 +0000)]
[X86][FMA] Add missing Predicates qualifier around scalar FMA intrinsic patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288010
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 27 Nov 2016 21:37:00 +0000 (21:37 +0000)]
[X86][FMA4] Add load folding support for FMA4 scalar intrinsic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288009
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 27 Nov 2016 21:36:58 +0000 (21:36 +0000)]
[X86][FMA4] Add test cases to demonstrate missed folding opportunities for FMA4 scalar intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288008
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 27 Nov 2016 21:36:54 +0000 (21:36 +0000)]
[X86] Add SHL by 1 to the load folding tables.
I don't think isel selects these today, favoring adding the register to itself instead. But the load folding tables shouldn't be so concerned with what isel will use and just represent the relationships.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288007
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 27 Nov 2016 21:08:19 +0000 (21:08 +0000)]
[X86][SSE] Add support for combining target shuffles to 128/256-bit PSLL/PSRL bit shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288006
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sun, 27 Nov 2016 21:07:28 +0000 (21:07 +0000)]
[InstSimplify] allow integer vector types to use computeKnownBits
Note that the non-splat lshr+lshr test folded, but that does not
work in general. Something is missing or wrong in computeKnownBits
as the non-splat shl+shl test still shows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288005
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 27 Nov 2016 19:51:41 +0000 (19:51 +0000)]
[AVX-512] Add integer and fp unpck instructions to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288004
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 27 Nov 2016 19:28:39 +0000 (19:28 +0000)]
[X86][SSE] Split lowerVectorShuffleAsShift ready for combines. NFCI.
Moved most of matching code into matchVectorShuffleAsShift to share with target shuffle combines (in a future commit).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288003
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 27 Nov 2016 18:51:13 +0000 (18:51 +0000)]
[X86] Add TB_NO_REVERSE to entries in the load folding table where the instruction's load size is smaller than the register size.
If we were to unfold these, the load size would be increased to the register size. This is not safe to do since the enlarged load can do things like cross a page boundary into a page that doesn't exist.
I probably missed some instructions, but this should be a large portion of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288001
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 27 Nov 2016 18:25:02 +0000 (18:25 +0000)]
[X86][SSE] Added tests showing missed combines for shuffle to shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288000
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sun, 27 Nov 2016 15:54:45 +0000 (15:54 +0000)]
add tests to show missing analysis; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287998
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sun, 27 Nov 2016 15:53:48 +0000 (15:53 +0000)]
fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287997
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 27 Nov 2016 08:55:31 +0000 (08:55 +0000)]
[AVX-512] Add masked EVEX vpmovzx/sx instructions to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287995
91177308-0d34-0410-b5e6-
96231b3b80d8
Mohammad Shahid [Sun, 27 Nov 2016 03:35:31 +0000 (03:35 +0000)]
[SLP] Add new and update existing lit testfor providing more context to incoming patch for vectorization of jumbled load
Change-Id: Ifb9091bb0f84c1937c2c8bd2fc345734f250d2f9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287992
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 27 Nov 2016 01:52:51 +0000 (01:52 +0000)]
[X86] Remove alignment restrictions from load folding table for some instructions that don't have a restriction.
Most of these are the SSE4.1 PMOVZX/PMOVSX instructions which all read less than 128-bits. The only other was PMOVUPD which by definition is an unaligned load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287991
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 26 Nov 2016 18:43:26 +0000 (18:43 +0000)]
[X86] Remove hasOneUse check that is redundant with the one in IsProfitableToFold.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287987
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 26 Nov 2016 18:43:24 +0000 (18:43 +0000)]
[X86] Fix the zero extending load detection in X86DAGToDAGISel::selectScalarSSELoad to pass the load node to IsProfitableToFold and IsLegalToFold.
Previously we were passing the SCALAR_TO_VECTOR node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287986
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 26 Nov 2016 18:43:21 +0000 (18:43 +0000)]
[X86] Simplify control flow. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287985
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 26 Nov 2016 17:29:25 +0000 (17:29 +0000)]
[X86] Add a hasOneUse check to selectScalarSSELoad to keep the same load from being folded multiple times.
Summary: When selectScalarSSELoad is looking for a scalar_to_vector of a scalar load, it makes sure the load is only used by the scalar_to_vector. But it doesn't make sure the scalar_to_vector is only used once. This can cause the same load to be folded multiple times. This can be bad for performance. This also causes the chain output to be duplicated, but not connected to anything so chain dependencies will not be satisfied.
Reviewers: RKSimon, zvi, delena, spatel
Subscribers: andreadb, llvm-commits
Differential Revision: https://reviews.llvm.org/D26790
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287983
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 26 Nov 2016 16:13:23 +0000 (16:13 +0000)]
[InstCombine] add test to show missing vector optimization; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287982
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 26 Nov 2016 15:23:20 +0000 (15:23 +0000)]
[InstCombine] don't drop metadata in FoldOpIntoSelect()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287980
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 26 Nov 2016 15:01:59 +0000 (15:01 +0000)]
add optional param to copy metadata when creating selects; NFC
There are other spots where we can use this; we're currently dropping
metadata in some places, and there are proposed changes where we will
want to propagate metadata.
IRBuilder's CreateSelect() already has a parameter like this, so this
change makes the regular 'Create' API line up with that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287976
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 26 Nov 2016 08:21:52 +0000 (08:21 +0000)]
[AVX-512] Add unmasked EVEX vpmovzx/sx instructions to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287975
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 26 Nov 2016 08:21:48 +0000 (08:21 +0000)]
[AVX-512] Add masked 128/256-bit integer add/sub instructions to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287974
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 26 Nov 2016 07:21:00 +0000 (07:21 +0000)]
[AVX-512] Add masked 512-bit integer add/sub instructions to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287972
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 26 Nov 2016 07:20:57 +0000 (07:20 +0000)]
[AVX-512] Teach LowerFormalArguments to use the extended register class when available. Fix the avx512vl stack folding tests to clobber more registers or otherwise they use xmm16 after this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287971
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 26 Nov 2016 07:20:53 +0000 (07:20 +0000)]
[AVX-512] Add VLX versions of VDIVPD/PS and VMULPD/PS to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287970
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Sat, 26 Nov 2016 02:26:04 +0000 (02:26 +0000)]
AMDGPU/SI: Use float as the operand type for amdgcn.interp intrinsics
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D26724
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287962
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 26 Nov 2016 02:14:00 +0000 (02:14 +0000)]
[X86][XOP] Add a reversed reg/reg form for VPROT instructions.
The W bit distinquishes which operand is the memory operand. But if the mod bits are 3 then the memory operand is a register and there are two possible encodings. We already did this correctly for several other XOP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287961
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 26 Nov 2016 02:13:58 +0000 (02:13 +0000)]
[X86] Add SSE, AVX, and AVX2 version of MOVDQU to the load/store folding tables for consistency.
Not sure this is truly needed but we had the floating point equivalents, the aligned equivalents, and the EVEX equivalents. So this just makes it complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287960
91177308-0d34-0410-b5e6-
96231b3b80d8
Dylan McKay [Sat, 26 Nov 2016 01:07:32 +0000 (01:07 +0000)]
Un-XFAIL an AVR CodeGen test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287958
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 25 Nov 2016 23:21:34 +0000 (23:21 +0000)]
[AVX-512] Put the AVX-512 sections of the load folding tables into mostly alphabetical order. This is consistent with the older sections of the table. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287956
91177308-0d34-0410-b5e6-
96231b3b80d8
David Majnemer [Fri, 25 Nov 2016 22:35:09 +0000 (22:35 +0000)]
Replace some callers of setTailCall with setTailCallKind
We were a little sloppy with adding tailcall markers. Be more
consistent by using setTailCallKind instead of setTailCall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287955
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 25 Nov 2016 21:12:39 +0000 (21:12 +0000)]
[SimplifyCFG] auto-generate better checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287954
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 25 Nov 2016 21:07:13 +0000 (21:07 +0000)]
[SimplifyCFG] auto-generate better checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287953
91177308-0d34-0410-b5e6-
96231b3b80d8
Marek Olsak [Fri, 25 Nov 2016 17:37:09 +0000 (17:37 +0000)]
AMDGPU/SI: Add back reverted SGPR spilling code, but disable it
suggested as a better solution by Matt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287942
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 25 Nov 2016 17:25:21 +0000 (17:25 +0000)]
Use SDValue helpers instead of explicitly going via SDValue::getNode(). NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287941
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 25 Nov 2016 17:19:53 +0000 (17:19 +0000)]
Use SDValue helper instead of explicitly going via SDValue::getNode(). NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287940
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 25 Nov 2016 16:48:05 +0000 (16:48 +0000)]
[AVX-512] Add support for changing VSHUFF64x2 to VSHUFF32x4 when its feeding a vselect with 32-bit element size.
Summary:
Shuffle lowering may have widened the element size of a i32 shuffle to i64 before selecting X86ISD::SHUF128. If this shuffle was used by a vselect this can prevent us from selecting masked operations.
This patch detects this and changes the element size to match the vselect.
I don't handle changing integer to floating point or vice versa as its not clear if its better to push such a bitcast to the inputs of the shuffle or to the user of the vselect. So I'm ignoring that case for now.
Reviewers: delena, zvi, RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287939
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 25 Nov 2016 16:33:53 +0000 (16:33 +0000)]
[AVX-512] Add VPERMT2* and VPERMI2* instructions to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287937
91177308-0d34-0410-b5e6-
96231b3b80d8
Marek Olsak [Fri, 25 Nov 2016 16:03:34 +0000 (16:03 +0000)]
Revert "AMDGPU: Implement SGPR spilling with scalar stores"
This reverts commit
4404d0d6e354e80dd7f8f0a0e12d8ad809cf007e.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287936
91177308-0d34-0410-b5e6-
96231b3b80d8
Marek Olsak [Fri, 25 Nov 2016 16:03:27 +0000 (16:03 +0000)]
Revert "AMDGPU: Fix MMO when splitting spill"
This reverts commit
79d4f8b8b1ce430c3d5dac4fc72a9eebaed24fe1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287935
91177308-0d34-0410-b5e6-
96231b3b80d8
Marek Olsak [Fri, 25 Nov 2016 16:03:22 +0000 (16:03 +0000)]
Revert "AMDGPU: Fix adding extra implicit def of register"
This reverts commit
e834ce5976567575621901fb967b8018b9916d71.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287934
91177308-0d34-0410-b5e6-
96231b3b80d8
Marek Olsak [Fri, 25 Nov 2016 16:03:19 +0000 (16:03 +0000)]
Revert "AMDGPU: Fix not setting kill flag on temp reg when spilling"
This reverts commit
057bbbe4ae170247ba37f08f2e70ef185267d1bb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287933
91177308-0d34-0410-b5e6-
96231b3b80d8
Marek Olsak [Fri, 25 Nov 2016 16:03:15 +0000 (16:03 +0000)]
Revert "AMDGPU: Make m0 unallocatable"
This reverts commit
124ad83dae04514f943902446520c859adee0e96.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287932
91177308-0d34-0410-b5e6-
96231b3b80d8
Marek Olsak [Fri, 25 Nov 2016 16:03:06 +0000 (16:03 +0000)]
Revert "AMDGPU: Remove m0 spilling code"
This reverts commit
f18de36554eb22416f8ba58e094e0272523a4301.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287931
91177308-0d34-0410-b5e6-
96231b3b80d8
Marek Olsak [Fri, 25 Nov 2016 16:03:02 +0000 (16:03 +0000)]
Revert "AMDGPU: Preserve m0 value when spilling"
This reverts commit
a5a179ffd94fd4136df461ec76fb30f04afa87ce.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287930
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 25 Nov 2016 15:07:15 +0000 (15:07 +0000)]
[X86][SSE] Added knownbits through bitcast test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287928
91177308-0d34-0410-b5e6-
96231b3b80d8
Abhilash Bhandari [Fri, 25 Nov 2016 14:07:44 +0000 (14:07 +0000)]
[Loop Unswitch] Patch to selective unswitch only the reachable branch instructions.
Summary:
The iterative algorithm for Loop Unswitching may render some of the branches unreachable in the unswitched loops.
Given the exponential nature of the algorithm, this is quite an overhead.
This patch fixes this problem by selectively unswitching only those branches within a loop that are reachable from the loop header.
Reviewers: Michael Zolothukin, Anna Thomas, Weiming Zhao.
Subscribers: llvm-commits.
Differential Revision: http://reviews.llvm.org/D26299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287925
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 25 Nov 2016 11:10:43 +0000 (11:10 +0000)]
[X86][SSE] Added v16i8 shuffle test case from PR31151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287919
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Dardis [Fri, 25 Nov 2016 11:06:43 +0000 (11:06 +0000)]
[mips] Correct jal expansion for local symbols in .local directives.
This patch corrects the behaviour of code such as:
.local foo
jal foo
foo:
to use the correct jal expansion when writing ELF files.
Patch by: Daniel Sanders
Reviewers: zoran.jovanovic, seanbruno, vkalintiris
Differential Revision: https://reviews.llvm.org/D24722
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287918
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 25 Nov 2016 02:29:24 +0000 (02:29 +0000)]
[X86] Invert an 'if' and early out to fix a weird indentation. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287909
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 25 Nov 2016 02:29:21 +0000 (02:29 +0000)]
[X86] Size a SmallVector to the worst case mask size for a 512-bit shuffle. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287908
91177308-0d34-0410-b5e6-
96231b3b80d8
Kuba Mracek [Thu, 24 Nov 2016 22:50:22 +0000 (22:50 +0000)]
Add "compiler-rt", "libcxx" and "libcxxabi" to svn:ignore under projects/
Differential Revision: https://reviews.llvm.org/D27069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287905
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 24 Nov 2016 21:48:52 +0000 (21:48 +0000)]
[DAGCombine] Teach DAG combine that if both inputs of a vselect are the same, then the condition doesn't matter and the vselect can be removed.
Selects with scalar condition already handle this correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287904
91177308-0d34-0410-b5e6-
96231b3b80d8