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Jakob Bornecrantz [Fri, 25 Feb 2011 23:50:52 +0000 (00:50 +0100)]
util: Don't create array texture shaders if the driver doesn't support it
Kenneth Graunke [Fri, 25 Feb 2011 01:49:07 +0000 (17:49 -0800)]
i965/fs: Initial plumbing to support TXD.
This adds the opcode and the code to convert ir_txd to OPCODE_TXD;
it doesn't actually add support yet.
Kenneth Graunke [Thu, 28 Oct 2010 19:53:21 +0000 (12:53 -0700)]
i965/fs: Complete TXL support on gen5+.
Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was
never handled.
Kenneth Graunke [Thu, 28 Oct 2010 20:12:20 +0000 (13:12 -0700)]
i965/fs: Complete TXL support on gen4.
Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was
never handled.
Kenneth Graunke [Thu, 28 Oct 2010 20:07:11 +0000 (13:07 -0700)]
i965/fs: Use a properly named constant in TXB handling.
The old value, BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE makes it sound like we're
doing a non-bias texture lookup. It has the same value as the new constant
BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE, so there should be no
functional changes.
Kenneth Graunke [Thu, 28 Oct 2010 20:04:41 +0000 (13:04 -0700)]
i965: Add #defines for gen4 SIMD8 TXB/TXL with shadow comparison.
From volume 4, page 161 of the public i965 documentation.
Jerome Glisse [Fri, 25 Feb 2011 16:56:29 +0000 (11:56 -0500)]
gallium/tgsi: shuffle ureg_src structure to work around gcc4.6.0 issue
There is an issue with gcc 4.6.0 that leads to segfault/assert with mesa
due to ureg_src size, reshuffling the structure member to better better
alignment work around the issue.
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47893
7.9 + 7.10 candidate
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Jerome Glisse [Fri, 25 Feb 2011 16:49:23 +0000 (11:49 -0500)]
gallium/st: place value check before value is use
7.9 & 7.10 candidate
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Dave Airlie [Fri, 25 Feb 2011 04:37:06 +0000 (14:37 +1000)]
gallium/util: add 1d/2d mipmap generation support
so far only hw mipmap generation is testing on softpipe,
passes test added to piglit.
this requires another patch to mesa to let array textures mipmaps
even start to happen.
Vinson Lee [Fri, 25 Feb 2011 03:49:37 +0000 (19:49 -0800)]
scons: Reduce all Cygwin platform names to 'cygwin'.
platform.system in SCons on Cygwin includes the OS version number.
Windows XP - CYGWIN_NT-5.1
Windows Vista - CYGWIN_NT-6.0
Windows 7 - CYGWIN_NT-6.1
Reduce all Cygwin platform variants to just 'cygwin' so anything
downstream can simply use 'cygwin' instead of the different full
platform names.
Dave Airlie [Thu, 24 Feb 2011 23:13:14 +0000 (09:13 +1000)]
r600g: explicity set sign bits for RGTC
Dave Airlie [Thu, 24 Feb 2011 03:55:25 +0000 (13:55 +1000)]
r600g: bc 4/5 or rgtc textures need to be tiled as well.
Make the s3tc upload code more generic.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 24 Feb 2011 23:14:53 +0000 (09:14 +1000)]
r300g: explicit sign bits on RGTC textures
Kenneth Graunke [Thu, 24 Feb 2011 19:17:02 +0000 (11:17 -0800)]
i965: Increase Sandybridge point size clamp in the clip state.
255.875 matches the hardware documentation. Presumably this was a typo.
NOTE: This is a candidate for the 7.10 branch, along with
commit
2bfc23fb86964e4153f57f2a56248760f6066033.
Reviewed-by: Eric Anholt <eric@anholt.net>
Neil Roberts [Sat, 5 Feb 2011 10:21:11 +0000 (10:21 +0000)]
intel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebuffer
In the case where glBlitFramebuffer is being used to copy to a texture
without scaling it is faster if we can use the hardware to do a blit
rather than having to do a texture render. In most of the drivers
glCopyTexSubImage2D will use a blit so this patch makes it check for
when glBlitFramebuffer is doing a simple copy and then divert to
glCopyTexSubImage2D.
This was originally proposed as an extension to the common meta-ops.
However, it was rejected as using the BLT is only advantageous for Intel
hardware.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33934
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Christoph Bumiller [Wed, 23 Feb 2011 13:54:25 +0000 (14:54 +0100)]
nvc0: fix PointCoord enable in FP header
Christoph Bumiller [Wed, 23 Feb 2011 16:29:02 +0000 (17:29 +0100)]
nvc0: change TGSI CMP translation to use slct
Saves us the explicit compare instruction needed with selp.
Christoph Bumiller [Wed, 23 Feb 2011 14:00:26 +0000 (15:00 +0100)]
nvc0: sprite coord enable is per GENERIC, not overall index
Christoph Bumiller [Thu, 24 Feb 2011 14:28:04 +0000 (15:28 +0100)]
nvc0: fix new_value calls using type instead of size
Christoph Bumiller [Thu, 24 Feb 2011 16:26:44 +0000 (17:26 +0100)]
nvc0: set local memory usage info in shader header
Before this, l[] access was a no-op.
Christoph Bumiller [Sun, 20 Feb 2011 12:13:11 +0000 (13:13 +0100)]
nvc0: don't fold loads from local memory
Christoph Bumiller [Thu, 24 Feb 2011 16:23:23 +0000 (17:23 +0100)]
nvc0: presin and preex2 can load from const space
Christoph Bumiller [Tue, 22 Feb 2011 20:50:17 +0000 (21:50 +0100)]
nvc0: kick out empty live ranges
They affect overlap tests even though they're actually empty.
Christoph Bumiller [Thu, 24 Feb 2011 16:22:15 +0000 (17:22 +0100)]
nvc0: preemptively insert branch at ENDIF
Might be necessary if a block sneaks in somewhere, like a common
block for moves of phi sources after a loop break.
This is harmless and normally will be removed before emission.
Christoph Bumiller [Thu, 24 Feb 2011 16:08:23 +0000 (17:08 +0100)]
nvc0: correct allocation of constrained registers
In linear scan we can't allocate multiple values with different
live ranges at the same time to assign them consecutive regs.
Maybe we should just switch to graph coloring for all values ...
Christoph Bumiller [Thu, 24 Feb 2011 16:04:49 +0000 (17:04 +0100)]
nvc0: sync textures with render targets ourselves
Fixes for example piglit/fbo-flushing and nexuiz' bloom effect.
Christoph Bumiller [Sun, 20 Feb 2011 16:57:47 +0000 (17:57 +0100)]
nvc0: improve userspace fencing
Before, there were situations in which we never checked the fences
for completion (some loading screens for example) and thus never
released memory.
Christoph Bumiller [Sun, 20 Feb 2011 14:10:02 +0000 (15:10 +0100)]
nvc0: values for undefined outputs must have file GPR
Christoph Bumiller [Sat, 19 Feb 2011 19:26:49 +0000 (20:26 +0100)]
nvc0: multiply polygon offset units by 2
Wasn't sure if this still was necessary because the piglit test
started to fail at some point on nv50 where we already do this.
Christoph Bumiller [Sat, 19 Feb 2011 19:26:29 +0000 (20:26 +0100)]
nvc0: fix SSG
Christoph Bumiller [Sat, 19 Feb 2011 13:18:28 +0000 (14:18 +0100)]
nvc0: don't visit target blocks of a loop break multiple times
Christoph Bumiller [Sat, 19 Feb 2011 13:14:40 +0000 (14:14 +0100)]
nvc0: don't overwrite phi sources at the end of a loop
Except the reference to its own result.
Fabian Bieler [Thu, 24 Feb 2011 09:56:16 +0000 (10:56 +0100)]
gallium/utils: Fix vertex element setup
Check if element was translated per element instead of per buffer.
José Fonseca [Wed, 23 Feb 2011 13:32:37 +0000 (13:32 +0000)]
svga: Ensure rendertargets and textures are always rebound at every command buffer start.
The svga_update_state() mechanism is inadequate as it will always end up
flushing the primitives before processing the SVGA_NEW_COMMAND_BUFFER
dirty state flag.
Chris Wilson [Thu, 24 Feb 2011 12:59:52 +0000 (12:59 +0000)]
i965: Remember to pack the constant blend color as floats into the batch
Fixes regression from
aac120977d1ead319141d48d65c9bba626ec03b8.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34597
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Chris Wilson [Thu, 24 Feb 2011 12:29:51 +0000 (12:29 +0000)]
intel: Reset the buffer offset after releasing reference to packed upload
Fixes oglc/vbo(basic.bufferdata)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34603
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Chris Wilson [Thu, 24 Feb 2011 10:58:22 +0000 (10:58 +0000)]
i965: Unmap the correct pointer after discontiguous upload
Fixes piglit/fbo-depth-sample-compare:
==14722== Invalid free() / delete / delete[]
==14722== at 0x4C240FD: free (vg_replace_malloc.c:366)
==14722== by 0x84FBBFD: intel_upload_unmap (intel_buffer_objects.c:695)
==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457)
==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394)
==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365)
==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389)
==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543)
==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973)
==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351)
==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== Address 0xc606310 is 0 bytes after a block of size 18,720 alloc'd
==14722== at 0x4C244E8: malloc (vg_replace_malloc.c:236)
==14722== by 0x85202AB: copy_array_to_vbo_array (brw_draw_upload.c:256)
==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457)
==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394)
==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365)
==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389)
==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543)
==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973)
==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351)
==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34604
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Chris Wilson [Thu, 24 Feb 2011 10:12:37 +0000 (10:12 +0000)]
intel: Protect against waiting on a NULL render target bo
If we fall back to software rendering due to the render target being
absent (GPU hang or other error in creating the named target), then we
do not need to nor should we wait upon the results.
Reported-by: Magnus Kessler <Magnus.Kessler@gmx.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34656
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Dave Airlie [Thu, 17 Feb 2011 05:07:57 +0000 (15:07 +1000)]
r600g: EXT_texture_array support.
This adds EXT_texture_array support to r600g, it passes the piglit
array-texture test but I suspect may not be complete.
It currently requires a kernel patch to fix the CS checker to allow
these, so you need to use R600_ARRAY_TEXTURE=true for now
to enable them.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 18 Feb 2011 04:51:58 +0000 (14:51 +1000)]
st/mesa: treat 1D ARRAY upload like a depth or 2D array upload.
This is because the HW doesn't always store a 1D array like a
2D texture, it more likely stores it like 2D texture (i.e.
alignments etc).
This means we upload each slice separately and let the driver
work out where to put it.
this might break nvc0 as I can't test it, I have only nv50 here.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Vinson Lee [Thu, 24 Feb 2011 02:21:14 +0000 (18:21 -0800)]
scons: Fix Cygwin platform names.
Fixes immediate Python exceptions with SCons on Cygwin.
Jakob Bornecrantz [Tue, 22 Feb 2011 23:12:08 +0000 (23:12 +0000)]
i915g: Lazy emit dynamic state
Jakob Bornecrantz [Mon, 21 Feb 2011 23:39:10 +0000 (23:39 +0000)]
i915g: Lazy emit immediate state
Jakob Bornecrantz [Tue, 22 Feb 2011 22:07:03 +0000 (22:07 +0000)]
i915g: Disable LIS7 state updates for now
Jakob Bornecrantz [Mon, 21 Feb 2011 23:09:43 +0000 (23:09 +0000)]
i915g: Clean up in i915_state_immediate
Jakob Bornecrantz [Mon, 21 Feb 2011 22:47:40 +0000 (22:47 +0000)]
i915g: Remove outdated comment
Jakob Bornecrantz [Tue, 22 Feb 2011 00:20:39 +0000 (00:20 +0000)]
i915g: Use dump function in sw winsys
Jakob Bornecrantz [Wed, 23 Feb 2011 00:11:09 +0000 (00:11 +0000)]
i915g: Enable mirror repeat wrap mode
Jakob Bornecrantz [Tue, 22 Feb 2011 22:28:06 +0000 (22:28 +0000)]
i915g: Always set vbo to flush on flushes
Reported-by Chris Wilson <chris@chris-wilson.co.uk>
Chris Wilson [Wed, 23 Feb 2011 23:09:36 +0000 (23:09 +0000)]
intel: gen3 is particular sensitive to batch size
... and prefers a small batch whereas gen4+ prefer a large batch to
carry more state.
Tuning using openarena/padman indicate that a batch size of just 4096 is
best for those cases.
Bugzilla: https://bugs.freedesktop.org/process_bug.cgi
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Chris Wilson [Wed, 23 Feb 2011 22:09:12 +0000 (22:09 +0000)]
i915: And remember assign the new value to the state reg...
Fixes regression from
298ebb78de8a6b6edf0aa0fe8d784d00bbc2930e.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34589
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tom Fogal [Tue, 22 Feb 2011 05:32:18 +0000 (22:32 -0700)]
Fix GLX_USE_TLS define.
It was only getting set in the case of DRI drivers.
Fabian Bieler [Mon, 14 Feb 2011 21:44:42 +0000 (22:44 +0100)]
r600g: Request DWORD aligned vertex buffers.
The spec says that the offsets in the vertex-fetch instructions need to be byte-aligned and makes no specification with regard to the required alignment of the offset and stride in the vertex resource constant register.
However, testing indicates that all three values need to be DWORD aligned.
Wiktor Janas [Wed, 23 Feb 2011 06:10:12 +0000 (07:10 +0100)]
st/mesa: fix computing the lowest address for interleaved attribs
Ptr can be very well NULL, so when there are two arrays, with one having
offset 0 (and thus NULL Ptr), and the other having a non-zero offset,
the non-zero value is taken as minimum (because of !low_addr ? start ...).
On 32-bit systems, this somehow works. On 64-bit systems, it leads to crashes.
Signed-off-by: Marek Olšák <maraeo@gmail.com>
Brian Paul [Tue, 22 Feb 2011 21:31:15 +0000 (14:31 -0700)]
vbo: added vbo_check_buffers_are_unmapped() debug function
Brian Paul [Tue, 22 Feb 2011 21:23:50 +0000 (14:23 -0700)]
vbo: removed unused #defines, add comments
Brian Paul [Tue, 22 Feb 2011 20:37:30 +0000 (13:37 -0700)]
mesa: move comment, change debug code
Brian Paul [Tue, 22 Feb 2011 20:31:09 +0000 (13:31 -0700)]
vbo: simplify NeedFlush flag clearing
Brian Paul [Tue, 22 Feb 2011 20:24:56 +0000 (13:24 -0700)]
vbo: use ctx intstead of exec->ctx
Brian Paul [Tue, 22 Feb 2011 19:44:42 +0000 (12:44 -0700)]
r300g: fix missing initializers warning
Brian Paul [Tue, 22 Feb 2011 19:44:10 +0000 (12:44 -0700)]
i915g: remove extra semicolons
Andy Skinner [Fri, 11 Feb 2011 15:31:25 +0000 (07:31 -0800)]
xlib: pass Display pointer to XMesaGarbageCollect()
Fixes an issue when different displays are used on different threads.
Signed-off-by: Brian Paul <brianp@vmware.com>
Kenneth Graunke [Sun, 20 Feb 2011 01:22:47 +0000 (17:22 -0800)]
i965: Increase Sandybridge point size clamp.
255.875 matches the hardware documentation. Presumably this was a typo.
Found by inspection. Not known to fix any issues.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Sun, 20 Feb 2011 00:48:24 +0000 (16:48 -0800)]
i965/fs: Correctly set up gl_FragCoord.w on Sandybridge.
pixel_w is the final result; wpos_w is used on gen4 to compute it.
NOTE: This is a candidate for the 7.10 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Sun, 20 Feb 2011 00:12:28 +0000 (16:12 -0800)]
i965/fs: Refactor control flow stack handling.
We can't safely use fixed size arrays since Gen6+ supports unlimited
nesting of control flow.
NOTE: This is a candidate for the 7.10 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Sat, 19 Feb 2011 09:05:11 +0000 (01:05 -0800)]
i965/fs: Avoid register coalescing away gen6 MATH workarounds.
The code that generates MATH instructions attempts to work around
the hardware ignoring source modifiers (abs and negate) by emitting
moves into temporaries. Unfortunately, this pass coalesced those
registers, restoring the original problem. Avoid doing that.
Fixes several OpenGL ES2 conformance failures on Sandybridge.
NOTE: This is a candidate for the 7.10 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Sat, 19 Feb 2011 09:03:08 +0000 (01:03 -0800)]
i965/fs: Apply source modifier workarounds to POW as well.
Single-operand math already had these workarounds, but POW (the only two
operand function) did not. It needs them too - otherwise we can hit
assertion failures in brw_eu_emit.c when code is actually generated.
NOTE: This is a candidate for the 7.10 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Tue, 22 Feb 2011 18:04:18 +0000 (10:04 -0800)]
i965: Fix shaders that write to gl_PointSize on Sandybridge.
gl_PointSize (VERT_RESULT_PSIZ) doesn't take up a message register,
as it's part of the header. Without this fix, writing to gl_PointSize
would cause the SF to read and use the wrong attributes, leading to all
kinds of random looking failure.
Reviewed-by: Eric Anholt <eric@anholt.net>
José Fonseca [Tue, 22 Feb 2011 14:59:09 +0000 (14:59 +0000)]
mesa: Avoid undeclared ffs function warning on mingw.
José Fonseca [Tue, 22 Feb 2011 14:14:45 +0000 (14:14 +0000)]
gallium: s/PIPE_TRANSFER_CPU_READ/PIPE_TRANSFER_READ/ in comments.
José Fonseca [Tue, 22 Feb 2011 14:14:22 +0000 (14:14 +0000)]
gallium/docs: Update PIPE_TRANSFER_xx docs. Reformat to use definitions.
Keith Whitwell [Wed, 5 Jan 2011 17:33:43 +0000 (17:33 +0000)]
gallium: new transfer flag: DISCARD_WHOLE_RESOURCE
Marek Olšák [Sun, 20 Feb 2011 17:05:24 +0000 (18:05 +0100)]
st/mesa: fix crash when using both user and vbo buffers with the same stride
If two buffers had the same stride where one buffer is a user one and
the other is a vbo, it was considered to be one interleaved buffer,
resulting in incorrect rendering and crashes.
This patch makes sure that the interleaved buffer is either user or vbo,
not both.
Marek Olšák [Sun, 20 Feb 2011 15:50:48 +0000 (16:50 +0100)]
st/mesa: fix crash when DrawBuffer->_ColorDrawBuffers[0] is NULL
This fixes the game Tiny and Big.
Chris Wilson [Tue, 22 Feb 2011 11:17:39 +0000 (11:17 +0000)]
i965: Trim the interleaved upload to the minimum number of vertices
... should have no impact on a properly formatted draw operation.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Chris Wilson [Tue, 22 Feb 2011 11:19:32 +0000 (11:19 +0000)]
i965: Reinstate max-index paranoia
Don't trust the applications not to reference beyond the end of the
vertex buffers.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Chris Wilson [Tue, 22 Feb 2011 11:18:25 +0000 (11:18 +0000)]
i965: Zero the offset into the vbo when uploading non-interleaved
Fixes regression from
559435d9152acc7162e4e60aae6591c7c6c8274b.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Jakob Bornecrantz [Wed, 1 Dec 2010 04:04:25 +0000 (05:04 +0100)]
st/dri: Track drawable context bindings
Needs to track this ourself since because we get into a race condition with
the dri_util.c code on make current when rendering to the front buffer.
This is what happens:
Old context is rendering to the front buffer.
App calls MakeCurrent with a new context. dri_util.c sets
drawable->driContextPriv to the new context and then calls the driver make
current. st/dri make current flushes the old context, which calls back into
st/dri via the flush frontbuffer hook. st/dri calls dri loader flush
frontbuffer, which calls invalidate buffer on the drawable into st/dri.
This is where things gets wrong. st/dri grabs the context from the dri
drawable (which now points to the new context) and calls invalidate
framebuffer to the new context which has not yet set the new drawable as its
framebuffers since we have not called make current yet, it asserts.
Eric Anholt [Tue, 22 Feb 2011 00:24:41 +0000 (16:24 -0800)]
i965: Fix VB packet reuse when offset for the new buffer isn't stride aligned.
Fixes regression in scissor-stencil-clear and 5 other tests.
Brian Paul [Tue, 22 Feb 2011 00:01:00 +0000 (17:01 -0700)]
Revert "mesa: convert macros to inline functions"
This reverts commit
e9ff76aa81d9bd973d46b7e46f1e4ece2112a5b7.
Need to use macros so __FUNCTION__ reports the caller.
Brian Paul [Mon, 21 Feb 2011 23:54:23 +0000 (16:54 -0700)]
st/mesa: need to translate clear color according to surface's base format
When clearing a GL_LUMINANCE_ALPHA buffer, for example, we need to convert
the clear color (R,G,B,A) to (R,R,R,A). We were doing this for texture border
colors but not renderbuffers. Move the translation function to st_format.c
and share it.
This fixes the piglit fbo-clear-formats test.
NOTE: This is a candidate for the 7.9 and 7.10 branches.
Brian Paul [Mon, 21 Feb 2011 23:46:02 +0000 (16:46 -0700)]
st/mesa: fix the default case in st_format_datatype()
Part of the fix for piglit fbo-clear-formats
NOTE: This is a candidate for the 7.9 and 7.10 branches.
Daniel Vetter [Mon, 21 Feb 2011 18:14:02 +0000 (19:14 +0100)]
i915g: add some throttling
Intel classic drivers switched to this, too, so it must be good.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Daniel Vetter [Mon, 21 Feb 2011 17:25:20 +0000 (18:25 +0100)]
i915g: s/bool/boolean/ style-fixup in winsys
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jakob Bornecrantz [Mon, 21 Feb 2011 22:00:02 +0000 (22:00 +0000)]
i915g: Fix warning
Jakob Bornecrantz [Sun, 20 Feb 2011 12:41:18 +0000 (13:41 +0100)]
i915g: Add option to lie about caps
Jakob Bornecrantz [Sun, 20 Feb 2011 11:52:55 +0000 (12:52 +0100)]
i915g: Move debug fields to screen
Jakob Bornecrantz [Sun, 20 Feb 2011 10:41:32 +0000 (11:41 +0100)]
i915g: Use debug get once options
Jakob Bornecrantz [Sun, 20 Feb 2011 11:52:11 +0000 (12:52 +0100)]
i915g: Rework texture tiling a bit
Jakob Bornecrantz [Mon, 21 Feb 2011 21:27:05 +0000 (21:27 +0000)]
i915g: Anisotropic filtering works
Jakob Bornecrantz [Sun, 20 Feb 2011 13:00:03 +0000 (14:00 +0100)]
i915g: TODO about point sprites
Jakob Bornecrantz [Sun, 20 Feb 2011 12:58:11 +0000 (13:58 +0100)]
i915g: TODO about untested code hidden behind caps
Should be fairly easy to test and fix since you can look at
the code in the classic driver.
Jakob Bornecrantz [Sun, 20 Feb 2011 10:45:48 +0000 (11:45 +0100)]
i915g: Reorg caps
Brian Paul [Mon, 21 Feb 2011 22:11:44 +0000 (15:11 -0700)]
st/mesa: fix incorrect texture size allocation in st_finalize_texture()
If finalizing a non-POW mipmapped texture with an odd-sized base texture
image we were allocating the wrong size of gallium texture (off by one).
Need to be more careful about computing the base texture image size.
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=34463
Brian Paul [Mon, 21 Feb 2011 22:11:44 +0000 (15:11 -0700)]
st/mesa: refactor guess_and_alloc_texture() code
Brian Paul [Mon, 21 Feb 2011 22:11:44 +0000 (15:11 -0700)]
st/mesa: fix mipmap generation for non-POW textures
This is part of the fix for https://bugs.freedesktop.org/show_bug.cgi?id=34463
Brian Paul [Mon, 21 Feb 2011 22:11:44 +0000 (15:11 -0700)]
mesa: convert macros to inline functions
Brian Paul [Mon, 21 Feb 2011 22:11:44 +0000 (15:11 -0700)]
vbo: more comments
Brian Paul [Mon, 21 Feb 2011 22:11:44 +0000 (15:11 -0700)]
vbo: make vbo_exec_FlushVertices_internal() static
Brian Paul [Mon, 21 Feb 2011 22:11:44 +0000 (15:11 -0700)]
vbo: remove old debug code, add comments