OSDN Git Service
Craig Topper [Mon, 15 Oct 2018 01:51:58 +0000 (01:51 +0000)]
[X86] Move promotion of vector and/or/xor from legalization to DAG combine
Summary:
I've noticed that the bitcasts we introduce for these make computeKnownBits and computeNumSignBits not work well in LegalizeVectorOps. LegalizeVectorOps legalizes bottom up while LegalizeDAG legalizes top down. The bottom up strategy for LegalizeVectorOps means operands are legalized before their uses. So we promote and/or/xor before we legalize the operands that use them making computeKnownBits/computeNumSignBits in places like LowerTruncate suboptimal. I looked at changing LegalizeVectorOps to be top down as well, but that was more disruptive and caused some regressions. I also looked at just moving promotion of binops to LegalizeDAG, but that had a few issues one around matching AND,ANDN,OR into VSELECT because I had to create ANDN as vXi64, but the other nodes hadn't legalized yet, I didn't look too hard at fixing that.
This patch seems to produce better results overall than my other attempts. We now form broadcasts of constants better in some cases. For at least some of them the AND was being introduced in LegalizeDAG, promoted to vXi64, and the BUILD_VECTOR was also legalized there. I think we got bad ordering of that. Now the promotion is out of the legalizer so we handle this better.
In the longer term I think we really should evaluate whether we should be doing this promotion at all. It's really there to reduce isel pattern count, but I'm wondering if we'd be better served just eating the pattern cost or doing C++ based isel for vector and/or/xor in X86ISelDAGToDAG. The masked and/or/xor will definitely be difficult in patterns if a bitcast gets between the vselect and the and/or/xor node. That becomes a lot of permutations to cover.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344487
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 15 Oct 2018 01:51:53 +0000 (01:51 +0000)]
[X86] Add 128 MOVDDUP to the constant pool printing in X86AsmPrinter::EmitInstruction.
We use this instruction to broadcast a single 64-bit value to a v2i64/v2f64 vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344486
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 15 Oct 2018 01:51:50 +0000 (01:51 +0000)]
[X86] Autogenerate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344485
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 14 Oct 2018 20:14:33 +0000 (20:14 +0000)]
[InstCombine] Add PR27343 test cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344484
91177308-0d34-0410-b5e6-
96231b3b80d8
Ayal Zaks [Sun, 14 Oct 2018 17:53:02 +0000 (17:53 +0000)]
[LV] Fix comments reported when not vectorizing single iteration loops; NFC
Landing this as a separate part of https://reviews.llvm.org/D50480, being a
seemingly unrelated change ([LV] Vectorizing loops of arbitrary trip count
without remainder under opt for size).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344483
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 14 Oct 2018 17:34:20 +0000 (17:34 +0000)]
[X86][AVX] Enable lowerVectorShuffleAsLanePermuteAndPermute v16i16/v32i8 shuffle lowering
Extends D53148 from v4f64 now that we have test coverage for v16i16/v32i8 shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344481
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 14 Oct 2018 16:49:04 +0000 (16:49 +0000)]
[ARM] Regenerate cttz tests
Improve codegen view as part of PR32655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344479
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Sun, 14 Oct 2018 16:09:59 +0000 (16:09 +0000)]
[ORC] Remove XXLayer::add methods that default to using the main JITDylib.
They're not currently used and may complicate upcoming changes to add's
signature and behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344478
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sun, 14 Oct 2018 15:56:28 +0000 (15:56 +0000)]
[LegalizeDAG] Don't bother with final MUL+SRL stage for byte CTPOP.
The final stage of CTPOP expansion (v = (v * 0x01010101...) >> (Len - 8)) is completely pointless for the byte (Len = 8) case as it reduces to (v = (v * 0x01...) >> 0), but annoyingly this doesn't always get optimized away.
Found while investigating generic vector CTPOP expansion (PR32655).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344477
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sun, 14 Oct 2018 15:25:06 +0000 (15:25 +0000)]
[InstCombine] combine a shuffle and an extract subvector shuffle
This is part of the missing IR-level folding noted in D52912.
This should be ok as a canonicalization because the new shuffle mask can't
be any more complicated than the existing shuffle mask. If there's some
target where the shorter vector shuffle is not legal, it should just end up
expanding to something like the pair of shuffles that we're starting with here.
Differential Revision: https://reviews.llvm.org/D53037
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344476
91177308-0d34-0410-b5e6-
96231b3b80d8
Dorit Nuzman [Sun, 14 Oct 2018 08:50:06 +0000 (08:50 +0000)]
recommit 344472 after fixing build failure on ARM and PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344475
91177308-0d34-0410-b5e6-
96231b3b80d8
Dorit Nuzman [Sun, 14 Oct 2018 07:21:20 +0000 (07:21 +0000)]
revert 344472 due to failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344473
91177308-0d34-0410-b5e6-
96231b3b80d8
Dorit Nuzman [Sun, 14 Oct 2018 07:06:16 +0000 (07:06 +0000)]
[IAI,LV] Add support for vectorizing predicated strided accesses using masked
interleave-group
The vectorizer currently does not attempt to create interleave-groups that
contain predicated loads/stores; predicated strided accesses can currently be
vectorized only using masked gather/scatter or scalarization. This patch makes
predicated loads/stores candidates for forming interleave-groups during the
Loop-Vectorizer's analysis, and adds the proper support for masked-interleave-
groups to the Loop-Vectorizer's planning and transformation stages. The patch
also extends the TTI API to allow querying the cost of masked interleave groups
(which each target can control); Targets that support masked vector loads/
stores may choose to enable this feature and allow vectorizing predicated
strided loads/stores using masked wide loads/stores and shuffles.
Reviewers: Ayal, hsaito, dcaballe, fhahn, javed.absar
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D53011
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344472
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 14 Oct 2018 04:01:40 +0000 (04:01 +0000)]
[X86] Fix bad indentation. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344471
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 14 Oct 2018 03:36:27 +0000 (03:36 +0000)]
[X86] Type legalize v2f32 stores by widening to v4f32, casting to v2f64, extracting f64 and storing.
Summary: This is similar to what D52528 did for loads. It should match what generic type legalization does in 64-bit mode where it uses a v2i64 cast and an i64 store.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344470
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Sat, 13 Oct 2018 22:18:22 +0000 (22:18 +0000)]
Move some helpers from the global namespace into anonymous ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344468
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Sat, 13 Oct 2018 21:53:40 +0000 (21:53 +0000)]
[ORC] During lookup, do not match against hidden symbols in other JITDylibs.
This adds two arguments to the main ExecutionSession::lookup method:
MatchNonExportedInJD, and MatchNonExported. These control whether and where
hidden symbols should be matched when searching a list of JITDylibs.
A similar effect could have been achieved by filtering search results, but
this would have involved materializing symbol definitions (since materialization
is triggered on lookup) only to throw the results away, among other issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344467
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 13 Oct 2018 21:50:15 +0000 (21:50 +0000)]
[AARCH64] Regenerate popcnt tests
Improve codegen view as part of PR32655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344466
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 13 Oct 2018 21:32:49 +0000 (21:32 +0000)]
[ARM] Regenerate popcnt tests
Improve codegen view as part of PR32655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344465
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 13 Oct 2018 18:40:48 +0000 (18:40 +0000)]
Pull out repeated variables from SelectionDAGLegalize::ExpandBitCount.
The CTPOP case has been changed from VT.getSizeInBits to VT.getScalarSizeInBits - but this fits in with future work for vector support (PR32655) and doesn't affect any current (scalar) uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344461
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 13 Oct 2018 17:47:20 +0000 (17:47 +0000)]
[LegalizeTypes] Prevent an assertion from PromoteIntRes_BSWAP and PromoteIntRes_BITREVERSE if the shift amount is too large for the VT returned by getShiftAmountTy
Summary:
getShiftAmountTy for X86 returns MVT::i8. If a BSWAP or BITREVERSE is created that requires promotion and the difference between the original VT and the promoted VT is more than 255 then we won't able to create the constant.
This patch adds a check to replace the result from getShiftAmountTy to MVT::i32 if the difference won't fit. This should get legalized later when the shift is ultimately expanded since its clearly an illegal type that we're only promoting to make it a power of 2 bit width. Alternatively we could base the decision completely on the largest shift amount the promoted VT could use.
Vectors should be immune here because getShiftAmountTy always returns the incoming VT for vectors. Only the scalar shift amount can be changed by the targets.
Reviewers: eli.friedman, RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53232
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344460
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Sat, 13 Oct 2018 16:58:03 +0000 (16:58 +0000)]
[WebAssembly][NFC] Fix signed/unsigned comparison warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344459
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 13 Oct 2018 16:15:37 +0000 (16:15 +0000)]
[InstCombine] fix complexity canonicalization with fake unary vector ops
This is a preliminary step to avoid regressions when we add
an actual 'fneg' instruction to IR. See D52934 and D53205.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344458
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 13 Oct 2018 16:11:15 +0000 (16:11 +0000)]
[X86][SSE] Remove most of vector CTTZ custom lowering and use LegalizeDAG instead.
There is one remnant - AVX1 custom splitting of 256-bit vectors - which is due to a regression where the X86ISD::ANDNP is still performed as a YMM.
I've also tightened the CTLZ or CTPOP lowering in SelectionDAGLegalize::ExpandBitCount to require a legal CTLZ - it doesn't affect existing users and fixes an issue with AVX512 codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344457
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 13 Oct 2018 16:02:47 +0000 (16:02 +0000)]
[InstCombine] add tests for operand complexity canonicalization; NFC
The tests with undef vector elements demonstrate a hole in
the current pattern matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344456
91177308-0d34-0410-b5e6-
96231b3b80d8
David Bolvansky [Sat, 13 Oct 2018 15:26:13 +0000 (15:26 +0000)]
[NFC] Fixed duplicated test file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344455
91177308-0d34-0410-b5e6-
96231b3b80d8
David Bolvansky [Sat, 13 Oct 2018 15:21:55 +0000 (15:21 +0000)]
[InstCombine] Fixed crash with aliased functions
Summary: Fixes PR39177
Reviewers: spatel, jbuening
Reviewed By: jbuening
Subscribers: jbuening, llvm-commits
Differential Revision: https://reviews.llvm.org/D53129
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344454
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 13 Oct 2018 15:16:55 +0000 (15:16 +0000)]
[X86][SSE] Begin removing vector CTTZ custom lowering and use LegalizeDAG instead.
Adds CTTZ vector legalization support and begins the removal of the X86/SSE custom lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344453
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 13 Oct 2018 14:45:44 +0000 (14:45 +0000)]
[X86][SSE] combineIncDecVector - use isConstantSplat
Use isConstantSplat instead of ISD::isConstantSplatVector to let us us peek through to illegal types (in this case for i686 targets to recognise i64 constants)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344452
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 13 Oct 2018 14:28:40 +0000 (14:28 +0000)]
[X86] Pull out target constant splat helper function. NFCI.
The code in LowerScalarImmediateShift is just a more powerful version of ISD::isConstantSplatVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344451
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 13 Oct 2018 13:33:32 +0000 (13:33 +0000)]
Pull out repeated getOperand(). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344450
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 13 Oct 2018 13:30:10 +0000 (13:30 +0000)]
Remove unused variable. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344449
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 13 Oct 2018 13:05:19 +0000 (13:05 +0000)]
[X86][SSE] Improve CTTZ lowering when CTLZ is legal
If we have better CTLZ support than CTPOP, then use cttz(x) = width - ctlz(~x & (x - 1)) - and remove the CTTZ_ZERO_UNDEF handling as it no longer gives better codegen.
Similar to rL344447, this is also closer to LegalizeDAG's approach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344448
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 13 Oct 2018 12:12:06 +0000 (12:12 +0000)]
[X86][SSE] Change CTTZ vector lowering to cttz(x) = ctpop(~x & (x - 1))
This patch changes the vector CTTZ lowering from:
cttz(x) = ctpop((x & -x) - 1)
to:
cttz(x) = ctpop(~x & (x - 1))
Not only does this make better use of the PANDN instruction, but it also matches the LegalizeDAG method which should allow us to remove the x86 specific code at some point in the future (we need to fix some issues with the bitcasted logic ops and CTPOP lowering first).
Differential Revision: https://reviews.llvm.org/D53214
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344447
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Sat, 13 Oct 2018 11:38:10 +0000 (11:38 +0000)]
[X86][AVX] Add lowerVectorShuffleAsLanePermuteAndPermute for v4f64 shuffles (PR39161)
Add shuffle lowering for the case where we can shuffle the lanes into place followed by an in-lane permute.
This is mainly for cases where we can have non-repeating permutes in each lane, but for now I've just enabled it for v4f64 unary shuffles to fix PR39161 - there is no test coverage for other shuffles that might benefit yet.
We now have several cross-lane shuffle lowering methods that all do something similar - I've looked at merging some of these (notably by making the repeated mask mechanism in lowerVectorShuffleByMerging128BitLanes optional), but there is a lot of assertions/assumptions in the way that makes this tricky - I ended up going for adding yet another relatively simple method instead.
Differential Revision: https://reviews.llvm.org/D53148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344446
91177308-0d34-0410-b5e6-
96231b3b80d8
Arnaud A. de Grandmaison [Sat, 13 Oct 2018 07:43:56 +0000 (07:43 +0000)]
[AArch64] Swap comparison operands if that enables some folding.
Summary:
AArch64 can fold some shift+extend operations on the RHS operand of
comparisons, so swap the operands if that makes sense.
This provides a fix for https://bugs.llvm.org/show_bug.cgi?id=38751
Reviewers: efriedma, t.p.northover, javed.absar
Subscribers: mcrosier, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D53067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344439
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Sat, 13 Oct 2018 07:26:10 +0000 (07:26 +0000)]
[WebAssembly] SIMD min and max
Summary: Depends on D52324 and D52764.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52325
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344438
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Sat, 13 Oct 2018 07:21:44 +0000 (07:21 +0000)]
[Intrinsic] Add llvm.minimum and llvm.maximum instrinsic functions
Summary:
These new intrinsics have the semantics of the `minimum` and `maximum`
operations specified by the latest draft of IEEE 754-2018. Unlike
llvm.minnum and llvm.maxnum, these new intrinsics propagate NaNs and
always treat -0.0 as less than 0.0. `minimum` and `maximum` lower
directly to the existing `fminnan` and `fmaxnan` ISel DAG nodes. It is
safe to reuse these DAG nodes because before this patch were only
emitted in situations where there were known to be no NaN arguments or
where NaN propagation was correct and there were known to be no zero
arguments. I know of only four backends that lower fminnan and
fmaxnan: WebAssembly, ARM, AArch64, and SystemZ, and each of these
lowers fminnan and fmaxnan to instructions that are compatible with
the IEEE 754-2018 semantics.
Reviewers: aheejin, dschuff, sunfish, javed.absar
Subscribers: kristof.beyls, dexonsmith, kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D52764
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344437
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Sat, 13 Oct 2018 07:09:10 +0000 (07:09 +0000)]
[WebAssembly][NFC] Unify ARGUMENT classes
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344436
91177308-0d34-0410-b5e6-
96231b3b80d8
Kostya Serebryany [Fri, 12 Oct 2018 23:21:48 +0000 (23:21 +0000)]
move GetOrCreateFunctionComdat to Instrumentation.cpp/Instrumentation.h
Summary:
GetOrCreateFunctionComdat is currently used in SanitizerCoverage,
where it's defined. I'm planing to use it in HWASAN as well,
so moving it into a common location.
NFC
Reviewers: morehouse
Reviewed By: morehouse
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53218
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344433
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Fri, 12 Oct 2018 23:18:52 +0000 (23:18 +0000)]
[RISCV] Eliminate unnecessary masking of promoted shift amounts
SelectionDAGBuilder::visitShift will always zero-extend a shift amount when it
is promoted to the ShiftAmountTy. This results in zero-extension (masking)
which is unnecessary for RISC-V as the shift operations only read the lower 5
or 6 bits (RV32 or RV64).
I initially proposed adding a getExtendForShiftAmount hook so the shift amount
can be any-extended (D52975). @efriedma explained this was unsafe, so I have
instead eliminate the unnecessary and operations at instruction selection time
in a manner similar to X86InstrCompiler.td.
Differential Revision: https://reviews.llvm.org/D53224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344432
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 12 Oct 2018 22:57:57 +0000 (22:57 +0000)]
[llvm-readobj] Fix an error message about .llvm.call-graph-profile
.note.llvm.cgprofile was an obvious typo in rL333823
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344430
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 12 Oct 2018 22:55:17 +0000 (22:55 +0000)]
[LegalizeVectorTypes] Use TLI.getVectorIdxTy instead of DAG.getIntPtrConstant.
There's no guarantee that vector indices should use pointer types. So use the correct query method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344428
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 12 Oct 2018 22:00:04 +0000 (22:00 +0000)]
[X86] Improve type legalization of (v2i32/v4i16/v8i16 (bitcast (v2f32))) to avoid a stack stack temporary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344425
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 12 Oct 2018 22:00:00 +0000 (22:00 +0000)]
[X86] Simplify the end of custom type legalization for (v2i32/v4i16/v8i8 (bitcast (f64))) by just emitting an EXTRACT_SUBVECTOR instead of a BUILD_VECTOR.
Generic legalization should be able to finish legalizing the EXTRACT_SUBVECTOR probably by turning it into a BUILD_VECTOR. But we should emit the simplest sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344424
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 12 Oct 2018 21:59:58 +0000 (21:59 +0000)]
[X86] Skip (v2i32/v4i16/v8i8 (bitcast (f64))) handling in ReplaceNodeResults if the dest type can be widened by generic legalization. NFCI
The algorithm we would do previously was identical to generic legalization. If we ever switch to legalizing integer vectors via widening we'll be able to kill off the code since it now only runs for promotion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344423
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 12 Oct 2018 21:59:55 +0000 (21:59 +0000)]
[LegalizeVectorTypes] When widening the result of a bitcast from a scalar type, use a scalar_to_vector to turn the scalar into a vector intead of a build vector full of mostly undefs.
This is more consistent with what we usually do and matches some code X86 custom emits in some cases that I think I can cleanup.
The MIPS test change just looks to be an instruction ordering change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344422
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Fri, 12 Oct 2018 19:41:05 +0000 (19:41 +0000)]
Revert BTF commit series.
The initial patch was not reviewed, and does not have any tests;
it should not have been merged.
This reverts 344395, 344390, 344387, 344385, 344381, 344376,
and 344366.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344405
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 12 Oct 2018 19:37:49 +0000 (19:37 +0000)]
[LegalizeVectorTypes] When widening the operands to a concat_vectors, see if we can use the widened operand 0 if the width matches and the other operands are undef.
This saves a conversion to extracts and build_vector. We already do this when both the result and the input need to be widened to the same type.
This changed the sse-intrinsics-fast-isel test because we don't lower (insert_vector_elt (scalar_to_vector X), Y, 1) well. We turn it into (vector_shuffle (scalar_to_vector X), (scalar_to_vector Y), <0, 4, 2, 3>) losing track of the fact that the upper elts could be undef.
We should probably find a way to prevent the scalarization of the <2 x f32> load on these tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344404
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 12 Oct 2018 19:37:47 +0000 (19:37 +0000)]
[LegalizeVectorTypes] When unrolling in WidenVecRes_Convert, make sure we use the original vector element count. Not min of the widened result type and the possibly widened input type.
If the input type is widened as well, but we still were forced to unroll, we shouldn't be considering the widened input element count. We should only create as many scalar operations as the original type called for.
This will be important for an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344403
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 12 Oct 2018 19:30:43 +0000 (19:30 +0000)]
Fix Wdocumentation warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344402
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 12 Oct 2018 19:03:54 +0000 (19:03 +0000)]
Regenerate test. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344399
91177308-0d34-0410-b5e6-
96231b3b80d8
Rui Ueyama [Fri, 12 Oct 2018 18:29:30 +0000 (18:29 +0000)]
Replace assert() with llvm_unreachable because it's obviously a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344395
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Fri, 12 Oct 2018 18:19:06 +0000 (18:19 +0000)]
[codeview] Emit S_BUILDINFO and LF_BUILDINFO with cwd and source file
Summary: We can fill in the command line and compiler path later if we want.
Reviewers: zturner
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D53179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344393
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Fri, 12 Oct 2018 18:18:53 +0000 (18:18 +0000)]
[llvm-mca] Correctly set aliases for register writes introduced by optimized register moves.
This fixes a problem introduced by r344334. A write from a non-zero move
eliminated at register renaming stage was not correctly handled by the PRF. This
would have led to an assertion failure if the processor model declares a PRF
that enables non-zero move elimination.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344392
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonathan Metzman [Fri, 12 Oct 2018 18:11:47 +0000 (18:11 +0000)]
[SanitizerCoverage] Prevent /OPT:REF from stripping constructors
Summary:
Linking with the /OPT:REF linker flag when building COFF files causes
the linker to strip SanitizerCoverage's constructors. Prevent this by
giving the constructors WeakODR linkage and by passing the linker a
directive to include sancov.module_ctor.
Include a test in compiler-rt to verify libFuzzer can be linked using
/OPT:REF
Reviewers: morehouse, rnk
Reviewed By: morehouse, rnk
Subscribers: rnk, morehouse, hiraditya
Differential Revision: https://reviews.llvm.org/D52119
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344391
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 12 Oct 2018 18:10:04 +0000 (18:10 +0000)]
Fix MCBTF string array initialization so its MSVC friendly. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344390
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 12 Oct 2018 17:57:07 +0000 (17:57 +0000)]
[BPF] Use cstdint {,u}int*_t instead of linux/types.h __u32 __u16 ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344387
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Liu [Fri, 12 Oct 2018 17:55:21 +0000 (17:55 +0000)]
Disambiguate: s/make_unique/llvm::make_unique/. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344385
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 12 Oct 2018 17:41:12 +0000 (17:41 +0000)]
[BPF] Don't include linux/types.h and fix style
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344381
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Fri, 12 Oct 2018 17:26:19 +0000 (17:26 +0000)]
Better support for POSIX paths in PDBs.
This a resubmission of a patch which was previously reverted
due to breaking several lld tests. The issues causing those
failures have been fixed, so the patch is now resubmitted.
---Original Commit Message---
While it doesn't make a *ton* of sense for POSIX paths to be
in PDBs, it's possible to occur in real scenarios involving
cross compilation.
The tools need to be able to handle this, because certain types
of debugging scenarios are possible without a running process
and so don't necessarily require you to be on a Windows system.
These include post-mortem debugging and binary forensics (e.g.
using a debugger to disassemble functions and examine symbols
without running the process).
There's changes in clang, LLD, and lldb in this patch. After
this the cross-platform disassembly and source-list tests pass
on Linux.
Furthermore, the behavior of LLD can now be summarized by a much
simpler rule than before: Unless you specify /pdbsourcepath and
/pdbaltpath, the PDB ends up with paths that are valid within
the context of the machine that the link is performed on.
Differential Revision: https://reviews.llvm.org/D53149
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344377
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 12 Oct 2018 17:23:25 +0000 (17:23 +0000)]
[BPF] Some fixes after rL344366
* Move #include outside of namespaces
* Add missing #include
* Add out-of-line virtual destructor to BTFTypeEntry
designated initializers should also be fixed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344376
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Desaulniers [Fri, 12 Oct 2018 17:22:07 +0000 (17:22 +0000)]
[Support] exit with custom return code for SIGPIPE
Summary:
We tell the user to file a bug report on LLVM right now, and
SIGPIPE isn't LLVM's fault so our error message is wrong.
Allows frontends to detect SIGPIPE from writing to closed readers.
This can be seen commonly from piping into head, tee, or split.
Fixes PR25349, rdar://problem/
14285346, b/
77310947
Reviewers: jfb
Reviewed By: jfb
Subscribers: majnemer, kristina, llvm-commits, thakis, srhines
Differential Revision: https://reviews.llvm.org/D53000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344372
91177308-0d34-0410-b5e6-
96231b3b80d8
Yonghong Song [Fri, 12 Oct 2018 17:01:46 +0000 (17:01 +0000)]
[BPF] Add BTF generation for BPF target
BTF is the debug format for BPF, a kernel virtual machine
and widely used for tracing, networking and security, etc ([1]).
Currently only instruction streams are passed to kernel,
the kernel verifier verifies them before execution. In order to
provide better visibility of bpf programs to user space
tools, some debug information, e.g., function names and
debug line information are desirable for kernel so tools
can get such information with better annotation
for jited instructions for performance or other reasons.
The dwarf is too complicated in kernel and for BPF.
Hence, BTF is designed to be the debug format for BPF ([2]).
Right now, pahole supports BTF for types, which
are generated based on dwarf sections in the ELF file.
In order to annotate performance metrics for jited bpf insns,
it is necessary to pass debug line info to the kernel.
Furthermore, we want to pass the actual code to the
kernel because of the following reasons:
. bpf program typically is small so storage overhead
should be small.
. in bpf land, it is totally possible that
an application loads the bpf program into the
kernel and then that application quits, so
holding debug info by the user space application
is not practical.
. having source codes directly kept by kernel
would ease deployment since the original source
code does not need ship on every hosts and
kernel-devel package does not need to be
deployed even if kernel headers are used.
The only reliable time to get the source code is
during compilation time. This will result in both more
accurate information and easier deployment as
stated in the above.
Another consideration is for JIT. The project like bcc
use MCJIT to compile a C program into bpf insns and
load them to the kernel ([3]). The generated BTF sections
will be readily available for such cases as well.
This patch implemented generation of BTF info in llvm
compiler. The BTF related sections will be generated
when both -target bpf and -g are specified. Two sections
are generated:
.BTF contains all the type and string information, and
.BTF.ext contains the func_info and line_info.
The separation is related to how two sections are used
differently in bpf loader, e.g., linux libbpf ([4]).
The .BTF section can be loaded into the kernel directly
while .BTF.ext needs loader manipulation before loading
to the kernel. The format of the each section is roughly
defined in llvm:include/llvm/MC/MCBTFContext.h and
from the implementation in llvm:lib/MC/MCBTFContext.cpp.
A later example also shows the contents in each section.
The type and func_info are gathered during CodeGen/AsmPrinter
by traversing dwarf debug_info. The line_info is
gathered in MCObjectStreamer before writing to
the object file. After all the information is gathered,
the two sections are emitted in MCObjectStreamer::finishImpl.
With cmake CMAKE_BUILD_TYPE=Debug, the compiler can
dump out all the tables except insn offset, which
will be resolved later as relocation records.
The debug type "btf" is used for BTFContext dump.
Dwarf tests the debug info generation with
llvm-dwarfdump to decode the binary sections and
check whether the result is expected. Currently
we do not have such a tool yet. We will implement
btf dump functionality in bpftool ([5]) as the bpftool is
considered the recommended tool for bpf introspection.
The implementation for type and func_info is tested
with linux kernel test cases. The line_info is visually
checked with dump from linux kernel libbpf ([4]) and
checked with readelf dumping section raw data.
Note that the .BTF and .BTF.ext information will not
be emitted to assembly code and there is no assembler
support for BTF either.
In the below, with a clang/llvm built with CMAKE_BUILD_TYPE=Debug,
Each table contents are shown for a simple C program.
-bash-4.2$ cat -n test.c
1 struct A {
2 int a;
3 char b;
4 };
5
6 int test(struct A *t) {
7 return t->a;
8 }
-bash-4.2$ clang -O2 -target bpf -g -mllvm -debug-only=btf -c test.c
Type Table:
[1] FUNC name_off=1 info=0x0c000001 size/type=2
param_type=3
[2] INT name_off=12 info=0x01000000 size/type=4
desc=0x01000020
[3] PTR name_off=0 info=0x02000000 size/type=4
[4] STRUCT name_off=16 info=0x04000002 size/type=8
name_off=18 type=2 bit_offset=0
name_off=20 type=5 bit_offset=32
[5] INT name_off=22 info=0x01000000 size/type=1
desc=0x02000008
String Table:
0 :
1 : test
6 : .text
12 : int
16 : A
18 : a
20 : b
22 : char
27 : test.c
34 : int test(struct A *t) {
58 : return t->a;
FuncInfo Table:
sec_name_off=6
insn_offset=<Omitted> type_id=1
LineInfo Table:
sec_name_off=6
insn_offset=<Omitted> file_name_off=27 line_off=34 line_num=6 column_num=0
insn_offset=<Omitted> file_name_off=27 line_off=58 line_num=7 column_num=3
-bash-4.2$ readelf -S test.o
......
[12] .BTF PROGBITS
0000000000000000 0000028d
00000000000000c1 0000000000000000 0 0 1
[13] .BTF.ext PROGBITS
0000000000000000 0000034e
0000000000000050 0000000000000000 0 0 1
[14] .rel.BTF.ext REL
0000000000000000 00000648
0000000000000030 0000000000000010 16 13 8
......
-bash-4.2$
The latest linux kernel ([6]) can already support .BTF with type information.
The [7] has the reference implementation in linux kernel side
to support .BTF.ext func_info. The .BTF.ext line_info support is not
implemented yet. If you have difficulty accessing [6], you can
manually do the following to access the code:
git clone https://github.com/yonghong-song/bpf-next-linux.git
cd bpf-next-linux
git checkout btf
The change will push to linux kernel soon once this patch is landed.
References:
[1]. https://www.kernel.org/doc/Documentation/networking/filter.txt
[2]. https://lwn.net/Articles/750695/
[3]. https://github.com/iovisor/bcc
[4]. https://github.com/torvalds/linux/tree/master/tools/lib/bpf
[5]. https://github.com/torvalds/linux/tree/master/tools/bpf/bpftool
[6]. https://github.com/torvalds/linux
[7]. https://github.com/yonghong-song/bpf-next-linux/tree/btf
Signed-off-by: Song Liu <songliubraving@fb.com>
Signed-off-by: Yonghong Song <yhs@fb.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
Differential Revision: https://reviews.llvm.org/D52950
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344366
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 12 Oct 2018 16:41:02 +0000 (16:41 +0000)]
[x86] add and use fast horizontal vector math subtarget feature
This is the planned follow-up to D52997. Here we are reducing horizontal vector math codegen
by default. AMD Jaguar (btver2) should have no difference with this patch because it has
fast-hops. (If we want to set that bit for other CPUs, let me know.)
The code changes are small, but there are many test diffs. For files that are specifically
testing for hops, I added RUNs to distinguish fast/slow, so we can see the consequences
side-by-side. For files that are primarily concerned with codegen other than hops, I just
updated the CHECK lines to reflect the new default codegen.
To recap the recent horizontal op story:
1. Before rL343727, we were producing hops for all subtargets for a variety of patterns.
Hops were likely not optimal for all targets though.
2. The IR improvement in r343727 exposed a hole in the backend hop pattern matching, so
we reduced hop codegen for all subtargets. That was bad for Jaguar (PR39195).
3. We restored the hop codegen for all targets with rL344141. Good for Jaguar, but
probably bad for other CPUs.
4. This patch allows us to distinguish when we want to produce hops, so everyone can be
happy. I'm not sure if we have the best predicate here, but the intent is to undo the
extra hop-iness that was enabled by r344141.
Differential Revision: https://reviews.llvm.org/D53095
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344361
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Desaulniers [Fri, 12 Oct 2018 16:35:44 +0000 (16:35 +0000)]
[MC][ELF] fix newly added test
Summary:
Reland of
- r344197 "[MC][ELF] compute entity size for explicit sections"
- r344206 "[MC][ELF] Fix section_mergeable_size.ll"
after being reverted in r344278 due to build breakages from not
specifying a target triple.
Move test from test/CodeGen/Generic/ to test/MC/ELF/.
Add explicit target triple so we don't try to run
this test on non ELF targets.
Reported: https://reviews.llvm.org/D53056#
1261707
Reviewers: fhahn, rnk, espindola, NoQ
Reviewed By: fhahn, rnk
Subscribers: NoQ, MaskRay, rengolin, emaste, arichardson, llvm-commits, pirama, srhines
Differential Revision: https://reviews.llvm.org/D53146
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344360
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Fri, 12 Oct 2018 16:31:20 +0000 (16:31 +0000)]
Make YAML quote forward slashes.
If you have the string /usr/bin, prior to this patch it would not
be quoted by our YAML serializer. But a string like C:\src would
be, due to the presence of a backslash. This makes the quoting
rules of basically every single file path different depending on
the path syntax (posix vs. Windows).
While technically not required by the YAML specification to quote
forward slashes, when the behavior of paths is inconsistent it
makes it difficult to portably write FileCheck lines that will
work with either kind of path.
Differential Revision: https://reviews.llvm.org/D53169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344359
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Fri, 12 Oct 2018 16:31:08 +0000 (16:31 +0000)]
Revert "Make YAML quote forward slashes."
This reverts commit
b86c16ad8c97dadc1f529da72a5bb74e9eaed344.
This is being reverted because I forgot to write a useful
commit message, so I'm going to resubmit it with an actual
commit message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344358
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Fri, 12 Oct 2018 16:24:09 +0000 (16:24 +0000)]
Make YAML quote forward slashes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344357
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 12 Oct 2018 15:49:19 +0000 (15:49 +0000)]
Pull out repeated value types. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344355
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 12 Oct 2018 15:48:47 +0000 (15:48 +0000)]
Pull out repeated value types. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344354
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 12 Oct 2018 15:22:14 +0000 (15:22 +0000)]
[AArch64][x86] add tests for trunc disguised as vector ops (PR39016); NFC
These correspond to the IR transform from:
D52439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344353
91177308-0d34-0410-b5e6-
96231b3b80d8
Guillaume Chatelet [Fri, 12 Oct 2018 15:12:22 +0000 (15:12 +0000)]
[llvm-exegesis][NFC] Simplify code at the cost of small code duplication
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344351
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Liu [Fri, 12 Oct 2018 15:01:11 +0000 (15:01 +0000)]
Fix unused variable warning after r344348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344350
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 12 Oct 2018 14:45:57 +0000 (14:45 +0000)]
[SelectionDAG] Move VectorLegalizer::ExpandCTLZ codegen into SelectionDAGLegalize
Generalize SelectionDAGLegalize's CTLZ expansion to handle vectors - lets VectorLegalizer::ExpandCTLZ to just pass the expansion on instead of repeating the same codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344349
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 12 Oct 2018 14:18:47 +0000 (14:18 +0000)]
[X86][SSE] LowerVectorCTPOP - pull out repeated byte sum stage.
Pull out repeated byte sum stage for popcount of vector elements > 8bits.
This allows us to simplify the LUT/BITMATH popcnt code to always assume vXi8 vectors, and also improves avx512bitalg codegen which only has access to vpopcntb/vpopcntw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344348
91177308-0d34-0410-b5e6-
96231b3b80d8
Hiroshi Inoue [Fri, 12 Oct 2018 14:02:20 +0000 (14:02 +0000)]
[PowerPC] avoid masking already-zero bits in BitPermutationSelector
The current BitPermutationSelector generates a code to build a value by tracking two types of bits: ConstZero and Variable.
ConstZero means a bit we need to mask off and Variable is a bit we copy from an input value.
This patch add third type of bits VariableKnownToBeZero caused by AssertZext node or zero-extending load node.
VariableKnownToBeZero means a bit comes from an input value, but it is known to be already zero. So we do not need to mask them.
VariableKnownToBeZero enhances flexibility to group bits, since we can avoid redundant masking for these bits.
This patch also renames "HasZero" to "NeedMask" since now we may skip masking even when we have zeros (of type VariableKnownToBeZero).
Differential Revision: https://reviews.llvm.org/D48025
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344347
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Moroz [Fri, 12 Oct 2018 13:59:31 +0000 (13:59 +0000)]
[SanitizerCoverage] Make Inline8bit and TracePC counters dead stripping resistant.
Summary:
Otherwise, at least on Mac, the linker eliminates unused symbols which
causes libFuzzer to error out due to a mismatch of the sizes of coverage tables.
Issue in Chromium: https://bugs.chromium.org/p/chromium/issues/detail?id=892167
Reviewers: morehouse, kcc, george.karpenkov
Reviewed By: morehouse
Subscribers: kubamracek, llvm-commits
Differential Revision: https://reviews.llvm.org/D53113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344345
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 12 Oct 2018 13:24:51 +0000 (13:24 +0000)]
[X86][AVX] Regenerate tzcnt tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344341
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Fri, 12 Oct 2018 12:38:27 +0000 (12:38 +0000)]
[llvm-mca] Remove method RegisterFileStatistics::initializeRegisterFileInfo(). NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344339
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Parker [Fri, 12 Oct 2018 12:26:37 +0000 (12:26 +0000)]
Fix documentation of MachineInstr::getNumOperands
The documentation stated "Access to explicit operands of the
instruction." This is misleading, as it also lists implicit operands.
Patch by Philip Ginsbach.
Differential Revision: https://reviews.llvm.org/D35481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344338
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 12 Oct 2018 12:10:34 +0000 (12:10 +0000)]
[X86][SSE] Add extract_subvector(PSHUFB) -> PSHUFB(extract_subvector()) combine
Fixes PR32160 by reducing the size of PSHUFB if we only use one of the lanes.
This approach can probably be generalized to handle any target shuffle (and any subvector index) but we have no test coverage at the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344336
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Fri, 12 Oct 2018 11:23:04 +0000 (11:23 +0000)]
[tblgen][llvm-mca] Add the ability to describe move elimination candidates via tablegen.
This patch adds the ability to identify instructions that are "move elimination
candidates". It also allows scheduling models to describe processor register
files that allow move elimination.
A move elimination candidate is an instruction that can be eliminated at
register renaming stage.
Each subtarget can specify which instructions are move elimination candidates
with the help of tablegen class "IsOptimizableRegisterMove" (see
llvm/Target/TargetInstrPredicate.td).
For example, on X86, BtVer2 allows both GPR and MMX/SSE moves to be eliminated.
The definition of 'IsOptimizableRegisterMove' for BtVer2 looks like this:
```
def : IsOptimizableRegisterMove<[
InstructionEquivalenceClass<[
// GPR variants.
MOV32rr, MOV64rr,
// MMX variants.
MMX_MOVQ64rr,
// SSE variants.
MOVAPSrr, MOVUPSrr,
MOVAPDrr, MOVUPDrr,
MOVDQArr, MOVDQUrr,
// AVX variants.
VMOVAPSrr, VMOVUPSrr,
VMOVAPDrr, VMOVUPDrr,
VMOVDQArr, VMOVDQUrr
], CheckNot<CheckSameRegOperand<0, 1>> >
]>;
```
Definitions of IsOptimizableRegisterMove from processor models of a same
Target are processed by the SubtargetEmitter to auto-generate a target-specific
override for each of the following predicate methods:
```
bool TargetSubtargetInfo::isOptimizableRegisterMove(const MachineInstr *MI)
const;
bool MCInstrAnalysis::isOptimizableRegisterMove(const MCInst &MI, unsigned
CPUID) const;
```
By default, those methods return false (i.e. conservatively assume that there
are no move elimination candidates).
Tablegen class RegisterFile has been extended with the following information:
- The set of register classes that allow move elimination.
- Maxium number of moves that can be eliminated every cycle.
- Whether move elimination is restricted to moves from registers that are
known to be zero.
This patch is structured in three part:
A first part (which is mostly boilerplate) adds the new
'isOptimizableRegisterMove' target hooks, and extends existing register file
descriptors in MC by introducing new fields to describe properties related to
move elimination.
A second part, uses the new tablegen constructs to describe move elimination in
the BtVer2 scheduling model.
A third part, teaches llm-mca how to query the new 'isOptimizableRegisterMove'
hook to mark instructions that are candidates for move elimination. It also
teaches class RegisterFile how to describe constraints on move elimination at
PRF granularity.
llvm-mca tests for btver2 show differences before/after this patch.
Differential Revision: https://reviews.llvm.org/D53134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344334
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 12 Oct 2018 10:26:59 +0000 (10:26 +0000)]
[X86][AVX] Add examples of shuffles that can be reduced to a cross-lane shuffle followed by a in-lane permute
Suitable for lowering by D53148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344332
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 12 Oct 2018 10:20:16 +0000 (10:20 +0000)]
[X86] Ignore float/double non-temporal loads (PR39256)
Scalar non-temporal loads were asserting instead of just being ignored.
Reduced from https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=10895
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344331
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Fri, 12 Oct 2018 09:01:59 +0000 (09:01 +0000)]
SCCP: avoid caching DenseMap entry that might be invalidated.
Later calls to getValueState might insert entries into the ValueState map and
cause reallocation, invalidating a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344327
91177308-0d34-0410-b5e6-
96231b3b80d8
Stefan Maksimovic [Fri, 12 Oct 2018 08:18:38 +0000 (08:18 +0000)]
[mips] Mark fmaxl as a long double emulation routine
Failure was discovered upon running
projects/compiler-rt/test/builtins/Unit/divtc3_test.c
in a stage2 compiler build.
When compiling projects/compiler-rt/lib/builtins/divtc3.c,
a call to fmaxl within the divtc3 implementation had its
return values read from registers $2 and $3 instead of $f0 and $f2.
Include fmaxl in the list of long double emulation routines
to have its return value correctly interpreted as f128.
Almost exact issue here: https://reviews.llvm.org/D17760
Differential Revision: https://reviews.llvm.org/D52649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344326
91177308-0d34-0410-b5e6-
96231b3b80d8
Eugene Leviant [Fri, 12 Oct 2018 07:24:02 +0000 (07:24 +0000)]
[ThinLTO] Don't import GV which contains blockaddress
Differential revision: https://reviews.llvm.org/D53139
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344325
91177308-0d34-0410-b5e6-
96231b3b80d8
Jordan Rupprecht [Fri, 12 Oct 2018 00:36:01 +0000 (00:36 +0000)]
[llvm-objcopy] Add -F|--target compatibility
Summary:
This change adds support for the GNU --target flag, which sets both --input-target and --output-target.
GNU objcopy doesn't do any checking for whether both --target and --{input,output}-target are used, and so it allows both, e.g. "--target A --output-target B" is equivalent to "--input-target A --output-target B" since the later command line flag would override earlier ones. This may be error prone, so I chose to implement it as an error if both are used. I'm not sure if anyone is actually using both.
Reviewers: jakehehrlich, jhenderson, alexshap
Reviewed By: jakehehrlich, alexshap
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53029
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344321
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 11 Oct 2018 23:56:56 +0000 (23:56 +0000)]
[DAGCombiner] rearrange extract_element+bitcast fold; NFC
I want to add another pattern here that includes scalar_to_vector,
so this makes that patch smaller. I was hoping to remove the
hasOneUse() check because it shouldn't be necessary for common
codegen, but an AMDGPU test has a comment suggesting that the
extra check makes things better on one of those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344320
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Thu, 11 Oct 2018 23:37:58 +0000 (23:37 +0000)]
Revert "DwarfDebug: Pick next location in case of missing location at block begin"
It originally triggered a stepping problem in the debugger, which could
be fixed by adjusting CodeGen/LexicalScopes.cpp however it seems we prefer
the previous behavior anyway.
See the discussion for details: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20181008/593833.html
This reverts commit r343880.
This reverts commit r343874.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344318
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Thu, 11 Oct 2018 23:36:46 +0000 (23:36 +0000)]
Revert "AMDGPU/GlobalISel: Implement select for G_INSERT"
This reverts commit r344310.
The test case was failing on some bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344317
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Thu, 11 Oct 2018 23:14:35 +0000 (23:14 +0000)]
X86/TargetTransformInfo: Report div/rem constant immediate costs as TCC_Free
DIV/REM by constants should always be expanded into mul/shift/etc.
patterns. Unfortunately the ConstantHoisting pass runs too early at a
point where the pattern isn't expanded yet. However after
ConstantHoisting hoisted some immediate the result may not expand
anymore. Also the hoisting typically doesn't make sense because it
operates on immediates that will change completely during the expansion.
Report DIV/REM as TCC_Free so ConstantHoisting will not touch them.
Differential Revision: https://reviews.llvm.org/D53174
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344315
91177308-0d34-0410-b5e6-
96231b3b80d8
Kostya Serebryany [Thu, 11 Oct 2018 23:03:27 +0000 (23:03 +0000)]
merge two near-identical functions createPrivateGlobalForString into one
Summary:
We have two copies of createPrivateGlobalForString (in asan and in esan).
This change merges them into one. NFC
Reviewers: vitalybuka
Reviewed By: vitalybuka
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344314
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Thu, 11 Oct 2018 22:49:54 +0000 (22:49 +0000)]
AMDGPU/GlobalISel: Implement select for G_INSERT
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D53116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344310
91177308-0d34-0410-b5e6-
96231b3b80d8
Ana Pazos [Thu, 11 Oct 2018 22:49:13 +0000 (22:49 +0000)]
[RISCV] Fix disassembling of fence instruction with invalid field
Summary:
Instruction with 0 in fence field being disassembled as fence , iorw.
Printing "unknown" to match GAS behavior.
This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer
for the RISC-V assembly language.
Reviewers: asb
Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, asb
Differential Revision: https://reviews.llvm.org/D51828
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344309
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Trieu [Thu, 11 Oct 2018 22:42:41 +0000 (22:42 +0000)]
Inline variable into assert to avoid unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344308
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexander Shaposhnikov [Thu, 11 Oct 2018 22:33:50 +0000 (22:33 +0000)]
[llvm-objcopy] Factor out CopyConfig
In this diff we move out CopyConfig from llvm-oobjcopy.cpp into a separate header CopyConfig.h
to enable us (in the future) reuse this class in the other implementations of objcopy (for coff, mach-o).
Additionally this enables us to unload the complexity from llvm-objcopy.cpp a little bit.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D53006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344307
91177308-0d34-0410-b5e6-
96231b3b80d8
Aaron Smith [Thu, 11 Oct 2018 22:25:55 +0000 (22:25 +0000)]
[llvm-pdbutil] Add missing pdb for test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344306
91177308-0d34-0410-b5e6-
96231b3b80d8
Wei Mi [Thu, 11 Oct 2018 22:14:27 +0000 (22:14 +0000)]
[SampleFDO][NFC] Remove debugging log left over in the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344304
91177308-0d34-0410-b5e6-
96231b3b80d8