OSDN Git Service
Lang Hames [Thu, 17 Nov 2016 01:02:52 +0000 (01:02 +0000)]
Remove a stale test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287183
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Peter Collingbourne [Thu, 17 Nov 2016 00:42:08 +0000 (00:42 +0000)]
llvm-dis: Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287182
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Dylan McKay [Thu, 17 Nov 2016 00:09:38 +0000 (00:09 +0000)]
[AVR] Remove some accidentally-commited code that broke the bots
This is a remnant of an on-chip unit testing tool that has since been
moved out-of-tree.
It was accidentally committed in r287162.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287180
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Peter Collingbourne [Wed, 16 Nov 2016 23:40:26 +0000 (23:40 +0000)]
Introduce GlobalSplit pass.
This pass splits globals into elements using inrange annotations on
getelementptr indices.
Differential Revision: https://reviews.llvm.org/D22295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287178
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Dylan McKay [Wed, 16 Nov 2016 23:06:14 +0000 (23:06 +0000)]
[AVR] Wrap all methods in the pseudo expansion pass in an anon namespace
The '-fpermissive' compiler flag complains if the template
specializations used in the class are used in a different namespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287176
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Dylan McKay [Wed, 16 Nov 2016 22:48:38 +0000 (22:48 +0000)]
[AVR] Fix basic block naming in ctlz and cttz tests
The branch selector would change the names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287174
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Dylan McKay [Wed, 16 Nov 2016 22:48:30 +0000 (22:48 +0000)]
[AVR] Remove unused method from AVRTargetMachine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287173
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Dylan McKay [Wed, 16 Nov 2016 22:38:43 +0000 (22:38 +0000)]
[AVR] Add tests for counting leading/trailing zeros
This adds two test files that verify the 'cttz' and 'ctlz' operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287172
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Sanjay Patel [Wed, 16 Nov 2016 22:34:05 +0000 (22:34 +0000)]
[x86] allow FP-logic ops when one operand is FP and result is FP
We save an inter-register file move this way. If there's any CPU where
the FP logic is slower, we could transform this back to int-logic in
MachineCombiner.
This helps, but doesn't solve, PR6137:
https://llvm.org/bugs/show_bug.cgi?id=6137
The 'andn' test shows that we're missing a pattern match to
recognize the xor with -1 constant as a 'not' op.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287171
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Ahmed Bougacha [Wed, 16 Nov 2016 22:25:05 +0000 (22:25 +0000)]
[AsmParser] Avoid recursing when lexing ';'. NFC.
This should prevent stack overflows in non-optimized builds on
.ll files with lots of consecutive commented-out lines.
Instead of recursing into LexToken(), continue into a 'while (true)'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287170
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Ahmed Bougacha [Wed, 16 Nov 2016 22:25:03 +0000 (22:25 +0000)]
[CodeGen] Pass references, not pointers, to MMI helpers. NFC.
While there, rename them to follow the coding style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287169
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Ahmed Bougacha [Wed, 16 Nov 2016 22:24:59 +0000 (22:24 +0000)]
Revert "Get GlobalISel to build on Linux after r286407"
This reverts commit r286962.
We want to avoid depending on SelectionDAG, and AddLandingPadInfo
lives in CodeGen now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287168
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Ahmed Bougacha [Wed, 16 Nov 2016 22:24:56 +0000 (22:24 +0000)]
[CodeGen] Pull MMI helpers from FunctionLoweringInfo to MMI. NFC.
They're not SelectionDAG- or FunctionLoweringInfo-specific. They
are, however, specific to building MMI from IR.
We could make them members, but it's nice having MMI be a "simple" data
structure and this logic kept separate.
This also lets us reuse them from GlobalISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287167
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Ahmed Bougacha [Wed, 16 Nov 2016 22:24:53 +0000 (22:24 +0000)]
[CodeGen] Cleanup MachineModuleInfo doxygen comments. NFC.
Remove redundant names and only keep header comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287166
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Ahmed Bougacha [Wed, 16 Nov 2016 22:24:46 +0000 (22:24 +0000)]
[CodeGen] Sort MMI forward declarations. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287165
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Kevin Enderby [Wed, 16 Nov 2016 22:17:38 +0000 (22:17 +0000)]
General clean up of error handling in llvm-objdump to remove its use of report_fatal_error().
No real functional change with this commit.
The problem with report_fatal_error() is it does not include the tool name
and the file name the for which the error message was generated.
Uses of report_fatal_error() were change to report_error() or error()
to get a better error and to make the code smaller and cleaner.
Also changed things like error(errorToErrorCode(SOrErr.takeError())) to
use report_error() with a file name and the llvm::Error (as well as the
ArchitectureName if available) so the error message is printed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287163
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Dylan McKay [Wed, 16 Nov 2016 21:58:04 +0000 (21:58 +0000)]
[AVR] Add the pseudo instruction expansion pass
Summary:
A lot of the pseudo instructions are required because LLVM assumes that
all integers of the same size as the pointer size are legal. This means
that it will not currently expand 16-bit instructions to their 8-bit
variants because it thinks 16-bit types are legal for the operations.
This also adds all of the CodeGen tests that required the pass to run.
Reviewers: arsenm, kparzysz
Subscribers: wdng, mgorny, modocache, llvm-commits
Differential Revision: https://reviews.llvm.org/D26577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287162
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Vitaly Buka [Wed, 16 Nov 2016 21:51:39 +0000 (21:51 +0000)]
Fix "isn't a prototype" warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287161
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Peter Collingbourne [Wed, 16 Nov 2016 21:48:59 +0000 (21:48 +0000)]
X86: Simplify X86ISD::Wrapper operand checks. NFCI.
We only ever create TargetConstantPool, TargetJumpTable, TargetExternalSymbol,
TargetGlobalAddress, TargetGlobalTLSAddress, MCSymbol and TargetBlockAddress
nodes as operands of X86ISD::Wrapper nodes, so we can remove one check and
invert the other.
Also update the documentation comment for X86ISD::Wrapper.
Differential Revision: https://reviews.llvm.org/D26731
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287160
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Sanjoy Das [Wed, 16 Nov 2016 21:45:22 +0000 (21:45 +0000)]
[ImplicitNullChecks] Do not not handle call MachineInstrs
We don't track callee clobbered registers correctly, so avoid hoisting
across calls.
Note: for this bug to trigger we need a `readonly` call target, since we
already have logic to not hoist across potentially storing instructions
either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287159
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Peter Collingbourne [Wed, 16 Nov 2016 21:44:45 +0000 (21:44 +0000)]
Bitcode: Introduce initial multi-module reader API.
Implement getLazyBitcodeModule() and parseBitcodeFile() in terms of it.
Differential Revision: https://reviews.llvm.org/D26719
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287156
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Tim Northover [Wed, 16 Nov 2016 20:54:28 +0000 (20:54 +0000)]
ARM: fix CodeGen for 64-bit shifts.
One half of the shifts obviously needed conditional selection based on whether
the shift amount is more than 32-bits, but leaving the other half as the
natural shift isn't acceptable either: it's undefined behaviour to shift a
32-bit value by more than 31.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287149
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Rong Xu [Wed, 16 Nov 2016 20:50:06 +0000 (20:50 +0000)]
Make block placement deterministic
We fail to produce bit-to-bit matching stage2 and stage3 compiler in PGO
bootstrap build. The reason is because LoopBlockSet is of SmallPtrSet type
whose iterating order depends on the pointer value.
This patch fixes this issue by changing to use SmallSetVector.
Differential Revision: http://reviews.llvm.org/D26634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287148
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Sanjay Patel [Wed, 16 Nov 2016 20:40:02 +0000 (20:40 +0000)]
[InstCombine] replace unreachable with assert and remove unreachable code; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287147
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Matt Arsenault [Wed, 16 Nov 2016 20:35:23 +0000 (20:35 +0000)]
AMDGPU: Enable ConstrainCopy DAG mutation
This fixes a probably unintended divergence from the default
scheduler behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287146
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Sanjay Patel [Wed, 16 Nov 2016 20:18:34 +0000 (20:18 +0000)]
[InstCombine] fix formatting and add FIXMEs to foldOperationIntoSelectOperand(); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287145
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Geoff Berry [Wed, 16 Nov 2016 19:35:19 +0000 (19:35 +0000)]
[AArch64] Handle vector types in replaceZeroVectorStore.
Summary:
Extend replaceZeroVectorStore to handle more vector type stores,
floating point zero vectors and set alignment more accurately on split
stores.
This is a follow-up change to r286875.
This change fixes PR31038.
Reviewers: MatzeB
Subscribers: mcrosier, aemerson, llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D26682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287142
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Mandeep Singh Grang [Wed, 16 Nov 2016 18:53:17 +0000 (18:53 +0000)]
[LoopVectorize] Fix for non-determinism in codegen
Summary: This patch fixes issues in codegen uncovered due to https://reviews.llvm.org/D26718
Reviewers: mssimpso
Subscribers: llvm-commits, mzolotukhin
Differential Revision: https://reviews.llvm.org/D26727
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287135
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Tom Stellard [Wed, 16 Nov 2016 18:42:17 +0000 (18:42 +0000)]
AMDGPU/SI: Avoid creating unnecessary copies in the SIFixSGPRCopies pass
Summary:
1. Don't try to copy values to and from the same register class.
2. Replace copies with of registers with immediate values with v_mov/s_mov
instructions.
The main purpose of this change is to make MachineSink do a better job of
determining when it is beneficial to split a critical edge, since the pass
assumes that copies will become move instructions.
This prevents a regression in uniform-cfg.ll if we enable critical edge
splitting for AMDGPU.
Reviewers: arsenm
Subscribers: arsenm, kzhuravl, llvm-commits
Differential Revision: https://reviews.llvm.org/D23408
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287131
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Eugene Zelenko [Wed, 16 Nov 2016 18:32:58 +0000 (18:32 +0000)]
[ExecutionEngine] Fix examples build broken in r287126 and other Include What You Use warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287130
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Sanjay Patel [Wed, 16 Nov 2016 18:09:44 +0000 (18:09 +0000)]
fix comment formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287127
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Eugene Zelenko [Wed, 16 Nov 2016 18:07:33 +0000 (18:07 +0000)]
[ExecutionEngine] Fix some Clang-tidy modernize-use-default, modernize-use-equals-delete and Include What You Use warnings; other minor fixes.
Differential revision: https://reviews.llvm.org/D26729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287126
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Sanjay Patel [Wed, 16 Nov 2016 17:42:40 +0000 (17:42 +0000)]
[x86] add fake scalar FP logic instructions to ReplaceableInstrs to save some bytes
We can replace "scalar" FP-bitwise-logic with other forms of bitwise-logic instructions.
Scalar SSE/AVX FP-logic instructions only exist in your imagination and/or the bowels of
compilers, but logically equivalent int, float, and double variants of bitwise-logic
instructions are reality in x86, and the float variant may be a shorter instruction
depending on which flavor (SSE or AVX) of vector ISA you have...so just prefer float all
the time.
This is a preliminary step towards solving PR6137:
https://llvm.org/bugs/show_bug.cgi?id=6137
Differential Revision:
https://reviews.llvm.org/D26712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287122
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Lang Hames [Wed, 16 Nov 2016 17:31:09 +0000 (17:31 +0000)]
[Orc] Re-enable the RPC unit test disabled in r286917.
This unit test infinite-looped on s390x due to a thread_yield being optimized
out. I've updated the QueueChannel class (where thread_yield was called) to use
a condition variable instead. This should cause the unit test to behave
correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287121
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Reid Kleckner [Wed, 16 Nov 2016 16:50:43 +0000 (16:50 +0000)]
[sancov] Name the global containing the main source file name
If the global name doesn't start with __sancov_gen, ASan will insert
unecessary red zones around it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287117
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Daniil Fukalov [Wed, 16 Nov 2016 16:41:40 +0000 (16:41 +0000)]
test commit, changed tab to spaces, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287116
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Pekka Jaaskelainen [Wed, 16 Nov 2016 15:22:23 +0000 (15:22 +0000)]
Add a little endian variant of TCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287111
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Simon Pilgrim [Wed, 16 Nov 2016 14:54:34 +0000 (14:54 +0000)]
[X86] Add integer division test for PR23590
Shows missed opportunity to recognise reduced integer division result size
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287110
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Simon Pilgrim [Wed, 16 Nov 2016 14:48:32 +0000 (14:48 +0000)]
[X86][AVX512] Autoupgrade lossless i32/u32 to f64 conversion intrinsics with generic IR
Both the (V)CVTDQ2PD (i32 to f64) and (V)CVTUDQ2PD (u32 to f64) conversion instructions are lossless and can be safely represented as generic SINT_TO_FP/UINT_TO_FP calls instead of x86 intrinsics without affecting final codegen.
LLVM counterpart to D26686
Differential Revision: https://reviews.llvm.org/D26736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287108
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Simon Pilgrim [Wed, 16 Nov 2016 14:24:04 +0000 (14:24 +0000)]
[X86][AVX512] Added some mask/maskz tests for sitofp/uitofp i32 to f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287106
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Simon Pilgrim [Wed, 16 Nov 2016 14:12:11 +0000 (14:12 +0000)]
[X86] Regenerated integer divide tests to test on 32 and 64 bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287104
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Simon Pilgrim [Wed, 16 Nov 2016 13:59:03 +0000 (13:59 +0000)]
[X86][SSE] Added PSUBUS from SELECT tests from D25987
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287103
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Simon Dardis [Wed, 16 Nov 2016 11:29:07 +0000 (11:29 +0000)]
[mips] Fix unsigned/signed type error
MipsFastISel uses a a class to represent addresses with a signed member
to represent the offset. MipsFastISel::emitStore, emitLoad and computeAddress
all treated the offset as being positive. In cases where the offset was
actually negative and a frame pointer was used, this would cause the constant
synthesis routine to crash as it would generate an unexpected instruction
sequence when frame indexes are replaced.
Reviewers: vkalintiris
Differential Revision: https://reviews.llvm.org/D26192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287099
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Simon Dardis [Wed, 16 Nov 2016 11:04:49 +0000 (11:04 +0000)]
[mips] not instruction alias
This patch adds the single operand form of the not alias to microMIPS and
MIPS along with additional tests.
This partially resolves PR/30381.
Thanks to Sean Bruno for reporting the issue!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287097
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Pavel Labath [Wed, 16 Nov 2016 10:46:48 +0000 (10:46 +0000)]
Remove TimeValue class
Summary:
All uses have been replaced by appropriate std::chrono types, and the class is
now unused.
Reviewers: zturner, mehdi_amini
Subscribers: llvm-commits, mgorny
Differential Revision: https://reviews.llvm.org/D26447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287094
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Ayman Musa [Wed, 16 Nov 2016 09:00:28 +0000 (09:00 +0000)]
[X86][AVX512] Removing llvm x86 intrinsics for _mm_mask_move_{ss|sd} intrinsics.
Differential Revision: https://reviews.llvm.org/D26128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287087
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Craig Topper [Wed, 16 Nov 2016 05:24:10 +0000 (05:24 +0000)]
[X86] Remove the scalar intrinsics for fadd/fsub/fdiv/fmul
Summary: These intrinsics have been unused for clang for a while. This patch removes them. We auto upgrade them to extractelements, a scalar operation and then an insertelement. This matches the sequence used by clangs intrinsic file.
Reviewers: zvi, delena, RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26660
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287083
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Davide Italiano [Wed, 16 Nov 2016 05:10:28 +0000 (05:10 +0000)]
[ELF] Convert ELF.h to Expected<T>.
This has two advantages:
1) We slowly move away from ErrorOr to the new handling interface,
in the hope of having an uniform error handling in LLVM, eventually.
2) We're starting to have *meaningful* error messages for invalid
object ELF files, rather than a generic "parse error". At some point
we should include also the offset to improve the quality of the
diagnostic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287081
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Saleem Abdulrasool [Wed, 16 Nov 2016 04:08:46 +0000 (04:08 +0000)]
test: use separate input file for test
Rather than using sed to generate the input and pipe the result to
strings, use the static input instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287079
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Konstantin Zhuravlyov [Wed, 16 Nov 2016 03:39:12 +0000 (03:39 +0000)]
[AMDGPU] Refactor v_mac_{f16, f32} patterns into a class NFC
Differential Revision: https://reviews.llvm.org/D26711
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287077
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Matthias Braun [Wed, 16 Nov 2016 03:38:27 +0000 (03:38 +0000)]
AArch64: Use DeadRegisterDefinitionsPass before regalloc.
Doing this before register allocation reduces register pressure as we do
not even have to allocate a register for those dead definitions.
Differential Revision: https://reviews.llvm.org/D26111
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287076
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Richard Smith [Wed, 16 Nov 2016 03:36:29 +0000 (03:36 +0000)]
Fix build break when the host C compiler is C89.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287075
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Konstantin Zhuravlyov [Wed, 16 Nov 2016 03:16:26 +0000 (03:16 +0000)]
[AMDGPU] Handle f16 select{_cc}
- Select `select` to `v_cndmask_b32`
- Expand `select_cc`
- Refactor patterns
Differential Revision: https://reviews.llvm.org/D26714
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287074
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Dean Michael Berris [Wed, 16 Nov 2016 02:18:23 +0000 (02:18 +0000)]
[XRay][docs] Define requirements on installed log handlers.
Summary:
We update the documentation to define what the requirements are for the
provided XRay log handler. This is to make it clear that the function
pointer provided must do internal synchronisation and that there are no
guarantees provided by XRay on when the function shall be invoked once
it has been installed as a log handler.
Reviewers: rSerge, rengolin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287073
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Quentin Colombet [Wed, 16 Nov 2016 01:07:12 +0000 (01:07 +0000)]
[RegAllocGreedy] Record missed hint for late recoloring.
In https://reviews.llvm.org/D25347, Geoff noticed that we still have
useless copy that we can eliminate after register allocation. At the
time the allocation is chosen for those copies, they are not useless
but, because of changes in the surrounding code, later on they might
become useless.
The Greedy allocator already has a mechanism to deal with such cases
with a late recoloring. However, we missed to record the some of the
missed hints.
This commit fixes that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287070
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Rui Ueyama [Wed, 16 Nov 2016 00:59:27 +0000 (00:59 +0000)]
Align Modi and FileInfo substreams on 32-byte offsets.
This is required by DbiStream, but DbiStreamBuilder didn't align
these substreams, so the output of DbiSTreamBuilder couldn't be
read by DbiStream.
Test will be added to LLD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287067
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Vyacheslav Klochkov [Wed, 16 Nov 2016 00:55:50 +0000 (00:55 +0000)]
Fixed the lost FastMathFlags for CALL operations in SLPVectorizer.
Reviewer: Michael Zolotukhin.
Differential Revision: https://reviews.llvm.org/D26575
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287064
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Justin Lebar [Wed, 16 Nov 2016 00:44:47 +0000 (00:44 +0000)]
[BypassSlowDivision] Handle division by constant numerators better.
Summary:
We don't do BypassSlowDivision when the denominator is a constant, but
we do do it when the numerator is a constant.
This patch makes two related changes to BypassSlowDivision when the
numerator is a constant:
* If the numerator is too large to fit into the bypass width, don't
bypass slow division (because we'll never run the smaller-width
code).
* If we bypass slow division where the numerator is a constant, don't
OR together the numerator and denominator when determining whether
both operands fit within the bypass width. We need to check only the
denominator.
Reviewers: tra
Subscribers: llvm-commits, jholewinski
Differential Revision: https://reviews.llvm.org/D26699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287062
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Justin Lebar [Wed, 16 Nov 2016 00:44:43 +0000 (00:44 +0000)]
[BypassSlowDivision] Simplify partially-tautological if statement.
if (A || (B && A)) --> if (A).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287061
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Rui Ueyama [Wed, 16 Nov 2016 00:38:33 +0000 (00:38 +0000)]
Fix Modi and File count if there are more than 65535 modules/files.
These numbers are intended to be capped at 65535, but
`std::max<uint16_t>(UINT16_MAX, N)` always returns N for any N because
the expression is the same as `std::max((uint16_t)UINT16_MAX, (uint16_t)N)`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287060
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Joerg Sonnenberger [Wed, 16 Nov 2016 00:37:30 +0000 (00:37 +0000)]
Always use relative jump table encodings on PowerPC64.
For the default, small and medium code model, use the existing
difference from the jump table towards the label. For all other code
models, setup the picbase and use the difference between the picbase and
the block address.
Overall, this results in smaller data tables at the expensive of one or
two more arithmetic operation at the jump site. Given that we only create
jump tables with a lot more than two entries, it is a net win in size.
For larger code models the assumption remains that individual functions
are no larger than 2GB.
Differential Revision: https://reviews.llvm.org/D26336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287059
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Jan Vesely [Tue, 15 Nov 2016 23:55:15 +0000 (23:55 +0000)]
AMDGPU/GCN: Exit early in hazard recognizer if there is no vreg argument
wbinvl.* are vector instruction that do not sue vector registers.
v2: check only M?BUF instructions
Differential Revision: https://reviews.llvm.org/D26633
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287056
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Sanjay Patel [Tue, 15 Nov 2016 23:09:53 +0000 (23:09 +0000)]
[x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287051
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Kevin Enderby [Tue, 15 Nov 2016 23:07:41 +0000 (23:07 +0000)]
General clean up of Mach-O error handling in llvm-objdump.
To get a good error message for all files that could contain Mach-O
files the code in llvm-objdump needs to use the archive member name
and name of the architecture of a slice of a universal file in those cases
where the error come from a Mach-O file in an archive or a universal file.
Most of this is fixed by moving the call to checkSymbolTable() into
ProcessMachO() and calling it when the operation needs the symbol
table. And then calling the form of report_error() that has the
ArchiveName and ArchitectureName arguments. One other place
needed to call this form of report_error() also with these arguments.
Also changed the code in MachODump.cpp to not use report_fatal_error()
and use report_error() instead to make the code smaller and cleaner. All
cases of this are for errors with the symbol table which should now never
be tripped since checkSymbolTable() should be called first to get a good
error message in these cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287050
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Sanjay Patel [Tue, 15 Nov 2016 23:01:11 +0000 (23:01 +0000)]
[x86] auto-generate better checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287049
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Sanjay Patel [Tue, 15 Nov 2016 22:42:20 +0000 (22:42 +0000)]
[x86] auto-generate better checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287048
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Filipe Cabecinhas [Tue, 15 Nov 2016 22:37:30 +0000 (22:37 +0000)]
[AddressSanitizer] Add support for (constant-)masked loads and stores.
This patch adds support for instrumenting masked loads and stores under
ASan, if they have a constant mask.
isInterestingMemoryAccess now supports returning a mask to be applied to
the loads, and instrumentMop will use it to generate additional checks.
Added tests for v4i32 v8i32, and v4p0i32 (~v4i64) for both loads and
stores (as well as a test to verify we don't add checks to non-constant
masks).
Differential Revision: https://reviews.llvm.org/D26230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287047
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Sanjay Patel [Tue, 15 Nov 2016 22:33:16 +0000 (22:33 +0000)]
[x86] auto-generate better checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287046
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Amaury Sechet [Tue, 15 Nov 2016 22:19:59 +0000 (22:19 +0000)]
[C API] Prevent nullptr dereferences in C API for counting attributes.
See https://reviews.llvm.org/D26392
Patch by @maleadt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287044
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Peter Collingbourne [Tue, 15 Nov 2016 21:36:35 +0000 (21:36 +0000)]
Object: replace backslashes with slashes in embedded relative thin archive paths on Windows.
This makes these thin archives portable between *nix and Windows.
Differential Revision: https://reviews.llvm.org/D26696
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287038
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Chad Rosier [Tue, 15 Nov 2016 21:34:12 +0000 (21:34 +0000)]
[AArch64] Add support for Qualcomm's Falkor CPU.
Differential Revision: https://reviews.llvm.org/D26673
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287036
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Tom Stellard [Tue, 15 Nov 2016 21:25:56 +0000 (21:25 +0000)]
AMDGPU/SI: Fix pattern for i16 = sign_extend i1
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D26670
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287035
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Sanjay Patel [Tue, 15 Nov 2016 21:19:28 +0000 (21:19 +0000)]
[x86] add tests for FP-logic equivalent instruction replacement
The ANDN test needs at least 3 different fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287032
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Chad Rosier [Tue, 15 Nov 2016 21:18:18 +0000 (21:18 +0000)]
[AArch64] Refactor test per Matthias' request.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287031
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Kostya Serebryany [Tue, 15 Nov 2016 21:12:50 +0000 (21:12 +0000)]
[sanitizer-coverage] make sure asan does not instrument coverage guards (reported in https://github.com/google/oss-fuzz/issues/84)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287030
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Kuba Brecka [Tue, 15 Nov 2016 21:07:03 +0000 (21:07 +0000)]
Fix llvm-symbolizer to correctly sort a symbol array and calculate symbol sizes
Sometimes, llvm-symbolizer gives wrong results due to incorrect sizes of some symbols. The reason for that was an incorrectly sorted array in computeSymbolSizes. The comparison function used subtraction of unsigned types, which is incorrect. Let's change this to return explicit -1 or 1.
Differential Revision: https://reviews.llvm.org/D26537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287028
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Tim Northover [Tue, 15 Nov 2016 21:06:07 +0000 (21:06 +0000)]
GlobalISel: remove unused variable to silence warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287027
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Tim Northover [Tue, 15 Nov 2016 20:26:01 +0000 (20:26 +0000)]
llvm-objdump: deal with unexpected object files more gracefully.
Specifically, we don't want to segfault on release builds, so print the problem
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287022
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Matt Arsenault [Tue, 15 Nov 2016 20:22:55 +0000 (20:22 +0000)]
AMDGPU: Enable store clustering
Also respect the TII hook for these like the generic code does
in case we want a flag later to disable this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287021
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Haicheng Wu [Tue, 15 Nov 2016 20:16:48 +0000 (20:16 +0000)]
[AArch64] Lower multiplication by a constant int to shl+add+shl
Lower a = b * C where C = (2^n + 1) * 2^m to
add w0, w0, w0, lsl n
lsl w0, w0, m
Differential Revision: https://reviews.llvm.org/
D229245
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287019
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Matt Arsenault [Tue, 15 Nov 2016 20:14:27 +0000 (20:14 +0000)]
AMDGPU: Analyze mubuf with immediate soffset
Fixes giving up on clustering common addr64 accesses with
constant 0 soffset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287018
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Matt Arsenault [Tue, 15 Nov 2016 19:58:54 +0000 (19:58 +0000)]
AMDGPU: Fix return after else
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287015
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Wei Mi [Tue, 15 Nov 2016 19:42:05 +0000 (19:42 +0000)]
Revert r286999 which caused buildbot test failures. Some testcases need to be made target specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287014
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Matt Arsenault [Tue, 15 Nov 2016 19:34:37 +0000 (19:34 +0000)]
AMDGPU: Replace assert(false) with unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287013
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Davide Italiano [Tue, 15 Nov 2016 19:15:18 +0000 (19:15 +0000)]
[ELF] Rewrite isMips64EL() using isMipsELF64(). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287011
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Stanislav Mekhanoshin [Tue, 15 Nov 2016 19:00:15 +0000 (19:00 +0000)]
[AMDGPU] Add wave barrier builtin
The wave barrier represents the discardable barrier. Its main purpose is to
carry convergent attribute, thus preventing illegal CFG optimizations. All lanes
in a wave come to convergence point simultaneously with SIMT, thus no special
instruction is needed in the ISA. The barrier is discarded during code generation.
Differential Revision: https://reviews.llvm.org/D26585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287007
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Sanjay Patel [Tue, 15 Nov 2016 18:44:53 +0000 (18:44 +0000)]
[x86] auto-generate checks; NFC
Also, fix the test params to use an attribute rather than a CPU model
and remove the AVX run because that does nothing but check for a 'v'
prefix in all of these tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287003
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Wei Mi [Tue, 15 Nov 2016 18:35:53 +0000 (18:35 +0000)]
[LSR] Allow formula containing Reg for SCEVAddRecExpr related with outerloop.
In RateRegister of existing LSR, if a formula contains a Reg which is a SCEVAddRecExpr,
and this SCEVAddRecExpr's loop is an outerloop, the formula will be marked as Loser
and dropped.
Suppose we have an IR that %for.body is outerloop and %for.body2 is innerloop. LSR only
handle inner loop now so only %for.body2 will be handled.
Using the logic above, formula like
reg(%array) + reg({1,+, %size}<%for.body>) + 1*reg({0,+,1}<%for.body2>) will be dropped
no matter what because reg({1,+, %size}<%for.body>) is a SCEVAddRecExpr type reg related
with outerloop. Only formula like
reg(%array) + 1*reg({{1,+, %size}<%for.body>,+,1}<nuw><nsw><%for.body2>) will be kept
because the SCEVAddRecExpr related with outerloop is folded into the initial value of the
SCEVAddRecExpr related with current loop.
But in some cases, we do need to share the basic induction variable
reg{0 ,+, 1}<%for.body2> among LSR Uses to reduce the final total number of induction
variables used by LSR, so we don't want to drop the formula like
reg(%array) + reg({1,+, %size}<%for.body>) + 1*reg({0,+,1}<%for.body2>) unconditionally.
From the existing comment, it tries to avoid considering multiple level loops at the same time.
However, existing LSR only handles innermost loop, so for any SCEVAddRecExpr with a loop other
than current loop, it is an invariant and will be simple to handle, and the formula doesn't have
to be dropped.
Differential Revision: https://reviews.llvm.org/D26429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286999
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Pawel Bylica [Tue, 15 Nov 2016 18:29:24 +0000 (18:29 +0000)]
Integer legalization: fix MUL expansion
Summary:
This fixes the runtime results produces by the fallback multiplication expansion introduced in r270720.
For tests I created a fuzz tester that compares the results with Boost.Multiprecision.
Reviewers: hfinkel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26628
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286998
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Zaara Syeda [Tue, 15 Nov 2016 17:54:19 +0000 (17:54 +0000)]
vector load store with length (left justified) llvm portion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286993
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Sanjay Patel [Tue, 15 Nov 2016 17:47:13 +0000 (17:47 +0000)]
fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286989
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Wei Mi [Tue, 15 Nov 2016 17:34:52 +0000 (17:34 +0000)]
[IndVars] Change the order to compute WidenAddRec in widenIVUse.
When both WidenIV::getWideRecurrence and WidenIV::getExtendedOperandRecurrence
return non-null but different WideAddRec, if getWideRecurrence is called
before getExtendedOperandRecurrence, we won't bother to call
getExtendedOperandRecurrence again. But As we know it is possible that after
SCEV folding, we cannot prove the legality using the SCEVAddRecExpr returned
by getWideRecurrence. Meanwhile if getExtendedOperandRecurrence returns non-null
WideAddRec, we know for sure that it is legal to do widening for current instruction.
So it is better to put getExtendedOperandRecurrence before getWideRecurrence, which
will increase the chance of successful widening.
Differential Revision: https://reviews.llvm.org/D26059
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286987
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Diana Picus [Tue, 15 Nov 2016 16:42:10 +0000 (16:42 +0000)]
[ARM] GlobalISel: Remove unused members. NFCI
This silences some warnings that I didn't see with my host compiler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286981
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Craig Topper [Tue, 15 Nov 2016 16:27:33 +0000 (16:27 +0000)]
[AVX-512] Add AVX-512 vector shift intrinsics to memory santitizer.
Just needed to add the intrinsics to the exist switch. The code is generic enough to support the wider vectors with no changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286980
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Simon Pilgrim [Tue, 15 Nov 2016 16:24:40 +0000 (16:24 +0000)]
[X86][SSE] Improve SINT_TO_FP of boolean vector results (signum)
This patch helps avoids poor legalization of boolean vector results (e.g. 8f32 -> 8i1 -> 8i16) that feed into SINT_TO_FP by inserting an early SIGN_EXTEND and so help improve the truncation logic.
This is not necessary for AVX512 targets where boolean vectors are legal - AVX512 manages to lower ( sint_to_fp vXi1 ) into some form of ( select mask, 1.0f , 0.0f ) in most cases.
Fix for PR13248
Differential Revision: https://reviews.llvm.org/D26583
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286979
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Sanjay Patel [Tue, 15 Nov 2016 16:01:16 +0000 (16:01 +0000)]
[InstCombine] add tests for bitcasted selects; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286978
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Pablo Barrio [Tue, 15 Nov 2016 15:42:23 +0000 (15:42 +0000)]
Revert "[JumpThreading] Unfold selects that depend on the same condition"
This reverts commit
ac54d0066c478a09c7cd28d15d0f9ff8af984afc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286976
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Pablo Barrio [Tue, 15 Nov 2016 15:42:17 +0000 (15:42 +0000)]
Revert "[JumpThreading] Prevent non-deterministic use lists"
This reverts commit
f2c2f5354070469dac253373c66527ca971ddc66.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286975
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Diana Picus [Tue, 15 Nov 2016 15:38:15 +0000 (15:38 +0000)]
[ARM] Make sure GlobalISel is only initialized once. NFCI
Move some code inside the proper 'if' block to make sure it is only run once,
when the subtarget is first created. Things can still break if we use different
ARM target machines or if we have functions with different 'target-cpu' or
'target-features', we should fix that too in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286974
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Robert Lougher [Tue, 15 Nov 2016 14:27:33 +0000 (14:27 +0000)]
[LoopVectorizer] When estimating reg usage, unused insts may "end" another use
The register usage algorithm incorrectly treats instructions whose value is
not used within the loop (e.g. those that do not produce a value).
The algorithm first calculates the usages within the loop. It iterates over
the instructions in order, and records at which instruction index each use
ends (in fact, they're actually recorded against the next index, as this is
when we want to delete them from the open intervals).
The algorithm then iterates over the instructions again, adding each
instruction in turn to a list of open intervals. Instructions are then
removed from the list of open intervals when they occur in the list of uses
ended at the current index.
The problem is, instructions which are not used in the loop are skipped.
However, although they aren't used, the last use of a value may have been
recorded against that instruction index. In this case, the use is not deleted
from the open intervals, which may then bump up the estimated register usage.
This patch fixes the issue by simply moving the "is used" check after the loop
which erases the uses at the current index.
Differential Revision: https://reviews.llvm.org/D26554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286969
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