OSDN Git Service
Matt Arsenault [Fri, 4 Apr 2014 20:13:13 +0000 (20:13 +0000)]
Add DAG parameter to ComputeNumSignBitsForTargetNode
This way, you can check the number of sign bits in the
operands. The depth parameter it already has is pretty useless
without this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205649
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Fri, 4 Apr 2014 20:13:08 +0000 (20:13 +0000)]
Fix tabs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205648
91177308-0d34-0410-b5e6-
96231b3b80d8
Juergen Ributzka [Fri, 4 Apr 2014 19:57:01 +0000 (19:57 +0000)]
Update the test to use FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205647
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Fri, 4 Apr 2014 17:36:55 +0000 (17:36 +0000)]
Tidy up naming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205633
91177308-0d34-0410-b5e6-
96231b3b80d8
Kai Nacke [Fri, 4 Apr 2014 16:21:59 +0000 (16:21 +0000)]
[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.
This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.
It is only for the assembler. Test case is included.
Reviewed by: Daniel.Sanders@imgtec.com
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205631
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Fri, 4 Apr 2014 15:15:57 +0000 (15:15 +0000)]
[PowerPC] Add a full condition code register to make the "cc" clobber work
gcc inline asm supports specifying "cc" as a clobber of all condition
registers. Add just enough modeling of the full register to make this work.
Fixed PR19326.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205630
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Fri, 4 Apr 2014 14:52:54 +0000 (14:52 +0000)]
[mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math
Summary:
They behave in accordance with the Has2008 and ABS2008 configuration bits of the
processor which are used to select between the 1985 and 2008 versions of IEEE
754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid
operation exceptions when given NaN), in 2008 mode they are non-arithmetic
(i.e. they are copies).
nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because
the ISA spec does not explicitly state that they obey Has2008 and ABS2008.
Reviewers: matheusalmeida
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205628
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Fri, 4 Apr 2014 14:49:30 +0000 (14:49 +0000)]
DAGLegalize: add last-ditch type-legalization for VSELECT.
When LLVM sees something like (v1iN (vselect v1i1, v1iN, v1iN)) it can
decide that the result is OK (v1i64 is legal on AArch64, for example)
but it still need scalarising because of that v1i1. There was no code
to do this though.
AArch64 and ARM64 have DAG combines to produce efficient code and
prevent that occuring in *most* such situations, but there are edge
cases that they miss. This adds a legalization to cope with that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205626
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Fri, 4 Apr 2014 14:49:21 +0000 (14:49 +0000)]
ARM64: handle v1i1 types arising from setcc properly.
There were several overlapping problems here, and this solution is
closely inspired by the one adopted in AArch64 in r201381.
Firstly, scalarisation of v1i1 setcc operations simply fails if the
input types are legal. This is fixed in LegalizeVectorTypes.cpp this
time, and allows AArch64 code to be simplified slightly.
Second, vselect with such a setcc feeding into it ends up in
ScalarizeVectorOperand, where it's not handled. I experimented with an
implementation, but found that whatever DAG came out was rather
horrific. I think Hao's DAG combine approach is a good one for
quality, though there are edge cases it won't catch (to be fixed
separately).
Should fix PR19335.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205625
91177308-0d34-0410-b5e6-
96231b3b80d8
Stepan Dyatkovskiy [Fri, 4 Apr 2014 10:17:56 +0000 (10:17 +0000)]
Fix for PR18921 (LDRD/STRD part)::
Removed "GNU Assembler extension (compatibility)" definitions from ARMInstrInfo.td
Fixed ARMAsmParser::ParseInstruction GNU compatability branch, so it also works for thumb mode from now.
Added new tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205622
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Fri, 4 Apr 2014 10:16:51 +0000 (10:16 +0000)]
Tweak unconditional-branch.ll passing on any hosts, while investigating x86_64-mingw32.
Sorry for the breakage.
For now, it will fail in two ways:
1. To fail for targeting x86_64-mingw32.
<stdin>:131:8: note: possible intended match here
0x30830a0100000002 3 0 1 0 0 is_stmt
2. To fail not to find the target x86.
llc: : error: unable to get target for 'x86_64-unknown-unknown',
see --version and --triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205621
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Fri, 4 Apr 2014 09:03:09 +0000 (09:03 +0000)]
ARM64: use regalloc-friendly COPY_TO_REGCLASS for bitcasts
The previous patterns directly inserted FMOV or INS instructions into
the DAG for scalar_to_vector & bitconvert patterns. This is horribly
inefficient and can generated lots more GPR <-> FPR register traffic
than necessary.
It's much better to emit instructions the register allocator
understands so it can coalesce the copies when appropriate.
It led to at least one ISelLowering hack to avoid the problems, which
was incorrect for v1i64 (FPR64 has no dsub). It can now be removed
entirely.
This should also fix PR19331.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205616
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Fri, 4 Apr 2014 09:03:02 +0000 (09:03 +0000)]
ARM64: add 128-bit MLA operations to the custom selection code.
Without this change, the llvm_unreachable kicked in. The code pattern
being spotted is rather non-canonical for 128-bit MLAs, but it can
happen and there's no point in generating sub-optimal code for it just
because it looks odd.
Should fix PR19332.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205615
91177308-0d34-0410-b5e6-
96231b3b80d8
Stepan Dyatkovskiy [Fri, 4 Apr 2014 08:14:13 +0000 (08:14 +0000)]
Fixed register class in STRD instruction for Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205612
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 4 Apr 2014 05:16:06 +0000 (05:16 +0000)]
Make consistent use of MCPhysReg instead of uint16_t throughout the tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205610
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Fri, 4 Apr 2014 02:14:38 +0000 (02:14 +0000)]
Fix spelling. Sigh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205605
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Fri, 4 Apr 2014 02:11:03 +0000 (02:11 +0000)]
ARM: Range based for-loop over block predecessors.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205604
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Fri, 4 Apr 2014 02:10:59 +0000 (02:10 +0000)]
Add iterator_ranges for block pred/succ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205603
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Fri, 4 Apr 2014 02:10:55 +0000 (02:10 +0000)]
ARM: Use range-based for loops in frame lowering.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205602
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Fri, 4 Apr 2014 02:05:21 +0000 (02:05 +0000)]
[RegAllocGreedy][Last Chance Recoloring] Emit diagnostics when last chance
recoloring cut-offs are encountered and register allocation failed.
This is related to PR18747
Patch by MAYUR PANDEY <mayur.p@samsung.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205601
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Fri, 4 Apr 2014 02:02:49 +0000 (02:02 +0000)]
Revert r205599, the commit was not intended to have so many changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205600
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Fri, 4 Apr 2014 01:58:57 +0000 (01:58 +0000)]
[RegAllocGreedy][Last Chance Recoloring] Emit diagnostics when last chance
recoloring cut-offs are hit.
This is related to PR18747.
Patch by MAYUR PANDEY <mayur.p@samsung.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205599
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Fri, 4 Apr 2014 01:19:56 +0000 (01:19 +0000)]
ARM: fix test case missed in previous roundup
This should hopefully bring the last MSVC buildbot back to green!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205596
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Fri, 4 Apr 2014 01:19:54 +0000 (01:19 +0000)]
MIPS: remove vim swap file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205595
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Fri, 4 Apr 2014 00:31:12 +0000 (00:31 +0000)]
Add an assert that this is only used with .o files.
I am not sure how to get a relocation in a .dylib, but this function would
return the wrong value if passed one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205592
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Thu, 3 Apr 2014 23:54:35 +0000 (23:54 +0000)]
Implement getRelocationAddress for MachO and ET_REL elf files.
With that, fix the symbolizer to work with any ELF file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205588
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Thu, 3 Apr 2014 23:51:28 +0000 (23:51 +0000)]
Implement macho relocation iterators with section number + relocation number.
This will make it possible to implement getRelocationAddress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205587
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Thu, 3 Apr 2014 23:47:24 +0000 (23:47 +0000)]
ARM: yet another round of ARM test clean ups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205586
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Thu, 3 Apr 2014 23:43:26 +0000 (23:43 +0000)]
Tidy up. Space before ':' in range-based for loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205585
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Thu, 3 Apr 2014 23:43:22 +0000 (23:43 +0000)]
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205584
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Thu, 3 Apr 2014 23:43:18 +0000 (23:43 +0000)]
Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205583
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Thu, 3 Apr 2014 23:43:12 +0000 (23:43 +0000)]
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205582
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Thu, 3 Apr 2014 23:20:02 +0000 (23:20 +0000)]
Fix llvm-objdump crash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205581
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Thu, 3 Apr 2014 22:42:22 +0000 (22:42 +0000)]
Remove section_rel_empty. Just compare begin() and end() instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205577
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Thu, 3 Apr 2014 21:48:41 +0000 (21:48 +0000)]
Reuse existing variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205572
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Bendersky [Thu, 3 Apr 2014 21:18:25 +0000 (21:18 +0000)]
Optimize away unnecessary address casts.
Removes unnecessary casts from non-generic address spaces to the generic address
space for certain code patterns.
Patch by Jingyue Wu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205571
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 3 Apr 2014 20:51:08 +0000 (20:51 +0000)]
[ARM64] Teach the ARM64DeadRegisterDefinition pass to respect implicit-defs.
When rematerializing through truncates, the coalescer may produce instructions
with dead defs, but live implicit-defs of subregs:
E.g.
%X1<def,dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32
These instructions are live, and their definitions should not be rewritten.
Fixes <rdar://problem/
16492408>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205565
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Thu, 3 Apr 2014 20:40:37 +0000 (20:40 +0000)]
unconditional-branch.ll is broken for targeting x86_64-cygming. Add an explicit triple for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205563
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Thu, 3 Apr 2014 20:19:29 +0000 (20:19 +0000)]
R600: Correct opcode for BFE_INT
Acording to AMD documentation, the correct opcode for
BFE_INT is 0x5, not 0x4
Fixes Arithm/Absdiff.Mat/3 OpenCV test
Patch by: Bruno Jiménez
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205562
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Thu, 3 Apr 2014 20:19:27 +0000 (20:19 +0000)]
R600/SI: Lower 64-bit immediates using REG_SEQUENCE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205561
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Thu, 3 Apr 2014 20:08:02 +0000 (20:08 +0000)]
Revert r205551, "Attempt to XFAIL this on mingw and cygwin hosts." It didn't fail on cygming.
That said, it emits errors to the stderr (with exit(0));
error: failed to compute relocation: IMAGE_REL_I386_SECREL
error: failed to compute relocation: IMAGE_REL_I386_SECREL
error: failed to compute relocation: IMAGE_REL_I386_SECREL
error: failed to compute relocation: IMAGE_REL_I386_SECREL
error: failed to compute relocation: IMAGE_REL_I386_SECREL
error: failed to compute relocation: IMAGE_REL_I386_DIR32
error: failed to compute relocation: IMAGE_REL_I386_SECREL
error: failed to compute relocation: IMAGE_REL_I386_DIR32
error: failed to compute relocation: IMAGE_REL_I386_SECREL
error: failed to compute relocation: IMAGE_REL_I386_SECREL
error: failed to compute relocation: IMAGE_REL_I386_DIR32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205560
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Thu, 3 Apr 2014 20:07:51 +0000 (20:07 +0000)]
llvm/test/CodeGen/X86/peephole-multiple-folds.ll: Relax expressions to satisfy win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205559
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 3 Apr 2014 18:23:52 +0000 (18:23 +0000)]
Attempt to XFAIL this on mingw and cygwin hosts. The line table on
these is very much off and is more than just the branch
from this bug incorrect:
Address Line Column File ISA Discriminator Flags
------------------ ------ ------ ------ --- ------------- -------------
0x30830a0100000002 3 0 1 0 0 is_stmt
0x30830a0100000008 3 0 1 0 0 is_stmt end_sequence
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205551
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Bendersky [Thu, 3 Apr 2014 17:51:58 +0000 (17:51 +0000)]
Fix PR19270 - type mismatch caused by invalid optimization.
Patch by Jingyue Wu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205547
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 3 Apr 2014 17:40:08 +0000 (17:40 +0000)]
Loosen up check so that we can pass on platforms that generate
slightly more verbose than needed line tables, e.g.:
Address Line Column File ISA Discriminator Flags
------------------ ------ ------ ------ --- ------------- -------------
0x0000000000000000 1 0 1 0 0 is_stmt
0x0000000000000000 1 0 1 0 0 is_stmt prologue_end
0x0000000000000010 2 0 1 0 0 is_stmt
0x0000000000000018 4 0 1 0 0 is_stmt
these should probably be looked at, but it isn't affecting the correctness
of the testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205546
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Thu, 3 Apr 2014 17:35:22 +0000 (17:35 +0000)]
ARM: update even more tests
More updating of tests to be explicit about the target triple rather than
relying on the default target triple supporting ARM mode.
Indicate to lit that object emission is not yet available for Windows on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205545
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Thu, 3 Apr 2014 16:29:11 +0000 (16:29 +0000)]
ArrayRef: use std::vector::data() now that we are building in C++11 mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205542
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Thu, 3 Apr 2014 16:01:44 +0000 (16:01 +0000)]
ARM: fixup more tests to specify the target more explicitly
This changes the tests that were targeting ARM EABI to explicitly specify the
environment rather than relying on the default. This breaks with the new
Windows on ARM support when running the tests on Windows where the default
environment is no longer EABI.
Take the opportunity to avoid a pointless redirect (helps when trying to debug
with providing a command line invocation which can be copy and pasted) and
removing a few greps in favour of FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Thu, 3 Apr 2014 15:10:35 +0000 (15:10 +0000)]
ARM: tell LLVM about zext properties of ldrexb/ldrexh
Implementing this via ComputeMaskedBits has two advantages:
+ It actually works. DAGISel doesn't deal with the chains properly
in the previous pattern-based solution, so they never trigger.
+ The information can be used in other DAG combines, as well as the
trivial "get rid of truncs". For example if the trunc is in a
different basic block.
rdar://problem/
16227836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205540
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Thu, 3 Apr 2014 14:14:22 +0000 (14:14 +0000)]
[mips] Add negative tests confirm that supported ISA's don't allow instructions added in later ISA's
Summary:
test/MC/Mips/<isa1>/invalid-<isa2>.s
Test that <isa1> does not support <isa2>'s instructions.
test/MC/Mips/<isa1>/invalid-<isa2>-xfail.s
Things that should be invalid but currently aren't. Will XPASS if any
become invalid.
Reviewers: matheusalmeida
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205538
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Thu, 3 Apr 2014 13:21:51 +0000 (13:21 +0000)]
[mips] Implement ehb, ssnop, and pause in assembler
Summary: Add negative tests for pause
Reviewers: matheusalmeida
Reviewed By: matheusalmeida
Differential Revision: http://llvm-reviews.chandlerc.com/D3246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205537
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Thu, 3 Apr 2014 13:06:54 +0000 (13:06 +0000)]
ARM: skip cmpxchg failure barrier if ordering is monotonic.
The terminal barrier of a cmpxchg expansion will be either Acquire or
SequentiallyConsistent. In either case it can be skipped if the
operation has Monotonic requirements on failure.
rdar://problem/
15996804
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205535
91177308-0d34-0410-b5e6-
96231b3b80d8
Zoran Jovanovic [Thu, 3 Apr 2014 12:47:34 +0000 (12:47 +0000)]
Implementation of 16-bit microMIPS instructions MFHI and MFLO.
Differential Revision: http://llvm-reviews.chandlerc.com/D3141
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205532
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Thu, 3 Apr 2014 12:13:36 +0000 (12:13 +0000)]
[mips] Add initial (experimental) MIPS-IV support.
Summary:
Adds the 'mips4' processor and a simple test of the ELF e_flags.
Patch by David Chisnall
His work was sponsored by: DARPA, AFRL
I made one small change to the testcase so that it uses
mips64-unknown-linux instead of mips4-unknown-linux.
This patch indirectly adds FeatureCondMov to FeatureMips64. This is ok
because it's supposed to be there anyway and it turns out that
FeatureCondMov is not a predicate of any instructions at the moment
(this is a bug that hasn't been noticed because there are no targets
without the conditional move instructions yet).
CC: theraven
Differential Revision: http://llvm-reviews.chandlerc.com/D3244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205530
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 3 Apr 2014 12:11:51 +0000 (12:11 +0000)]
Fix for PR 19261:
llc doesn't generate nodes for unconditional fall-through branches for targets
without FastISel implementation (X86 has it, but can be disabled by
"-fast-isel=false") in SelectionDAGBuilder::visitBr().
So for line 4 in the following testcase
1: void foo(int i){
2: switch(i){
3: default:
4: break;
5: }
6: return;
7: }
there is no corresponding line in .debug_line section, and a debugger
cannot set a breakpoint at line 4.
Fix this by always emitting a branch when we're not optimizing and add a
testcase to ensure that there's code on every line we'd want to break.
Patch by Daniil Fukalov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205529
91177308-0d34-0410-b5e6-
96231b3b80d8
Zoran Jovanovic [Thu, 3 Apr 2014 12:01:01 +0000 (12:01 +0000)]
MicroMIPS specific little endian fixup data byte ordering.
Differential Revision: http://llvm-reviews.chandlerc.com/D3245
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205528
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Thu, 3 Apr 2014 11:44:58 +0000 (11:44 +0000)]
ARM: expand atomic ldrex/strex loops in IR
The previous situation where ATOMIC_LOAD_WHATEVER nodes were expanded
at MachineInstr emission time had grown to be extremely large and
involved, to account for the subtly different code needed for the
various flavours (8/16/32/64 bit, cmpxchg/add/minmax).
Moving this transformation into the IR clears up the code
substantially, and makes future optimisations much easier:
1. an atomicrmw followed by using the *new* value can be more
efficient. As an IR pass, simple CSE could handle this
efficiently.
2. Making use of cmpxchg success/failure orderings only has to be done
in one (simpler) place.
3. The common "cmpxchg; did we store?" idiom can be exposed to
optimisation.
I intend to gradually improve this situation within the ARM backend
and make sure there are no hidden issues before moving the code out
into CodeGen to be shared with (at least ARM64/AArch64, though I think
PPC & Mips could benefit too).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205525
91177308-0d34-0410-b5e6-
96231b3b80d8
Stepan Dyatkovskiy [Thu, 3 Apr 2014 11:29:15 +0000 (11:29 +0000)]
PR19320:
The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP.
It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524
91177308-0d34-0410-b5e6-
96231b3b80d8
Silviu Baranga [Thu, 3 Apr 2014 10:44:27 +0000 (10:44 +0000)]
[ARM] When generating a vpaddl node the input lane type is not always the type of the
add operation since extract_vector_elt can perform an extend operation. Get the input lane
type from the vector on which we're performing the vpaddl operation on and extend or
truncate it to the output type of the original add node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205523
91177308-0d34-0410-b5e6-
96231b3b80d8
Sasa Stankovic [Thu, 3 Apr 2014 10:37:45 +0000 (10:37 +0000)]
[mips] Extend MipsMCExpr class to handle %higher(sym1 - sym2 + const) and
%highest(sym1 - sym2 + const) relocations. Remove "ABS_" from VK_Mips_HI
and VK_Mips_LO enums in MipsMCExpr, to be consistent with VK_Mips_HIGHER
and VK_Mips_HIGHEST.
This change also deletes test file test/MC/Mips/higher_highest.ll and moves
its CHECK's to the new test file test/MC/Mips/higher-highest-addressing.s.
The deleted file tests that R_MIPS_HIGHER and R_MIPS_HIGHEST relocations are
emitted in the .o file. Since it uses -force-mips-long-branch option, it was
created when MipsLongBranch's implementation was emitting R_MIPS_HIGHER and
R_MIPS_HIGHEST relocations in the .o file. It was disabled when MipsLongBranch
started to directly calculate offsets.
Differential Revision: http://llvm-reviews.chandlerc.com/D3230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205522
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Thu, 3 Apr 2014 09:36:05 +0000 (09:36 +0000)]
ARM64: add regression test for r205519.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205520
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Thu, 3 Apr 2014 09:26:16 +0000 (09:26 +0000)]
ARM64: always use i64 for the RHS of shift operations
Switching between i32 and i64 based on the LHS type is a good idea in
theory, but pre-legalisation uses i64 regardless of our choice,
leading to potential ISel errors.
Should fix PR19294.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205519
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Thu, 3 Apr 2014 08:45:16 +0000 (08:45 +0000)]
ARM: Use __STACK_LIMIT symbol for segmented stacks
We cannot use STACK_LIMIT, as it is not reserved for the compiler
by the C spec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205516
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Thu, 3 Apr 2014 07:08:21 +0000 (07:08 +0000)]
Stack map docs. Remove some stray markup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205515
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Thu, 3 Apr 2014 07:06:13 +0000 (07:06 +0000)]
ARM64: don't generate __sincos_stret calls unless on MachO
This should fix PR19314.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205514
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrew Trick [Thu, 3 Apr 2014 07:03:28 +0000 (07:03 +0000)]
Minor update to the stack map documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205513
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Thu, 3 Apr 2014 06:28:20 +0000 (06:28 +0000)]
DebugInfo: Use a 64 bit type for the subrange
While we were encoding 64 bit values (data8) in the subrange itself,
using a 32 bit type for the subrange was still confusing the gdb. Oh,
and make it unsigned too.
As the comment points out, this could be pushed into the frontend so
that it would be 32 or 64 bit as appropriate, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205512
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 3 Apr 2014 05:03:20 +0000 (05:03 +0000)]
[CodeGen] Fix peephole optimizer bug introduced in r205481. Fixes PR19318.
I should have read that comment a little more carefully. ;)
Regression test in the works, committing in the mean time to un-break people.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205511
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Thu, 3 Apr 2014 03:57:03 +0000 (03:57 +0000)]
Handle getting UnknownAddressOrSize or section_end().
These should probably be error conditions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205509
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Thu, 3 Apr 2014 03:13:33 +0000 (03:13 +0000)]
Implement get getSymbolFileOffset with getSymbolAddress.
This has the following advantages:
* Less code.
* The old ELF implementation was wrong for non-relocatable objects.
* The old ELF implementation (and I think MachO) was wrong for thumb.
No current testcase since this is only used from MCJIT and it only uses
relocatable objects and I don't think it supports thumb yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205508
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Thu, 3 Apr 2014 02:32:47 +0000 (02:32 +0000)]
Remove getSymbolValue.
All existing users explicitly ask for an address or a file offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205503
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Thu, 3 Apr 2014 02:27:00 +0000 (02:27 +0000)]
Add support for the R_ARM_ABS32 relocation.
This should bring the arm buildbots back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205502
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Thu, 3 Apr 2014 02:20:43 +0000 (02:20 +0000)]
Only clear the thumb bit from function addresses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205500
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Thu, 3 Apr 2014 01:51:15 +0000 (01:51 +0000)]
Simplify ELFObjectFile<ELFT>::getSymbolAddress.
In particular, we only need to fetch the section if this is a relocatable
object.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205499
91177308-0d34-0410-b5e6-
96231b3b80d8
Juergen Ributzka [Thu, 3 Apr 2014 01:38:47 +0000 (01:38 +0000)]
Revert "[Constant Hoisting] Lazily compute the idom and cache the result."
This code is no longer usefull, because we only compute and use the
IDom once. There is no benefit in caching it anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205498
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Thu, 3 Apr 2014 00:53:59 +0000 (00:53 +0000)]
Account for scalarization costs in BasicTTI::getMemoryOpCost for extending vector loads
When a vector type legalizes to a larger vector type, and the target does not
support the associated extending load (or truncating store), then legalization
will scalarize the load (or store) resulting in an associated scalarization
cost. BasicTTI::getMemoryOpCost needs to account for this.
Between this, and r205487, PowerPC on the P7 with VSX enabled shows:
MultiSource/Benchmarks/PAQ8p/paq8p: 43% speedup
SingleSource/Benchmarks/BenchmarkGame/puzzle: 51% speedup
SingleSource/UnitTests/Vectorizer/gcc-loops 28% speedup
(some of these are new; some of these, such as PAQ8p, just reverse regressions
that VSX support would trigger)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205495
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Thu, 3 Apr 2014 00:19:35 +0000 (00:19 +0000)]
Revert "Fix a nomenclature error in llvm-nm."
This reverts commit r205479.
It turns out that nm does use addresses, it is just that every reasonable
relocatable ELF object has sections with address 0. I have no idea if those
exist in reality, but it at least it shows that llvm-nm should use the name
address.
The added test was includes an unusual .o file with non 0 section addresses. I
created it by hacking ELFObjectWriter.cpp.
Really sorry for the churn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205493
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Trieu [Thu, 3 Apr 2014 00:14:18 +0000 (00:14 +0000)]
Fix test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205492
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Wed, 2 Apr 2014 23:57:49 +0000 (23:57 +0000)]
[X86] As per suggestion from Craig Topper and Hal Finkel, override
TargetInstrInfo::findCommutedOpIndices to enable VFMA*231 commutation, rather
than abusing commuteInstruction.
Thanks very much for the suggestion guys!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205489
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Wed, 2 Apr 2014 23:18:54 +0000 (23:18 +0000)]
Fix multi-register costs in BasicTTI::getCastInstrCost
For an cast (extension, etc.), the currently logic predicts a low cost if the
associated operation (keyed on the destination type) is legal (or promoted).
This is not true when the number of values required to legalize the type is
changing. For example, <8 x i16> being sign extended by <8 x i32> is not
generically cheap on PPC with VSX, even though sign extension to v4i32 is
legal, because two output v4i32 values are required compared to the single
v8i16 input value, and without custom logic in the target, this conversion will
scalarize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205487
91177308-0d34-0410-b5e6-
96231b3b80d8
Juergen Ributzka [Wed, 2 Apr 2014 23:06:22 +0000 (23:06 +0000)]
Add test case for [Constant Hoisting] Erase dead cast instructions (r204538).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205484
91177308-0d34-0410-b5e6-
96231b3b80d8
Renato Golin [Wed, 2 Apr 2014 23:03:28 +0000 (23:03 +0000)]
ARM Linux support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205483
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Wed, 2 Apr 2014 22:59:58 +0000 (22:59 +0000)]
[CodeGen] Teach the peephole optimizer to remember (and exploit) all folding
opportunities in the current basic block, rather than just the last one seen.
<rdar://problem/
16478629>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205481
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Wed, 2 Apr 2014 22:52:46 +0000 (22:52 +0000)]
Fix a nomenclature error in llvm-nm.
What llvm-nm prints depends on the file format. On ELF for example, if the
file is relocatable, it prints offsets. If it is not, it prints addresses.
Since it doesn't really need to care what it is that it is printing, use the
generic term value.
Fix or implement getSymbolValue to keep llvm-nm working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205479
91177308-0d34-0410-b5e6-
96231b3b80d8
Pete Cooper [Wed, 2 Apr 2014 22:49:58 +0000 (22:49 +0000)]
Add ability to disable building LLVM utils
Patch by Chris Bieneman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205478
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Wed, 2 Apr 2014 22:43:49 +0000 (22:43 +0000)]
[PowerPC] Make PPCTTI::getMemoryOpCost call BasicTTI::getMemoryOpCost
PPCTTI::getMemoryOpCost will now make use of BasicTTI::getMemoryOpCost to
calculate the base cost of the memory access, and then adjust on top of that.
There is no functionality change from this modification, but it will become
important so that PPCTTI can take advantage of scalarization information for which
BasicTTI::getMemoryOpCost will account in the near future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205476
91177308-0d34-0410-b5e6-
96231b3b80d8
Juergen Ributzka [Wed, 2 Apr 2014 22:21:01 +0000 (22:21 +0000)]
Add comments and test case for [DAG] Keep the opaque constant flag when performing unary constant folding operations (r204737).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205474
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Wed, 2 Apr 2014 22:17:30 +0000 (22:17 +0000)]
typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205473
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Wed, 2 Apr 2014 22:06:16 +0000 (22:06 +0000)]
[X86] Make the VFMA*231 variants commutable and relax the alignment restrictions
on FMA3 memory operands. FMA3 instructions are VEX encoded, so they can load
from unaligned memory.
Testcase to follow, along with related patch.
<rdar://problem/
16478629>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205472
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan P. N. Exon Smith [Wed, 2 Apr 2014 22:05:57 +0000 (22:05 +0000)]
Revert "Reapply "LTO: add API to set strategy for -internalize""
This reverts commit r199244.
Conflicts:
include/llvm-c/lto.h
include/llvm/LTO/LTOCodeGenerator.h
lib/LTO/LTOCodeGenerator.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205471
91177308-0d34-0410-b5e6-
96231b3b80d8
Juergen Ributzka [Wed, 2 Apr 2014 21:45:36 +0000 (21:45 +0000)]
Add comments and test case for [X86TTI] Make constant base pointers for GetElementPtr opaque (r204739).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205468
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Wed, 2 Apr 2014 21:22:03 +0000 (21:22 +0000)]
ARM: fixup tests to specify the target more explicitly
This changes the tests that were targeting ARM EABI to explicitly specify the
environment rather than relying on the default. This breaks with the new
Windows on ARM support when running the tests on Windows where the default
environment is no longer EABI.
Take the opportunity to avoid a pointless redirect (helps when trying to debug
with providing a command line invocation which can be copy and pasted) and
removing a few greps in favour of FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205465
91177308-0d34-0410-b5e6-
96231b3b80d8
Juergen Ributzka [Wed, 2 Apr 2014 21:15:36 +0000 (21:15 +0000)]
Add test case for [Stackmaps][X86TTI] Fix think-o in getIntImmCost calculation (r204738).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205464
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Wed, 2 Apr 2014 20:32:05 +0000 (20:32 +0000)]
ARM: update subtarget information for Windows on ARM
Update the subtarget information for Windows on ARM. This enables using the MC
layer to target Windows on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205459
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 2 Apr 2014 20:21:22 +0000 (20:21 +0000)]
Make a few more range-based loops use explicit types.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205458
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Wed, 2 Apr 2014 20:00:33 +0000 (20:00 +0000)]
Add back an assert that was lost in the ELFObjectFile.h split.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205456
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Wed, 2 Apr 2014 19:53:29 +0000 (19:53 +0000)]
TargetLibraryInfo: Disable memcpy and memset on R600
There are no implementations of these for R600.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205455
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 2 Apr 2014 19:28:18 +0000 (19:28 +0000)]
Simplify resolveFrameIndex() signature.
Just pass a MachineInstr reference rather than an MBB iterator.
Creating a MachineInstr& is the first thing every implementation did
anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205453
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 2 Apr 2014 19:28:13 +0000 (19:28 +0000)]
ARM: cortex-m0 doesn't support unaligned memory access.
Unlike other v6+ processors, cortex-m0 never supports unaligned accesses.
From the v6m ARM ARM:
"A3.2 Alignment support: ARMv6-M always generates a fault when an unaligned
access occurs."
rdar://
16491560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205452
91177308-0d34-0410-b5e6-
96231b3b80d8
Jim Grosbach [Wed, 2 Apr 2014 19:28:08 +0000 (19:28 +0000)]
Make some range based loop types more explicit.
No functional change, but more readable code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205451
91177308-0d34-0410-b5e6-
96231b3b80d8