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Sanjay Patel [Fri, 24 Feb 2017 21:47:44 +0000 (21:47 +0000)]
[utils] allow auto-generation of checks for thumb triples
If there's some reason not to do this, feel free to revert and/or fix, but
for the cases I'm looking at, the script appears to do fine for these targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296181
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Evgeniy Stepanov [Fri, 24 Feb 2017 21:44:58 +0000 (21:44 +0000)]
Disallow redefinition of section symbols.
Differential Revision: https://reviews.llvm.org/D30235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296180
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Evgeniy Stepanov [Fri, 24 Feb 2017 21:44:52 +0000 (21:44 +0000)]
Initialize MCContext::InlineSrcMgr in the constructor.
Found with ASan (and a local source change) on test/CodeGen/XCore/section-name.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296179
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Sanjay Patel [Fri, 24 Feb 2017 21:36:34 +0000 (21:36 +0000)]
[ARM] add tests for alternate forms of select-of-constants; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296178
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Dan Gohman [Fri, 24 Feb 2017 21:21:44 +0000 (21:21 +0000)]
[WebAssembly] Define an initial set of relocation types for Wasm.
This set will likely evolve, along with the Wasm linking ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296177
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Tim Northover [Fri, 24 Feb 2017 21:21:38 +0000 (21:21 +0000)]
GlobalISel: check for CImm rather than Imm on G_CONSTANTs.
All G_CONSTANTS created by the MachineIRBuilder have an operand of type CImm
(i.e. a ConstantInt), so that's what the selector needs to look for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296176
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Sanjay Patel [Fri, 24 Feb 2017 21:19:09 +0000 (21:19 +0000)]
[ARM] auto-generate complete checks; NFC
The affected test may change with a patch I'm looking at for DAGCombiner,
so I want to make sure it's not a regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296175
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Dan Gohman [Fri, 24 Feb 2017 21:05:35 +0000 (21:05 +0000)]
[WebAssembly] Handle f16 in fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296172
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Xin Tong [Fri, 24 Feb 2017 20:59:26 +0000 (20:59 +0000)]
Fix Indentation. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296169
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Lang Hames [Fri, 24 Feb 2017 20:56:43 +0000 (20:56 +0000)]
[Orc][RPC] Accept both const char* and char* arguments for string serialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296168
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Eli Friedman [Fri, 24 Feb 2017 20:51:36 +0000 (20:51 +0000)]
[CodeGenPrepare] Make -addr-sink-using-gep work with address spaces.
When we construct addressing modes, we use isNoopAddrSpaceCast to ignore
addrspacecast instructions. Make sure we insert the correct addrspacecast
when we reconstruct the addressing mode.
Differential Revision: https://reviews.llvm.org/D30114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296167
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Yaxun Liu [Fri, 24 Feb 2017 20:27:25 +0000 (20:27 +0000)]
[InstCombine] Fix bug in pointer replacement
This optimisation was crashing when there was a chain of more than one bitcast
instruction to replace, as a result of the changes in D27283.
Patch by James Price.
Differential Revision: https://reviews.llvm.org/D30347
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296163
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Davide Italiano [Fri, 24 Feb 2017 18:48:10 +0000 (18:48 +0000)]
[Target/MIPS] Kill dead code, no functional change intended.
Hopefully placates gcc with -Werror.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296153
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Michael Kuperstein [Fri, 24 Feb 2017 18:41:32 +0000 (18:41 +0000)]
[CGP] Split some critical edges coming out of indirect branches
Splitting critical edges when one of the source edges is an indirectbr
is hard in general (because it requires changing the memory the indirectbr
reads). But if a block only has a single indirectbr predecessor (which is
the common case), we can simulate splitting that edge by splitting
the destination block, and retargeting the *direct* branches.
This is motivated by the use of computed gotos in python 2.7: PyEval_EvalFrame()
ends up using an indirect branch with ~100 successors, and passing a constant to
each of those. Since MachineSink can't break indirect critical edges on demand
(and doing this in MIR doesn't look feasible), this causes us to emit about ~100
defs of registers containing constants, which we in the predecessor block, where
only one of those constants is used in each successor. So, at each computed goto,
we needlessly spill about a 100 constants to stack. The end result is that a
clang-compiled python interpreter can be about ~2.5x slower on a simple python
reduction loop than a gcc-compiled interpreter.
Differential Revision: https://reviews.llvm.org/D29916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296149
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Simon Pilgrim [Fri, 24 Feb 2017 18:31:04 +0000 (18:31 +0000)]
Revert: r296141 [APInt] Add APInt::extractBits() method to extract APInt subrange
The current pattern for extract bits in range is typically:
Mask.lshr(BitOffset).trunc(SubSizeInBits);
Which can be particularly slow for large APInts (MaskSizeInBits > 64) as they require the allocation of memory for the temporary variable.
This is another of the compile time issues identified in PR32037 (see also D30265).
This patch adds the APInt::extractBits() helper method which avoids the temporary memory allocation.
Differential Revision: https://reviews.llvm.org/D30336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296147
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Matthew Simpson [Fri, 24 Feb 2017 18:20:12 +0000 (18:20 +0000)]
[LV] Merge floating-point and integer induction widening code
This patch merges the existing floating-point induction variable widening code
into the integer induction variable widening code, creating a single set of
functions for both kinds of inductions. The primary motivation for doing this
is to enable vector phi node creation for floating-point induction variables.
Differential Revision: https://reviews.llvm.org/D30211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296145
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Nemanja Ivanovic [Fri, 24 Feb 2017 18:16:06 +0000 (18:16 +0000)]
[PowerPC] Use subfic instruction for subtract from immediate
Provide a 64-bit pattern to use SUBFIC for subtracting from a 16-bit immediate.
The corresponding pattern already exists for 32-bit integers.
Committing on behalf of Hiroshi Inoue.
Differential Revision: https://reviews.llvm.org/D29387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296144
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Nemanja Ivanovic [Fri, 24 Feb 2017 18:03:16 +0000 (18:03 +0000)]
[PowerPC] Use rldicr instruction for AND with an immediate if possible
Emit clrrdi (extended mnemonic for rldicr) for AND-ing with masks that
clear bits from the right hand size.
Committing on behalf of Hiroshi Inoue.
Differential Revision: https://reviews.llvm.org/D29388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296143
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Simon Pilgrim [Fri, 24 Feb 2017 17:46:18 +0000 (17:46 +0000)]
[APInt] Add APInt::extractBits() method to extract APInt subrange
The current pattern for extract bits in range is typically:
Mask.lshr(BitOffset).trunc(SubSizeInBits);
Which can be particularly slow for large APInts (MaskSizeInBits > 64) as they require the allocation of memory for the temporary variable.
This is another of the compile time issues identified in PR32037 (see also D30265).
This patch adds the APInt::extractBits() helper method which avoids the temporary memory allocation.
Differential Revision: https://reviews.llvm.org/D30336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296141
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Simon Pilgrim [Fri, 24 Feb 2017 17:20:27 +0000 (17:20 +0000)]
Fixed IntOperandMatcher::emitCxxPredicateExpr arguments
Extra const in the StringRef argument meant that MSVC complained about it not correctly overriding from OperandPredicateMatcher::emitCxxPredicateExpr (which didn't have the const)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296138
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Sanjay Patel [Fri, 24 Feb 2017 17:17:33 +0000 (17:17 +0000)]
[DAGCombiner] add missing folds for scalar select of {-1,0,1}
The motivation for filling out these select-of-constants cases goes back to D24480,
where we discussed removing an IR fold from add(zext) --> select. And that goes back to:
https://reviews.llvm.org/rL75531
https://reviews.llvm.org/rL159230
The idea is that we should always canonicalize patterns like this to a select-of-constants
in IR because that's the smallest IR and the best for value tracking. Note that we currently
do the opposite in some cases (like the cases in *this* patch). Ie, the proposed folds in
this patch already exist in InstCombine today:
https://github.com/llvm-mirror/llvm/blob/master/lib/Transforms/InstCombine/InstCombineSelect.cpp#L1151
As this patch shows, most targets generate better machine code for simple ext/add/not ops
rather than a select of constants. So the follow-up steps to make this less of a patchwork
of special-case folds and missing IR canonicalization:
1. Have DAGCombiner convert any select of constants into ext/add/not ops.
2 Have InstCombine canonicalize in the other direction (create more selects).
Differential Revision: https://reviews.llvm.org/D30180
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296137
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Simon Dardis [Fri, 24 Feb 2017 16:32:18 +0000 (16:32 +0000)]
Recommit "[mips] Fix atomic compare and swap at O0."
This time with the missing files.
Similar to PR/25526, fast-regalloc introduces spills at the end of basic
blocks. When this occurs in between an ll and sc, the store can cause the
atomic sequence to fail.
This patch fixes the issue by introducing more pseudos to represent atomic
operations and moving their lowering to after the expansion of postRA
pseudos.
This resolves PR/32020.
Thanks to James Cowgill for reporting the issue!
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D30257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296134
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Simon Dardis [Fri, 24 Feb 2017 16:30:27 +0000 (16:30 +0000)]
Revert "[mips] Fix atomic compare and swap at O0."
This reverts r296132. I forgot to include the tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296133
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Simon Dardis [Fri, 24 Feb 2017 16:27:45 +0000 (16:27 +0000)]
[mips] Fix atomic compare and swap at O0.
Similar to PR/25526, fast-regalloc introduces spills at the end of basic
blocks. When this occurs in between an ll and sc, the store can cause the
atomic sequence to fail.
This patch fixes the issue by introducing more pseudos to represent atomic
operations and moving their lowering to after the expansion of postRA
pseudos.
This resolves PR/32020.
Thanks to James Cowgill for reporting the issue!
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D30257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296132
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Daniel Sanders [Fri, 24 Feb 2017 15:43:30 +0000 (15:43 +0000)]
[globalisel] Decouple src pattern operands from dst pattern operands.
Summary:
This isn't testable for AArch64 by itself so this patch also adds
support for constant immediates in the pattern and physical
register uses in the result.
The new IntOperandMatcher matches the constant in patterns such as
'(set $rd:GPR32, (G_XOR $rs:GPR32, -1))'. It's always safe to fold
immediates into an instruction so this is the first rule that will match
across multiple BB's.
The Renderer hierarchy is responsible for adding operands to the result
instruction. Renderers can copy operands (CopyRenderer) or add physical
registers (in particular %wzr and %xzr) to the result instruction
in any order (OperandMatchers now import the operand names from
SelectionDAG to allow renderers to access any operand). This allows us to
emit the result instruction for:
%1 = G_XOR %0, -1 --> %1 = ORNWrr %wzr, %0
%1 = G_XOR -1, %0 --> %1 = ORNWrr %wzr, %0
although the latter is untested since the matcher/importer has not been
taught about commutativity yet.
Added BuildMIAction which can build new instructions and mutate them where
possible. W.r.t the mutation aspect, MatchActions are now told the name of
an instruction they can recycle and BuildMIAction will emit mutation code
when the renderers are appropriate. They are appropriate when all operands
are rendered using CopyRenderer and the indices are the same as the matcher.
This currently assumes that all operands have at least one matcher.
Finally, this change also fixes a crash in
AArch64InstructionSelector::select() caused by an immediate operand
passing isImm() rather than isCImm(). This was uncovered by the other
changes and was detected by existing tests.
Depends on D29711
Reviewers: t.p.northover, ab, qcolombet, rovka, aditya_nandakumar, javed.absar
Reviewed By: rovka
Subscribers: aemerson, dberris, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D29712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296131
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Simon Pilgrim [Fri, 24 Feb 2017 15:35:52 +0000 (15:35 +0000)]
[X86][SSE] Target shuffle combine can try to combine up to 16 vectors
Noticed while profiling PR32037, the target shuffle ops were being stored in SmallVector<*,8> types but the combiner could store as many as 16 ops at maximum depth (2 per depth).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296130
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Sanjay Patel [Fri, 24 Feb 2017 15:18:42 +0000 (15:18 +0000)]
[InstCombine] don't try SimplifyDemandedInstructionBits from zext/sext because it's slow and unnecessary
This one seems more obvious than D30270 that it can't make improvements because an extension always needs
all of the incoming bits. There's one specific transform in SimplifyDemandedInstructionBits of converting
a sext to a zext when the sign-bit is known zero, but that is handled explicitly in visitSext() with
ComputeSignBit().
Like D30270, there are no IR differences (other than instruction names) for the case in PR32037:
https://bugs.llvm.org//show_bug.cgi?id=32037
...and no regression test differences.
Zext/sext are a smaller part of the profile, but this still appears to shave off another 0.5% or so from
'opt -O2'.
Differential Revision: https://reviews.llvm.org/D30280
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296129
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Sanjay Patel [Fri, 24 Feb 2017 15:09:59 +0000 (15:09 +0000)]
[x86] use DAG.getAllOnesConstant(); NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296128
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Daniel Sanders [Fri, 24 Feb 2017 14:53:35 +0000 (14:53 +0000)]
Fix missing call to base class constructor in r296121.
The 'Kind' member used in RTTI for InstructionPredicateMatcher was not
initialized but went undetected since I always ended up with the correct value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296126
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Simon Dardis [Fri, 24 Feb 2017 14:34:32 +0000 (14:34 +0000)]
[mips] Handle 64 bit immediate in and/or/xor pseudo instructions on mips64
Previously LLVM was assuming 32-bit signed immediates which results in and with
a bitmask that has bit 31 set to incorrectly include bits 63-32 in the result.
After applying this patch I can now compile all of the FreeBSD mips assembly
code with clang.
This issue also affects the nor, slt and sltu macros and I will fix those in a
separate review.
Patch By: Alexander Richardson
Commit message reformatted by sdardis.
Reviewers: atanasyan, theraven, sdardis
Differential Revision: https://reviews.llvm.org/D30298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296125
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Diana Picus [Fri, 24 Feb 2017 14:01:27 +0000 (14:01 +0000)]
[ARM] GlobalISel: Select G_STORE
Same as selecting G_LOAD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296122
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Daniel Sanders [Fri, 24 Feb 2017 13:58:11 +0000 (13:58 +0000)]
[globalisel] Sort RuleMatchers by priority.
Summary:
This makes more important rules have priority over less important rules.
For example, '%a = G_ADD $b:s64, $c:s64' has priority over
'%a = G_ADD $b:s32, $c:s32'. Previously these rules were emitted in the
correct order by chance.
NFC in this patch but it is required to make the next patch work correctly.
Depends on D29710
Reviewers: t.p.northover, ab, qcolombet, aditya_nandakumar, rovka
Reviewed By: ab, rovka
Subscribers: javed.absar, dberris, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D29711
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296121
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Diana Picus [Fri, 24 Feb 2017 13:27:55 +0000 (13:27 +0000)]
Minor test fix
The test was using a size of 8 for loading/storing pointers. It should be 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296120
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Diana Picus [Fri, 24 Feb 2017 13:07:25 +0000 (13:07 +0000)]
[ARM] GlobalISel: Add reg bank mappings for stores
Same as the ones for loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296115
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Simon Dardis [Fri, 24 Feb 2017 12:47:41 +0000 (12:47 +0000)]
[mips][mc] Fix a crash when disassembling odd sized sections
Attempt to fix failing test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296112
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Diana Picus [Fri, 24 Feb 2017 12:47:11 +0000 (12:47 +0000)]
Fixup r296105 - only run tests on Mips
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296111
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Simon Pilgrim [Fri, 24 Feb 2017 11:31:00 +0000 (11:31 +0000)]
Fix signed/unsigned comparison warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296109
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Diana Picus [Fri, 24 Feb 2017 11:28:24 +0000 (11:28 +0000)]
[ARM] GlobalISel: Legalize stores
Allow the same types that we allow for loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296108
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Simon Dardis [Fri, 24 Feb 2017 10:51:27 +0000 (10:51 +0000)]
[mips][mc] Fix a crash when disassembling odd sized sections
Corresponding test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296106
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Simon Dardis [Fri, 24 Feb 2017 10:50:27 +0000 (10:50 +0000)]
[mips][mc] Fix a crash when disassembling odd sized sections
Make the MIPS disassembler consistent with the other targets in returning
a Size of zero when the input buffer cannot contain an instruction due
to it's size. Previously it reported the minimum instruction size when
it failed due to the buffer not being big enough for an instruction
causing llvm-objdump to crash when disassembling all sections.
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D29984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296105
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Diana Picus [Fri, 24 Feb 2017 10:35:39 +0000 (10:35 +0000)]
Revert "[ARM] GlobalISel: Legalize stores"
This reverts commit r296103 because the test broke on one of the bots. Sorry!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296104
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Diana Picus [Fri, 24 Feb 2017 10:19:23 +0000 (10:19 +0000)]
[ARM] GlobalISel: Legalize stores
Allow the same types that we allow for loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296103
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Simon Pilgrim [Fri, 24 Feb 2017 10:15:29 +0000 (10:15 +0000)]
[APInt] Add APInt::setBits() method to set all bits in range
The current pattern for setting bits in range is typically:
Mask |= APInt::getBitsSet(MaskSizeInBits, LoPos, HiPos);
Which can be particularly slow for large APInts (MaskSizeInBits > 64) as they require the allocation memory for the temporary variable.
This is one of the key compile time issues identified in PR32037.
This patch adds the APInt::setBits() helper method which avoids the temporary memory allocation completely, this first implementation uses setBit() internally instead but already significantly reduces the regression in PR32037 (~10% drop). Additional optimization may be possible.
I investigated whether there is need for APInt::clearBits() and APInt::flipBits() equivalents but haven't seen these patterns to be particularly common, but reusing the code would be trivial.
Differential Revision: https://reviews.llvm.org/D30265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296102
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Justin Bogner [Fri, 24 Feb 2017 07:42:35 +0000 (07:42 +0000)]
Add missing initialization for MachineOptimizationRemarkEmitter
This was missed in r293110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296096
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Dan Gohman [Fri, 24 Feb 2017 07:33:55 +0000 (07:33 +0000)]
[WebAssembly] Add a README.txt entry for mergeable sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296095
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Craig Topper [Fri, 24 Feb 2017 07:21:10 +0000 (07:21 +0000)]
[AVX-512] Separate the fadd/fsub/fmul/fdiv/fmax/fmin with rounding mode ISD opcodes into separate packed and scalar opcodes. This is more consistent with the rest of the ISD opcodes. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296094
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Craig Topper [Fri, 24 Feb 2017 06:38:24 +0000 (06:38 +0000)]
[ExecutionDepsFix] Use range-based for loop. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296093
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Craig Topper [Fri, 24 Feb 2017 05:35:07 +0000 (05:35 +0000)]
[IR][X86] Fix llvm version number in comments in AutoUpgrade. Forgot the next release is 5.0 not 4.1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296092
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Craig Topper [Fri, 24 Feb 2017 05:35:04 +0000 (05:35 +0000)]
[AVX-512] Remove lzcnt intrinsics and autoupgrade them to generic ctlz intrinsics with select.
Clang has been emitting cltz intrinsics for a while now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296091
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Craig Topper [Fri, 24 Feb 2017 05:34:59 +0000 (05:34 +0000)]
[AVX-512] Move lzcnt and conflict intrinsic tests to avx512cd intrinsic test file since that's their feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296090
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Craig Topper [Fri, 24 Feb 2017 05:34:57 +0000 (05:34 +0000)]
[AVX-512] Use update_llc_test_checks.py to generate a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296089
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Petr Hosek [Fri, 24 Feb 2017 03:10:10 +0000 (03:10 +0000)]
[Fuchsia] Use thread-pointer ABI slots for stack-protector and safe-stack
The Fuchsia ABI defines slots from the thread pointer where the
stack-guard value for stack-protector, and the unsafe stack pointer
for safe-stack, are stored. This parallels the Android ABI support.
Patch by Roland McGrath
Differential Revision: https://reviews.llvm.org/D30237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296081
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Eli Friedman [Fri, 24 Feb 2017 03:04:11 +0000 (03:04 +0000)]
Add some testcases for bitfields with illegal widths.
clang will generate IR like this for input using packed bitfields;
very simple semantically, but it's a bit tricky to actually
generate good code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296080
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Eli Friedman [Fri, 24 Feb 2017 02:58:49 +0000 (02:58 +0000)]
Fix old testcase for dead store to match the original intent.
The x86 backend has a special case for load+xor+store, which isn't really
what this is trying to test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296077
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Xin Tong [Fri, 24 Feb 2017 01:43:36 +0000 (01:43 +0000)]
Fix an iterator invalidation bug when simplifying LIC user.
LoopUnswitch/simplify-with-nonvalness.ll is the test case for this.
The LIC has 2 users and deleting the 1st user when it can be simplified
invalidated the iterator for the 2nd user.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296069
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Adam Nemet [Fri, 24 Feb 2017 01:22:55 +0000 (01:22 +0000)]
[LazyMachineBFI] Add testcase
This is based on Justin's testcase and checking whether BFI is not populated
in case hotness is off.
This is a patch meant on top of Justin's patch to enable Machine opt-remarks
in the
AsmPrinter (http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20170130/426595.html)
Differential Revision: https://reviews.llvm.org/D29837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296065
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Michael Kuperstein [Fri, 24 Feb 2017 01:22:19 +0000 (01:22 +0000)]
Revert r269060 to pacify bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296064
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Justin Bogner [Fri, 24 Feb 2017 01:13:09 +0000 (01:13 +0000)]
OptDiag: Add test for r296053
Forgot to commit this with the change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296061
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Michael Kuperstein [Fri, 24 Feb 2017 00:56:21 +0000 (00:56 +0000)]
[CGP] Split some critical edges coming out of indirect branches
Splitting critical edges when one of the source edges is an indirectbr
is hard in general (because it requires changing the memory the indirectbr
reads). But if a block only has a single indirectbr predecessor (which is
the common case), we can simulate splitting that edge by splitting
the destination block, and retargeting the *direct* branches.
This is motivated by the use of computed gotos in python 2.7: PyEval_EvalFrame()
ends up using an indirect branch with ~100 successors, and passing a constant to
each of those. Since MachineSink can't break indirect critical edges on demand
(and doing this in MIR doesn't look feasible), this causes us to emit about ~100
defs of registers containing constants, which we in the predecessor block, where
only one of those constants is used in each successor. So, at each computed goto,
we needlessly spill about a 100 constants to stack. The end result is that a
clang-compiled python interpreter can be about ~2.5x slower on a simple python
reduction loop than a gcc-compiled interpreter.
Differential Revision: https://reviews.llvm.org/D29916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296060
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Ahmed Bougacha [Fri, 24 Feb 2017 00:34:47 +0000 (00:34 +0000)]
[GlobalISel] Use the same name for all remarks.
While there, switch to the explicit ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296059
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Ahmed Bougacha [Fri, 24 Feb 2017 00:34:44 +0000 (00:34 +0000)]
[GlobalISel] Use the DISubprogram for translation failure remarks.
Justin added support for DISubprogram locs in r295531 and r296052.
Use that instead of no-loc for constants and arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296058
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Ahmed Bougacha [Fri, 24 Feb 2017 00:34:41 +0000 (00:34 +0000)]
[GlobalISel] Remove now-unnecessary variable. NFC.
Since r296047, we're able to return early on failures.
Don't track whether we succeeded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296057
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Adrian McCarthy [Fri, 24 Feb 2017 00:25:17 +0000 (00:25 +0000)]
Fix unit tests after r296049.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296055
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Justin Bogner [Fri, 24 Feb 2017 00:19:22 +0000 (00:19 +0000)]
OptDiag: Summarize the instruction count in asm-printer
Add an optimization remark to asm-printer that summarizes the number
of instructions emitted per function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296053
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Justin Bogner [Fri, 24 Feb 2017 00:19:18 +0000 (00:19 +0000)]
OptDiag: Use DiagnosticLocation in MachineOptimizationRemarks
DiagnosticInfo switched from DebugLoc to DiagnosticLocation in
r295519, update these subclasses to match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296052
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Evgeniy Stepanov [Fri, 24 Feb 2017 00:13:17 +0000 (00:13 +0000)]
[msan] Fix instrumentation of array allocas.
Before this, MSan poisoned exactly one element of any array alloca,
even if the number of elements was zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296050
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Adrian McCarthy [Fri, 24 Feb 2017 00:10:47 +0000 (00:10 +0000)]
Implement some methods for NativeRawSymbol
This allows the ability to call IPDBSession::getGlobalScope with a NativeSession and
to then query it for some basic fields from the PDB's InfoStream.
Note that the symbols now have non-const references back to the Session so that
NativeRawSymbol can access the PDBFile through the Session.
Differential Revision: https://reviews.llvm.org/D30314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296049
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Ahmed Bougacha [Thu, 23 Feb 2017 23:57:36 +0000 (23:57 +0000)]
[GlobalISel] Don't translate other blocks when one failed.
We were stopping the translation of the parent block when the
translation of an instruction failed, but we were still trying to
translate the other blocks of the parent function.
Don't do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296047
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Ahmed Bougacha [Thu, 23 Feb 2017 23:57:28 +0000 (23:57 +0000)]
[GlobalISel] Finalize translated function on scope exit. NFC.
This is the compromise between having a per-function IRTranslator
and manually managing the per-function state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296046
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Adrian Prantl [Thu, 23 Feb 2017 23:54:29 +0000 (23:54 +0000)]
fix 80-column violation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296045
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Xin Tong [Thu, 23 Feb 2017 23:47:10 +0000 (23:47 +0000)]
Delete outdated comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296043
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Xin Tong [Thu, 23 Feb 2017 23:42:19 +0000 (23:42 +0000)]
LoopUnswitch - Simplify based on known not to a be constant.
Summary: In case we do not know what the condition is in an unswitched loop, but we know its definitely NOT a known constant. We can perform simplifcations based on this information.
Reviewers: sanjoy, hfinkel, chenli, efriedma
Reviewed By: efriedma
Subscribers: david2050, llvm-commits, mzolotukhin
Differential Revision: https://reviews.llvm.org/D28968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296041
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Adam Nemet [Thu, 23 Feb 2017 23:11:23 +0000 (23:11 +0000)]
[OptDiag] Comment about the legacy status of emitOptimizationRemark*
functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296039
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Adam Nemet [Thu, 23 Feb 2017 23:11:21 +0000 (23:11 +0000)]
[OptDiag] Remove hotness parameter from legacy remark ctors
Anything using hotness should be using ORE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296038
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Adam Nemet [Thu, 23 Feb 2017 23:11:11 +0000 (23:11 +0000)]
[OptDiag] Hide legacy remark ctors
These are only used when emitting remarks without ORE directly using the free
functions emitOptimizationRemark*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296037
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Bryant Wong [Thu, 23 Feb 2017 23:00:46 +0000 (23:00 +0000)]
[ADT] Fix zip iterator interface.
This commit provides `zip_{first,shortest}` with the standard member types and
methods expected of iterators (e.g., `difference_type`), in order for zip to be
used with other adaptors, such as `make_filter_range`.
Support for reverse iteration has also been added.
Differential Revision: https://reviews.llvm.org/D30246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296036
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Sanjoy Das [Thu, 23 Feb 2017 22:50:52 +0000 (22:50 +0000)]
[IR] Add a Instruction::dropPoisonGeneratingFlags helper
Summary:
The helper will be used in a later change. This change itself is NFC
since the only user of this new function is its unit test.
Reviewers: majnemer, efriedma
Reviewed By: efriedma
Subscribers: efriedma, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D30184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296035
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Artem Belevich [Thu, 23 Feb 2017 22:38:24 +0000 (22:38 +0000)]
[NVPTX] Added support for .f16x2 instructions.
This patch enables support for .f16x2 operations.
Added new register type Float16x2.
Added support for .f16x2 instructions.
Added handling of vectorized loads/stores of v2f16 values.
Differential Revision: https://reviews.llvm.org/D30057
Differential Revision: https://reviews.llvm.org/D30310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296032
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Tim Northover [Thu, 23 Feb 2017 22:35:00 +0000 (22:35 +0000)]
ARM: make sure FastISel bails on f64 operations for Cortex-M4.
FastISel wasn't checking the isFPOnlySP subtarget feature before emitting
double-precision operations, so it got completely invalid CodeGen for doubles
on Cortex-M4F.
The normal ISel testing wasn't spectacular either so I added a second RUN line
to improve that while I was in the area.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296031
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Hans Wennborg [Thu, 23 Feb 2017 22:29:00 +0000 (22:29 +0000)]
Revert r282872 "CVP. Turn marking adds as no wrap on by default"
While not CVP's fault, this caused miscompiles (PR31181). Reverting
until those are resolved.
(This also reverts the follow-ups r288154 and r288161 which removed the
flag.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296030
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Vedant Kumar [Thu, 23 Feb 2017 22:20:32 +0000 (22:20 +0000)]
[llvm-cov] Strip redundant path components from filenames (fix PR31982)
Instead of stripping the longest common prefix off of the filenames in a
report, strip out the longest chain of redundant path components. This
fixes the case in PR31982, where there are two files with the same
prefix, and stripping out the LCP makes things less intelligible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296029
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Dehao Chen [Thu, 23 Feb 2017 22:15:18 +0000 (22:15 +0000)]
Add call branch annotation for ICP promoted direct call in SamplePGO mode.
Summary: SamplePGO uses branch_weight annotation to represent callsite hotness. When ICP promotes an indirect call to direct call, we need to make sure the direct call is annotated with branch_weight in SamplePGO mode, so that downstream function inliner can use hot callsite heuristic.
Reviewers: davidxl, eraman, xur
Reviewed By: davidxl, xur
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D30282
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296028
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Krzysztof Parzyszek [Thu, 23 Feb 2017 22:11:52 +0000 (22:11 +0000)]
[Hexagon] Handle saturations in Hexagon bit tracker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296026
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Krzysztof Parzyszek [Thu, 23 Feb 2017 22:08:50 +0000 (22:08 +0000)]
[Hexagon] Allow setting register in BitVal without storing into map
In the bit tracker, references to other bit values in which the register
is 0 are prohibited. This means that generating self-referential register
cells like { w:32 [0-15]:s[0-15] [16-31]:s[15] } is impossible. In order
to get a self-referential cell, it had to be stored into a map and then
reloaded from it. To avoid this step, add a function that will set the
register to a given value without going through the map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296025
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Stanislav Mekhanoshin [Thu, 23 Feb 2017 21:51:28 +0000 (21:51 +0000)]
[AMDGPU] Shut the warning "getRegUnitWeight hides overload...". NFC.
Clang issues warning about hidden overload. That was intended, so
add "using AMDGPUGenRegisterInfo::getRegUnitWeight;" to mute it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296021
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Adam Nemet [Thu, 23 Feb 2017 21:32:53 +0000 (21:32 +0000)]
[ORE] Remove ORE.emit{{.+}} functions
Last use was killed in my previous patch. The preferred way is now to
construct the remark, pipe things to it and pass it to ORE.emit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296019
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Kyle Butt [Thu, 23 Feb 2017 21:22:24 +0000 (21:22 +0000)]
CodeGen: MachineBlockPlacement: Rename member to more general name. NFC.
Rename ComputedTrellisEdges to ComputedEdges to allow for other methods of
pre-computing edges.
Differential Revision: https://reviews.llvm.org/D30308
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296018
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Adam Nemet [Thu, 23 Feb 2017 21:17:36 +0000 (21:17 +0000)]
[LAA] Remove unused LoopAccessReport
The need for this removed when I converted everything to use the opt-remark
classes directly with the streaming interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296017
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Adam Nemet [Thu, 23 Feb 2017 21:17:31 +0000 (21:17 +0000)]
[LV] Remove unused VectorizationReport
The need for this removed when I converted everything to use the opt-remark
classes directly with the streaming interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296016
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Evgeniy Stepanov [Thu, 23 Feb 2017 21:06:35 +0000 (21:06 +0000)]
Disable TLS for stack protector on Android API<17.
The TLS slot did not exist back then.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296014
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Ahmed Bougacha [Thu, 23 Feb 2017 21:05:42 +0000 (21:05 +0000)]
[GlobalISel] Emit opt remarks on isel fallbacks.
Having more fine-grained information on the specific construct that
caused us to fallback is valuable for large-scale data collection.
We still have the fallback warning, that's also used for FastISel.
We still need to remove the fallback warning, and teach FastISel to also
emit remarks (it currently has a combination of the warning, stats, and
debug prints: the remarks could unify all three).
The abort-on-fallback path could also be better handled using remarks:
one could imagine a "-Rpass-error", analoguous to "-Werror", which would
promote missed/failed remarks to errors. It's not clear whether that
would be useful for other remarks though, so we're not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296013
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Ahmed Bougacha [Thu, 23 Feb 2017 21:05:33 +0000 (21:05 +0000)]
[CodeGen] Teach opt remarks how to print MI instructions.
This will be used with GISel opt remarks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296012
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Ahmed Bougacha [Thu, 23 Feb 2017 21:05:29 +0000 (21:05 +0000)]
[CodeGen] Print MI without a newline when skipping debugloc. NFC.
This matches the behavior for skip-operands. While there, document it.
This is a follow-up to r296007.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296011
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Ahmed Bougacha [Thu, 23 Feb 2017 21:05:23 +0000 (21:05 +0000)]
[CodeGen] Use const MBBs in the opt remark diagnostics. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296010
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Stanislav Mekhanoshin [Thu, 23 Feb 2017 20:19:44 +0000 (20:19 +0000)]
Correct register pressure calculation in presence of subregs
If a subreg is used in an instruction it counts as a whole superreg
for the purpose of register pressure calculation. This patch corrects
improper register pressure calculation by examining operand's lane mask.
Differential Revision: https://reviews.llvm.org/D29835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296009
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Ahmed Bougacha [Thu, 23 Feb 2017 19:17:34 +0000 (19:17 +0000)]
[ORE] Use const CodeRegions in the remark diagnostics. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296008
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Ahmed Bougacha [Thu, 23 Feb 2017 19:17:31 +0000 (19:17 +0000)]
[CodeGen] Add a way to SkipDebugLoc in MachineInstr::print(). NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296007
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Ahmed Bougacha [Thu, 23 Feb 2017 19:17:24 +0000 (19:17 +0000)]
[GlobalISel] Simplify Select type cleanup using a ScopeExit. NFC.
This lets us use more natural early-returns when selection fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296006
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Adrian Prantl [Thu, 23 Feb 2017 19:13:48 +0000 (19:13 +0000)]
Revert "Teach the IR verifier to reject conflicting debug info for function arguments."
This reverts commit r295749 while investigating PR32042.
It looks like this check uncovered a problem in the frontend that
needs to be fixed before the check can be enabled again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296005
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Sanjay Patel [Thu, 23 Feb 2017 19:02:33 +0000 (19:02 +0000)]
[DAG] add convenience function to get -1 constant; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296004
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