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Craig Topper [Wed, 6 Sep 2017 19:03:55 +0000 (19:03 +0000)]
[X86] Move more isel patterns to X86InstrVecCompiler.td. NFC
This moves more of our subvector insert/extract tricks to X86InstrVecCompiler.td and refactors them into multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312661
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Stanislav Mekhanoshin [Wed, 6 Sep 2017 18:29:51 +0000 (18:29 +0000)]
[AMDGPU] Fixed encoding of v_pk_mul_f16 in fcanonicalize
Differential Revision: https://reviews.llvm.org/D37522
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312660
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Krzysztof Parzyszek [Wed, 6 Sep 2017 17:57:13 +0000 (17:57 +0000)]
[IfConversion] Remove kill flags from common instructions as well
When if-converting a diamond, two separate blocks will be placed back
to back to form a straight line code. To ensure correctness of the
liveness information, any registers that are live in the second block
should not be killed in the first block, even if they were in the
original code.
Additionally, when the two blocks share common instructions at the
beginning, these instructions will not be duplicated, but only placed
once, before both of the blocks. Since the function "isIdenticalTo"
(as used here) ignores kill flags, the common initial code in one
block may have a kill flag for a register that is live in the other
block.
Because the code that removes kill flags only runs for the non-common
parts of the predicated blocks, a kill flag mismatch in the common
code could still lead to a live register being killed prematurely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312654
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Craig Topper [Wed, 6 Sep 2017 17:06:40 +0000 (17:06 +0000)]
[X86] Actually add the new file that was supposed to go with r312649.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312650
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Craig Topper [Wed, 6 Sep 2017 16:56:52 +0000 (16:56 +0000)]
[X86] Introduce a new td file to hold patterns some of the non instruction patterns from SSE and AVX512
This patch moves some of similar non-instruction patterns from X86InstrSSE.td and X86InstrAVX512.td to a common file.
This is intended as a starting point. There are many other optimization patterns that exist in both files that we could move here.
Differential Revision: https://reviews.llvm.org/D37455
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312649
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Nuno Lopes [Wed, 6 Sep 2017 16:55:31 +0000 (16:55 +0000)]
Fix PR33878: BasicAA incorrectly assumes different address spaces don't alias
Remove code that assumed that a nullptr of address space != 0 couldnt alias with a non-null pointer. This is incorrect, since nothing can be concluded about a null pointer in an address space != 0.
This code was written before address spaces were introduced
Differential Revision: https://reviews.llvm.org/D37518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312648
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Alexander Kornienko [Wed, 6 Sep 2017 16:28:33 +0000 (16:28 +0000)]
Minor style fixes in lib/Support/**/Program.(inc|cpp).
No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312646
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Petr Hosek [Wed, 6 Sep 2017 16:23:15 +0000 (16:23 +0000)]
Revert "[llvm-objcopy] Add support for relocations"
This reverts r312643 because it's failing on llvm-i686-linux-RA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312645
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Krzysztof Parzyszek [Wed, 6 Sep 2017 16:22:55 +0000 (16:22 +0000)]
[Hexagon] Add option to generate calls to "abort" for "unreachable"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312644
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Petr Hosek [Wed, 6 Sep 2017 16:19:48 +0000 (16:19 +0000)]
[llvm-objcopy] Add support for relocations
This change adds support for SHT_REL and SHT_RELA sections in
llvm-objcopy.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D36554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312643
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Wei Mi [Wed, 6 Sep 2017 16:05:17 +0000 (16:05 +0000)]
[TailCall] Allow llvm.memcpy/memset/memmove to be tail calls when parent
function return the intrinsics's first argument.
llvm.memcpy/memset/memmove return void but they will return the first
argument after they are expanded as libcalls. Now if the parent function
has any return value, llvm.memcpy cannot be turned into tail call after
expansion.
The patch is to handle that case in SelectionDAGBuilder so when caller
function return the same value as the first argument of llvm.memcpy,
tail call is allowed.
Differential Revision: https://reviews.llvm.org/D37406
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312641
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Stanislav Mekhanoshin [Wed, 6 Sep 2017 15:31:30 +0000 (15:31 +0000)]
[AMDGPU] Fix shouldClusterMemOps to process flat loads
Flat loads do not have vdata operand but have vdst instead.
Differential Revision: https://reviews.llvm.org/D37502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312640
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Nicolai Haehnle [Wed, 6 Sep 2017 13:50:13 +0000 (13:50 +0000)]
AMDGPU: Make worst-case assumption about the wait states in inline assembly
Summary:
Mesa still uses a hack where empty inline assembly is used as a kind of
optimization barrier. This exposed a problem where not enough wait states
were inserted, because the hazard recognizer implicitly assumed that each
inline assembly "instruction" has at least one wait state.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D37205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312635
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Simon Pilgrim [Wed, 6 Sep 2017 10:23:12 +0000 (10:23 +0000)]
[X86][X87] Ensure x87 instructions are tagged as altering the FPSW reg
As noted in PR34080, a lot of x87 instructions alter the FPSW status register (or leave it in an undefined state) but aren't tagged as such in the tablegen.
This patch tags the control word, stack, wait and math instructions as altering FPSW, which matches what the AMD APMs suggests happens.
Differential Revision: https://reviews.llvm.org/D36414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312629
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Alex Bradbury [Wed, 6 Sep 2017 09:21:21 +0000 (09:21 +0000)]
[RISCV][NFC] Fix sorting of includes in lib/Target/RISCV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312624
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Craig Topper [Wed, 6 Sep 2017 06:50:03 +0000 (06:50 +0000)]
[DAGCombiner] When combining EXTRACT_SUBVECTOR of a BUILD_VECTOR, make sure we don't create a BUILD_VECTOR with an illegal type after type legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312621
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Chandler Carruth [Wed, 6 Sep 2017 06:28:08 +0000 (06:28 +0000)]
[x86] Fix PR34377 by disabling cmov conversion when we relied on it
performing a zext of a register.
On the PR there is discussion of how to more effectively handle this,
but this patch prevents us from miscompiling code.
Differential Revision: https://reviews.llvm.org/D37504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312620
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Zvi Rackover [Wed, 6 Sep 2017 05:33:04 +0000 (05:33 +0000)]
X86 Tests: Tidy up AVX512 conversion tests. NFC.
Rename functions to a consistent format to make it easier to track coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312619
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Jatin Bhateja [Wed, 6 Sep 2017 03:58:14 +0000 (03:58 +0000)]
Updating a test reference for rL312608.
Differential Revision: https://reviews.llvm.org/D37501
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312614
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Craig Topper [Wed, 6 Sep 2017 03:35:58 +0000 (03:35 +0000)]
[X86] Add more FMA3 patterns to cover a load in all 3 possible positions.
This matches what we already do for AVX512. The peephole pass makes up for this in most if not all cases. But this makes isel behavior for these consistent with every other instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312613
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Hal Finkel [Wed, 6 Sep 2017 03:08:26 +0000 (03:08 +0000)]
[PowerPC] Don't use xscvdpspn on the P7
xscvdpspn was not introduced until the P8, so don't use it on the P7. Fixes a
regression introduced in r288152.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312612
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Jatin Bhateja [Wed, 6 Sep 2017 02:58:47 +0000 (02:58 +0000)]
[X86] Allow cross-lane permutations for sub targets supporting AVX2.
Summary:
Most instructions in AVX work “in-lane”, that is, each source element is applied only to other
elements of the same lane, thus a cross lane permutation is costly and needs more than one instrution.
AVX2 includes instructions to perform any-to-any permutation of words over a 256-bit register
and vectorized table lookup.
This should also Fix PR34369
Differential Revision: https://reviews.llvm.org/D37388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312608
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Lang Hames [Wed, 6 Sep 2017 02:53:37 +0000 (02:53 +0000)]
[ORC] Fix some comments in JITSymbol.
Patch by Breckin Loggins. Thanks Breckin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312607
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Eric Beckmann [Wed, 6 Sep 2017 01:50:36 +0000 (01:50 +0000)]
Fix crbug 759265 by suppressing llvm mt warnings.
Summary:
Previous would throw warning whenever libxml2 is not installed. Now
only give this warning if merging manifest fails.
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37240
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312604
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Rafael Espindola [Wed, 6 Sep 2017 00:57:53 +0000 (00:57 +0000)]
Use the section name if a STT_SECTION symbol has empty name.
Without this we would have multiple relocations pointing to symbols
with the same name: the empty string. There was no way for yaml2obj to
be able to handle that.
A more general solution would be to unique symbol names in a similar
way to how we unique section names. In practice I think this covers
all common cases and is a bit more user friendly than using names like
sym1, sym2, sym3, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312603
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Yaxun Liu [Wed, 6 Sep 2017 00:30:27 +0000 (00:30 +0000)]
[AMDGPU] Transform __read_pipe_* and __write_pipe_*
When packet size equals packet align and is power of 2, transform
__read_pipe* and __write_pipe* to specialized library function.
Differential Revision: https://reviews.llvm.org/D36831
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312598
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Sanjay Patel [Tue, 5 Sep 2017 23:13:13 +0000 (23:13 +0000)]
[ValueTracking, InstCombine] canonicalize fcmp ord/uno with non-NAN ops to null constants
This is a preliminary step towards solving the remaining part of PR27145 - IR for isfinite():
https://bugs.llvm.org/show_bug.cgi?id=27145
In order to solve that one more generally, we need to add matching for and/or of fcmp ord/uno
with a constant operand.
But while looking at those patterns, I realized we were missing a canonicalization for nonzero
constants. Rather than limiting to just folds for constants, we're adding a general value
tracking method for this based on an existing DAG helper.
By transforming everything to 0.0, we can simplify the existing code in foldLogicOfFCmps()
and pick up missing vector folds.
Differential Revision: https://reviews.llvm.org/D37427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312591
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Rafael Espindola [Tue, 5 Sep 2017 23:00:51 +0000 (23:00 +0000)]
Fix a use after free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312590
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Eli Friedman [Tue, 5 Sep 2017 22:54:06 +0000 (22:54 +0000)]
[ARM] Make ARMExpandPseudo add implicit uses for predicated instructions
Missing these could potentially screw up post-ra scheduling.
Issue found by inspection, so I don't have a real testcase. Included
test just verifies the expected operands after expansion.
Differential Revision: https://reviews.llvm.org/D35156
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312589
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Eli Friedman [Tue, 5 Sep 2017 22:45:23 +0000 (22:45 +0000)]
[ARM] Register ARMExpandPseudo pass.
This allows -run-pass etc. to refer to it.
(Split off from D35156.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312587
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Rafael Espindola [Tue, 5 Sep 2017 22:30:00 +0000 (22:30 +0000)]
obj2yaml: Print unique section names.
Without this patch passing a .o file with multiple sections with the
same name to obj2yaml produces a yaml file that yaml2obj cannot
handle. This is pr34162.
The problem is that when specifying, for example, the section of a
symbol, we get only
Section: foo
and don't know which of the sections whose name is foo we have to use.
One alternative would be to use section numbers. This would work, but
the output from obj2yaml would be very inconvenient to edit as
deleting a section would invalidate all indexes.
Another alternative would be to invent a unique section id that would
exist only on yaml. This would work, but seems a bit heavy handed. We
could make the id optional and default it to the section name.
Since in the last alternative the id is basically what this patch uses
as a name, it can be implemented as a followup patch if needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312585
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Lang Hames [Tue, 5 Sep 2017 22:24:40 +0000 (22:24 +0000)]
[ORC] Convert null remote symbols to null JITSymbols.
The existing code created a JITSymbol with an invalid materializer instead,
guaranteeing a 'missing symbol' error when someone tried to materialize the
symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312584
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Zachary Turner [Tue, 5 Sep 2017 22:06:39 +0000 (22:06 +0000)]
[CodeView] Don't output S_UDTs for nested typedefs.
S_UDT records are basically the "bridge" between the debugger's
expression evaluator and the type information. If you type
(Foo*)nullptr into the watch window, the debugger looks for an
S_UDT record named Foo. If it can find one, it displays your type.
Otherwise you get an error.
We have always understood this to mean that if you have code like
this:
struct A {
int X;
};
struct B {
typedef A AT;
AT Member;
};
that you will get 3 S_UDT records. "A", "B", and "B::AT". Because
if you were to type (B::AT*)nullptr into the debugger, it would
need to find an S_UDT record named "B::AT".
But "B::AT" is actually the S_UDT record that would be generated
if B were a namespace, not a struct. So the debugger needs to be
able to distinguish this case. So what it does is:
1. Look for an S_UDT named "B::AT". If it finds one, it knows
that AT is in a namespace.
2. If it doesn't find one, split at the scope resolution operator,
and look for an S_UDT named B. If it finds one, look up the type
for B, and then look for AT as one of its members.
With this algorithm, S_UDT records for nested typedefs are not just
unnecessary, but actually wrong!
The results of implementing this in clang are dramatic. It cuts
our /DEBUG:FASTLINK PDB sizes by more than 50%, and we go from
being ~20% larger than MSVC PDBs on average, to ~40% smaller.
It also slightly speeds up link time. We get about 10% faster
links than without this patch.
Differential Revision: https://reviews.llvm.org/D37410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312583
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Vedant Kumar [Tue, 5 Sep 2017 22:04:00 +0000 (22:04 +0000)]
Revert "[Decompression] Fail gracefully when out of memory"
This reverts commit r312526.
Revert "Fix test/DebugInfo/dwarfdump-decompression-invalid-size.test"
This reverts commit r312527.
It causes an ASan failure:
http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check/4150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312582
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Davide Italiano [Tue, 5 Sep 2017 21:27:23 +0000 (21:27 +0000)]
[unittest/ReverseIteration] Unbreak when compiling with GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312579
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Sanjay Patel [Tue, 5 Sep 2017 21:20:35 +0000 (21:20 +0000)]
[InstCombine] add nnan tests; NFC
As suggested in D37427, we could have a value tracking function and folds that use
it to simplify these cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312578
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Davide Italiano [Tue, 5 Sep 2017 20:49:41 +0000 (20:49 +0000)]
[GVNHoist] Move duplicated code to a helper function. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312575
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Mandeep Singh Grang [Tue, 5 Sep 2017 20:39:01 +0000 (20:39 +0000)]
[unittests] Add reverse iteration unit test for pointer-like keys
Reviewers: dblaikie, efriedma, mehdi_amini
Reviewed By: dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37241
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312574
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Reid Kleckner [Tue, 5 Sep 2017 20:26:25 +0000 (20:26 +0000)]
Fix RST syntax in LangRef for llvm.codeview.annotation intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312571
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Reid Kleckner [Tue, 5 Sep 2017 20:14:58 +0000 (20:14 +0000)]
Add llvm.codeview.annotation to implement MSVC __annotation
Summary:
This intrinsic represents a label with a list of associated metadata
strings. It is modelled as reading and writing inaccessible memory so
that it won't be removed as dead code. I think the intention is that the
annotation strings should appear at most once in the debug info, so I
marked it noduplicate. We are allowed to inline code with annotations as
long as we strip the annotation, but that can be done later.
Reviewers: majnemer
Subscribers: eraman, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D36904
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312569
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Daniel Neilson [Tue, 5 Sep 2017 19:54:03 +0000 (19:54 +0000)]
[SCEV] Ensure ScalarEvolution::createAddRecFromPHIWithCastsImpl properly handles out of range truncations of the start and accum values
Summary:
When constructing the predicate P1 in ScalarEvolution::createAddRecFromPHIWithCastsImpl() it is possible
for the PHISCEV from which the predicate is constructed to be a SCEVConstant instead of a SCEVAddRec. If
this happens, then the cast<SCEVAddRec>(PHISCEV) in the code will assert.
Such a PHISCEV is possible if either the start value or the accumulator value is a constant value
that not equal to its truncated value, and if the truncated value is zero.
This patch adds tests that demonstrate the cast<> assertion, and fixes this problem by checking
whether the PHISCEV is a constant before constructing the P1 predicate; if it is, then P1 is
equivalent to one of P2 or P3. Additionally, if we know that the start value or accumulator
value are constants then we check whether the P2 and/or P3 predicates are known false at compile
time; if either is, then we bail out of constructing the AddRec.
Reviewers: sanjoy, mkazantsev, silviu.baranga
Reviewed By: mkazantsev
Subscribers: mkazantsev, llvm-commits
Differential Revision: https://reviews.llvm.org/D37265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312568
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Peter Collingbourne [Tue, 5 Sep 2017 19:51:38 +0000 (19:51 +0000)]
LTO: Try to open cache files before renaming them.
It appears that a potential race between the cache client and the cache
pruner that I thought was unlikely actually happened in practice [1].
Try to avoid the race condition by opening the temporary file before
renaming it. Do this only on non-Windows platforms because we cannot
rename open files on Windows using the sys::fs::rename function.
[1] https://luci-logdog.appspot.com/v/?s=chromium%2Fbb%2Fchromium.memory%2FLinux_CFI%2F1610%2F%2B%2Frecipes%2Fsteps%2Fcompile%2F0%2Fstdout
Differential Revision: https://reviews.llvm.org/D37410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312567
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Craig Topper [Tue, 5 Sep 2017 19:09:02 +0000 (19:09 +0000)]
[X86] Remove unnecessary (v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X)))) patterns
We had already disabled the pattern for SSE4.1 and SSE4.2. But it got re-enabled for AVX and AVX512.
With SSE41 we rely on a separate (v4f32 (X86vzmovl VR128)) pattern to select blendps with a xorps to create zeroess. And a separate (v4f32 (scalar_to_vector FR32X)) to select a COPY_TO_REG_CLASS to move FR32 to VR128
The same thing can happen for AVX with vblendps and those separate patterns already exist.
For AVX512, (v4f32 (X86vzmov VR128)) will select a VMOVSS instruction instead of VBLENDPS due to their not being a EVEX VBLENDPS. This is what we were getting out of the larger pattern anyway. So the larger pattern is unneeded for AVX512 too.
For SSE1-SSSE3 we can rely on (v4f32 (X86vzmov VR128)) selecting a MOVSS similar to AVX512. Again this is what the larger pattern did too.
So the only real change here is that AVX1/2 now properly outputs a VBLENDPS during isel instead of a VMOVSS to match SSE41. Most tests didn't notice because the two address instruction pass knows how to turn VMOVSS into VBLENDPS to get an independent destination register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312564
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Konstantin Zhuravlyov [Tue, 5 Sep 2017 19:01:10 +0000 (19:01 +0000)]
AMDGPU: Cleanup/refactor SIMemoryLegalizer [3]:
- Refactor SIMemOpInfo's constructors
- Allow construction of NotAtomic SIMemOpInfo
Differential Revision: https://reviews.llvm.org/D37396
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312563
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Matt Arsenault [Tue, 5 Sep 2017 18:36:36 +0000 (18:36 +0000)]
AMDGPU: Fix not accounting for tail call resource usage
If the only call in a function is a tail call, the
function isn't considered to have a call since it's a
type of return.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312561
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Zvi Rackover [Tue, 5 Sep 2017 18:24:39 +0000 (18:24 +0000)]
X86 Tests: Adding missing AVX512 fptoui coverage tests. NFC.
Some of the cases show missing pattern i intend to fix shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312560
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Tony Jiang [Tue, 5 Sep 2017 18:08:02 +0000 (18:08 +0000)]
[PPC][NFC] Renaming things with 'xxinsert' moniker to 'vecinsert' to make it more general.
Commit on behalf of Graham Yiu (gyiu@ca.ibm.com)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312547
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Adam Nemet [Tue, 5 Sep 2017 18:03:39 +0000 (18:03 +0000)]
Split opt-remark YAML and opt output testing on this test
This prepares for https://reviews.llvm.org/D33514
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312544
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Craig Topper [Tue, 5 Sep 2017 17:33:58 +0000 (17:33 +0000)]
[AVX512] Remove patterns for (v8f32 (X86vzmovl (insert_subvector undef, (v4f32 (scalar_to_vector FR32X:)), (iPTR 0)))) and the same for v4f64.
We don't have this same pattern for AVX2 so I don't believe we should have it for AVX512. We also didn't have it for v16f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312543
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Konstantin Zhuravlyov [Tue, 5 Sep 2017 16:41:25 +0000 (16:41 +0000)]
AMDGPU/NFC: Cleanup/refactor SIMemoryLegalizer [2]:
- Make SIMemOpInfo a class
- Add accessor methods to SIMemOpInfo
- Move get*Info methods to SIMemOpInfo
Differential Revision: https://reviews.llvm.org/D37395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312541
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Konstantin Zhuravlyov [Tue, 5 Sep 2017 16:18:05 +0000 (16:18 +0000)]
AMDGPU/NFC: Cleanup/refactor SIMemoryLegalizer [1]:
- Rename MemOpInfo -> SIMemOpInfo
- Move SIMemOpInfo class out of SIMemoryLegalizer class
Differential Revision: https://reviews.llvm.org/D37394
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312540
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Simon Pilgrim [Tue, 5 Sep 2017 14:32:06 +0000 (14:32 +0000)]
[AMDGPU] Added extra test checks to make D19325 diff clearer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312537
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Simon Pilgrim [Tue, 5 Sep 2017 13:40:29 +0000 (13:40 +0000)]
[X86] Limit store merge size when implicitfloat is enabled (PR34421)
As suggested by @niravd : https://bugs.llvm.org/show_bug.cgi?id=34421#c2
Differential Revision: https://reviews.llvm.org/D37464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312534
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Simon Pilgrim [Tue, 5 Sep 2017 12:32:16 +0000 (12:32 +0000)]
Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312531
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Simon Pilgrim [Tue, 5 Sep 2017 12:28:30 +0000 (12:28 +0000)]
[X86] Regenerate scalar rotation tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312530
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Simon Pilgrim [Tue, 5 Sep 2017 12:23:45 +0000 (12:23 +0000)]
[X86][AVX512] Use AVX512 attributes instead of -mcpu in vector shift tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312529
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Simon Pilgrim [Tue, 5 Sep 2017 12:05:14 +0000 (12:05 +0000)]
[X86][AVX512] Use AVX512 attributes instead of -mcpu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312528
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Jonas Devlieghere [Tue, 5 Sep 2017 11:59:16 +0000 (11:59 +0000)]
Fix test/DebugInfo/dwarfdump-decompression-invalid-size.test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312527
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Jonas Devlieghere [Tue, 5 Sep 2017 11:21:38 +0000 (11:21 +0000)]
[Decompression] Fail gracefully when out of memory
This patch adds failing gracefully when running out of memory when
allocating a buffer for decompression.
This provides a work-around for:
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3224
Differential revision: https://reviews.llvm.org/D37447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312526
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Diana Picus [Tue, 5 Sep 2017 08:22:47 +0000 (08:22 +0000)]
[ARM] GlobalISel: Minor cleanups in inst selector
Use the STI member of ARMInstructionSelector instead of
TII.getSubtarget() and also make use of STI's methods instead of
checking the object format manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312522
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Diana Picus [Tue, 5 Sep 2017 07:57:41 +0000 (07:57 +0000)]
[ARM] GlobalISel: Support global variables for RWPI
In RWPI code, globals that are not read-only are accessed relative to
the SB register (R9). This is achieved by explicitly generating an ADD
instruction between SB and an offset that we either load from a constant
pool or movw + movt into a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312521
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Craig Topper [Tue, 5 Sep 2017 05:49:44 +0000 (05:49 +0000)]
[X86] Add hasSideEffects=0 and mayLoad=1 to some instructions that recently had their patterns removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312520
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Craig Topper [Tue, 5 Sep 2017 05:26:38 +0000 (05:26 +0000)]
[InstCombine] Add test cases for folding (select (icmp ne/eq (and X, C1), (bitwiseop Y, C2), Y -> (bitwiseop Y, (shl/shr (and X, C1), C3)) or similar.
This is possible if C1 and C2 are both powers of 2. Or if binop is 'and' then ~C2 needs to be a power of 2.
We already support this for 'or', but we should be able to support 'and' and 'xor'. This will be enhanced by D37274.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312519
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Craig Topper [Tue, 5 Sep 2017 05:26:37 +0000 (05:26 +0000)]
[InstCombine] Move foldSelectICmpAnd helper function earlier in the file to enable reuse in a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312518
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Craig Topper [Tue, 5 Sep 2017 05:26:36 +0000 (05:26 +0000)]
[InstCombine] In foldSelectIntoOp, avoid creating a Constant before we know for sure we're going to use it and avoid an unnecessary call to m_APInt.
Instead of creating a Constant and then calling m_APInt with it (which will always return true). Just create an APInt initially, and use that for the checks in isSelect01 function. If it turns out we do need the Constant, create it from the APInt.
This is a refactor for a future patch that will do some more checks of the constant values here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312517
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Lang Hames [Tue, 5 Sep 2017 05:06:05 +0000 (05:06 +0000)]
[ORC] Add some more docs/comments to the RemoteObjectLayer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312516
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Lang Hames [Tue, 5 Sep 2017 04:31:14 +0000 (04:31 +0000)]
[ORC] Exclude RemoteObjectLayer from the ExecutionEngine module, as modules
builds seem to be having trouble with it.
http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/11401
When trying to link lli-child-target, the linker reports missing symbols for
the 'Name' members of 'rpc::Function<OrcRPCNegotiate, FunctionIdT(std::string)>'
(base class for OrcRPCNegotiate) and 'rpc::Function<OrcRPCResponse, void()>'
(base class for OrcRPCResponse), despite there being definitions for these
immediately below the rpc::Function class template.
This looks like the same bug that bit OrcRemoteTargetClient/Server in r286920.
<rdar://problem/
34249745>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312515
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Hiroshi Inoue [Tue, 5 Sep 2017 04:15:17 +0000 (04:15 +0000)]
[PowerPC] eliminate redundant compare instruction
If multiple conditional branches are executed based on the same comparison, we can execute multiple conditional branches based on the result of one comparison on PPC. For example,
if (a == 0) { ... }
else if (a < 0) { ... }
can be executed by one compare and two conditional branches instead of two pairs of a compare and a conditional branch.
This patch identifies a code sequence of the two pairs of a compare and a conditional branch and merge the compares if possible.
To maximize the opportunity, we do canonicalization of code sequence before merging compares.
For the above example, the input for this pass looks like:
cmplwi r3, 0
beq 0, .LBB0_3
cmpwi r3, -1
bgt 0, .LBB0_4
So, before merging two compares, we canonicalize it as
cmpwi r3, 0 ; cmplwi and cmpwi yield same result for beq
beq 0, .LBB0_3
cmpwi r3, 0 ; greather than -1 means greater or equal to 0
bge 0, .LBB0_4
The generated code should be
cmpwi r3, 0
beq 0, .LBB0_3
bge 0, .LBB0_4
Differential Revision: https://reviews.llvm.org/D37211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312514
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Lang Hames [Tue, 5 Sep 2017 04:11:51 +0000 (04:11 +0000)]
[ORC] Drop callB wrapper from the remote object layer added in r312511.
This snippet was accidentally in the final commit, but is unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312513
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Lang Hames [Tue, 5 Sep 2017 03:34:09 +0000 (03:34 +0000)]
[ORC] Add a pair of ORC layers that forward object-layer operations via RPC.
This patch introduces RemoteObjectClientLayer and RemoteObjectServerLayer,
which can be used to forward ORC object-layer operations from a JIT stack in
the client to a JIT stack (consisting only of object-layers) in the server.
This is a new way to support remote-JITing in LLVM. The previous approach
(supported by OrcRemoteTargetClient and OrcRemoteTargetServer) used a
remote-mapping memory manager that sat "beneath" the JIT stack and sent
fully-relocated binary blobs to the server. The main advantage of the new
approach is that relocatable objects can be cached on the server and re-used
(if the code that they represent hasn't changed), whereas fully-relocated blobs
can not (since the addresses they have been permanently bound to will change
from run to run).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312511
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Daniel Berlin [Tue, 5 Sep 2017 02:17:43 +0000 (02:17 +0000)]
NewGVN: Fix PR 34430 - we need to look through predicateinfo copies to detect self-cycles of phi nodes. We also need to not ignore certain types of arguments when testing whether the phi has a backedge or was originally constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312510
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Daniel Berlin [Tue, 5 Sep 2017 02:17:42 +0000 (02:17 +0000)]
NewGVN: Fix PR 34452 by passing instruction all the way down when we do aggregate value simplification
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312509
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Daniel Berlin [Tue, 5 Sep 2017 02:17:41 +0000 (02:17 +0000)]
NewGVN: Detect copies through predicateinfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312508
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Daniel Berlin [Tue, 5 Sep 2017 02:17:40 +0000 (02:17 +0000)]
NewGVN: Change where check for original instruction in phi of ops leader finding is done. Where we had it before, we would stop looking when we hit the original instruction, but skip it. Now we skip it and keep looking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312507
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Sanjay Patel [Mon, 4 Sep 2017 22:01:25 +0000 (22:01 +0000)]
[x86] add tests for vector store merge opportunity; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312504
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Sanjay Patel [Mon, 4 Sep 2017 21:46:05 +0000 (21:46 +0000)]
[x86] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312503
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Sanjay Patel [Mon, 4 Sep 2017 21:43:32 +0000 (21:43 +0000)]
[x86] add/regenerate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312502
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Lang Hames [Mon, 4 Sep 2017 20:54:46 +0000 (20:54 +0000)]
[ORC] Refactor OrcRemoteTarget code to expose its RPC API, reduce
code duplication in the client, and improve error propagation.
This patch moves the OrcRemoteTarget rpc::Function declarations from
OrcRemoteTargetRPCAPI into their own namespaces under llvm::orc::remote so that
they can be used in new contexts (in particular, a remote-object-file adapter
layer that I will commit shortly).
Code duplication in OrcRemoteTargetClient (especially in loops processing the
code, rw-data and ro-data allocations) is removed by moving the loop bodies
into their own functions.
Error propagation is (slightly) improved by adding an ErrorReporter functor to
the OrcRemoteTargetClient -- Errors that can't be returned (because they occur
in destructors, or behind stable APIs that don't provide error returns) can be
sent to the ErrorReporter instead. Some methods in the Client API are also
changed to make better use of the Expected class: returning Expected<T>s rather
than returning Errors and taking T&s to store the results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312500
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Sanjay Patel [Mon, 4 Sep 2017 17:21:17 +0000 (17:21 +0000)]
[x86] add test for unnecessary cmp + masked store; NFC
As noted in PR11210:
https://bugs.llvm.org/show_bug.cgi?id=11210
...fixing this should allow us to eliminate x86-specific masked store intrinsics in IR.
(Although more testing will be needed to confirm that.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312496
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Sam McCall [Mon, 4 Sep 2017 15:47:00 +0000 (15:47 +0000)]
Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding""
This crashes on boringSSL on PPC (will send reduced testcase)
This reverts commit r312328.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312490
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Strahinja Petrovic [Mon, 4 Sep 2017 15:14:37 +0000 (15:14 +0000)]
Fix test/Transforms/GlobalOpt/integer-bool-dwarf
This patch fixes regression related with
integer-bool-dwarf test.
Patch by Nikola Prica.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312489
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Michael Zuckerman [Mon, 4 Sep 2017 14:15:34 +0000 (14:15 +0000)]
Update test for testing avx512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312487
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Simon Pilgrim [Mon, 4 Sep 2017 13:51:57 +0000 (13:51 +0000)]
[X86][AVX512] Add support for VPERMILPS v16f32 shuffle lowering (PR34382)
Avoid use of VPERMPS where we don't need it by instead using the variable mask version of VPERMILPS for unary shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312486
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Simon Pilgrim [Mon, 4 Sep 2017 13:43:13 +0000 (13:43 +0000)]
Added shuffle test case from PR34382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312485
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Simon Pilgrim [Mon, 4 Sep 2017 11:08:47 +0000 (11:08 +0000)]
Added shuffle test case from PR34369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312481
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George Rimar [Mon, 4 Sep 2017 10:30:39 +0000 (10:30 +0000)]
[DebugInfo] - Fix for lld DWARF parsing of base address selection entries in range lists.
It solves issue of wrong section index evaluating for ranges when
base address is used.
Based on David Blaikie's patch D36097.
Differential revision: https://reviews.llvm.org/D37214
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312477
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Ayman Musa [Mon, 4 Sep 2017 09:31:32 +0000 (09:31 +0000)]
[X86] Replace -mcpu option with -mattr in LIT tests added in https://reviews.llvm.org/rL312442
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312474
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Igor Breger [Mon, 4 Sep 2017 09:06:45 +0000 (09:06 +0000)]
[GlobalISel][X86] G_PHI support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312473
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Zvi Rackover [Mon, 4 Sep 2017 08:35:13 +0000 (08:35 +0000)]
LoopVectorize: MaxVF should not be larger than the loop trip count
Summary:
Improve how MaxVF is computed while taking into account that MaxVF should not be larger than the loop's trip count.
Other than saving on compile-time by pruning the possible MaxVF candidates, this patch fixes pr34438 which exposed the following flow:
1. Short trip count identified -> Don't bail out, set OptForSize:=True to avoid tail-loop and runtime checks.
2. Compute MaxVF returned 16 on a target supporting AVX512.
3. OptForSize -> choose VF:=MaxVF.
4. Bail out because TripCount = 8, VF = 16, TripCount % VF !=0 means we need a tail loop.
With this patch step 2. will choose MaxVF=8 based on TripCount.
Reviewers: Ayal, dorit, mkuper, hfinkel
Reviewed By: hfinkel
Subscribers: hfinkel, llvm-commits
Differential Revision: https://reviews.llvm.org/D37425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312472
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Sam Parker [Mon, 4 Sep 2017 08:12:16 +0000 (08:12 +0000)]
[LoopUnroll][DebugInfo] Don't add metadata to unrolled remainder loop
Debug information can be, and was, corrupted when the runtime
remainder loop was fully unrolled. This is because a !null node can
be created instead of a unique one describing the loop. In this case,
the original node gets incorrectly updated with the NewLoopID
metadata.
In the case when the remainder loop is going to be quickly fully
unrolled, there isn't the need to add loop metadata for it anyway.
Differential Revision: https://reviews.llvm.org/D37338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312471
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Craig Topper [Mon, 4 Sep 2017 07:35:05 +0000 (07:35 +0000)]
[X86] Remove duplicate FMA patterns from the isel table.
This reorders some patterns to get tablegen to detect them as duplicates. Tablegen only detects duplicates when creating variants for commutable operations. It does not detect duplicates between the patterns as written in the td file. So we need to ensure all the FMA patterns in the td file are unique.
This also uses null_frag to remove some other unneeded patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312470
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Craig Topper [Mon, 4 Sep 2017 06:59:50 +0000 (06:59 +0000)]
[X86] Mark the FMA nodes as commutable so tablegen will auto generate the patterns.
This uses the capability introduced in r312464 to make SDNode patterns commutable on the first two operands.
This allows us to remove some of the extra FMA patterns that have to put loads and mask operands in different places to cover all cases. This even includes patterns that were missing to support match a load in the first operand with FMA4. Non-broadcast loads with masking for AVX512.
I believe this is causing us to generate some duplicate patterns because tablegen's isomorphism checks don't catch isomorphism between the patterns as written in the td. It only detects isomorphism in the commuted variants it tries to create. The the unmasked 231 and 132 memory forms are isomorphic as written in the td file so we end up keeping both. I think we precommute the 132 pattern to fix this.
We also need a follow up patch to go back to the legacy FMA3 instructions and add patterns to the 231 and 132 forms which we currently don't have.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312469
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Dean Michael Berris [Mon, 4 Sep 2017 05:34:58 +0000 (05:34 +0000)]
[XRay][CodeGen] Use PIC-friendly code in XRay sleds and remove synthetic references in .text
Summary:
This is a re-roll of D36615 which uses PLT relocations in the back-end
to the call to __xray_CustomEvent() when building in -fPIC and
-fxray-instrument mode.
Reviewers: pcc, djasper, bkramer
Subscribers: sdardis, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D37373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312466
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Craig Topper [Mon, 4 Sep 2017 03:44:33 +0000 (03:44 +0000)]
[TableGen] Teach tablegen to allow SDNPCommutable nodes with more than 2 operands.
Summary:
Tablegen already supports commutable instrinsics with more than 2 operands. There it just assumes the first two operands are commutable.
I plan to use this to improve the generation of FMA patterns in the X86 backend.
Reviewers: aymanmus, zvi, RKSimon, spatel, arsenm
Reviewed By: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: https://reviews.llvm.org/D37430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312464
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Craig Topper [Mon, 4 Sep 2017 01:13:36 +0000 (01:13 +0000)]
[X86] Add a combine to recognize when we have two insert subvectors that together write the whole vector, but the starting vector isn't undef.
In this case we should replace the starting vector with undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312462
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Craig Topper [Mon, 4 Sep 2017 01:13:34 +0000 (01:13 +0000)]
[X86] Remove some unnecessary curly braces and blank line. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312461
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Craig Topper [Sun, 3 Sep 2017 22:25:52 +0000 (22:25 +0000)]
[X86] Add a combine to turn (insert_subvector zero, (insert_subvector zero, X, Idx), Idx) into an insert of X into the larger zero vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312460
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 3 Sep 2017 22:25:50 +0000 (22:25 +0000)]
[X86] Add more patterns to use moves to zero the upper portions of a vector register that I missed in r312450.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312459
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 3 Sep 2017 22:25:49 +0000 (22:25 +0000)]
[X86] Combine inserting a vector of zeros into a vector of zeros just the larger vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312458
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 3 Sep 2017 17:52:25 +0000 (17:52 +0000)]
[X86] Add patterns to turn an insert into lower subvector of a zero vector into a move instruction which will implicitly zero the upper elements.
Ideally we'd be able to emit the SUBREG_TO_REG without the explicit register->register move, but we'd need to be sure the producing operation would select something that guaranteed the upper bits were already zeroed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312450
91177308-0d34-0410-b5e6-
96231b3b80d8