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Matt Arsenault [Wed, 13 Sep 2017 23:47:01 +0000 (23:47 +0000)]
AMDGPU: Don't spill SP reg like a normal CSR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313217
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Reid Kleckner [Wed, 13 Sep 2017 23:30:01 +0000 (23:30 +0000)]
[codeview] Fold FIXME into comment, there's nothing to do. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313214
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Hans Wennborg [Wed, 13 Sep 2017 23:23:09 +0000 (23:23 +0000)]
Revert r312719 "[MachineCombiner] Update instruction depths incrementally for large BBs."
This caused PR34596.
> [MachineCombiner] Update instruction depths incrementally for large BBs.
>
> Summary:
> For large basic blocks with lots of combinable instructions, the
> MachineTraceMetrics computations in MachineCombiner can dominate the compile
> time, as computing the trace information is quadratic in the number of
> instructions in a BB and it's relevant successors/predecessors.
>
> In most cases, knowing the instruction depth should be enough to make
> combination decisions. As we already iterate over all instructions in a basic
> block, the instruction depth can be computed incrementally. This reduces the
> cost of machine-combine drastically in cases where lots of instructions
> are combined. The major drawback is that AFAIK, computing the critical path
> length cannot be done incrementally. Therefore we only compute
> instruction depths incrementally, for basic blocks with more
> instructions than inc_threshold. The -machine-combiner-inc-threshold
> option can be used to set the threshold and allows for easier
> experimenting and checking if using incremental updates for all basic
> blocks has any impact on the performance.
>
> Reviewers: sanjoy, Gerolf, MatzeB, efriedma, fhahn
>
> Reviewed By: fhahn
>
> Subscribers: kiranchandramohan, javed.absar, efriedma, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D36619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313213
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Adrian Prantl [Wed, 13 Sep 2017 23:16:13 +0000 (23:16 +0000)]
Use MemoryBufferRef. (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313212
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Adrian Prantl [Wed, 13 Sep 2017 23:07:24 +0000 (23:07 +0000)]
Factor out duplicate code from llvm-dwarfdump (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313211
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Adrian Prantl [Wed, 13 Sep 2017 22:30:43 +0000 (22:30 +0000)]
Update testcase that was XFAILed on Darwin for llvm-dwarfdump change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313209
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Stanislav Mekhanoshin [Wed, 13 Sep 2017 22:20:47 +0000 (22:20 +0000)]
Allow target to decide when to cluster loads/stores in misched
MachineScheduler when clustering loads or stores checks if base
pointers point to the same memory. This check is done through
comparison of base registers of two memory instructions. This
works fine when instructions have separate offset operand. If
they require a full calculated pointer such instructions can
never be clustered according to such logic.
Changed shouldClusterMemOps to accept base registers as well and
let it decide what to do about it.
Differential Revision: https://reviews.llvm.org/D37698
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313208
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Adrian Prantl [Wed, 13 Sep 2017 22:09:01 +0000 (22:09 +0000)]
llvm-dwarfdump: automatically dump both regular and .dwo variant of sections
Since users typically don't really care about the .dwo / non.dwo
distinction, this patch makes it so dwarfdump --debug-<info,...> dumps
.debug_info and (if available) also .debug_info.dwo. This simplifies
the command line interface (I've removed all dwo-specific dump
options) and makes the tool friendlier to use.
Differential Revision: https://reviews.llvm.org/D37771
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313207
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Matt Arsenault [Wed, 13 Sep 2017 21:55:52 +0000 (21:55 +0000)]
AMDGPU: Handle coldcc in more places
Missed in r312936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313205
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Reid Kleckner [Wed, 13 Sep 2017 21:54:20 +0000 (21:54 +0000)]
[codeview] VLAs and unsized arrays should use a size of zero
Previously we used a size of '1' for VLAs because we weren't sure what
MSVC did. However, MSVC does support declaring an array without a size,
for which it emits an array type with a size of zero. Clang emits the
same DI metadata for VLAs and arrays without bound, so we would describe
arrays without bound as having one element. This lead to Microsoft
debuggers only printing a single element.
Emitting a size of zero appears to cause these debuggers to search the
symbol information to find a definition of the variable with accurate
array bounds.
Fixes http://crbug.com/763580
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313203
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Dehao Chen [Wed, 13 Sep 2017 21:49:36 +0000 (21:49 +0000)]
Update the early_inline test to explicitly add attribute for all functions. (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313202
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Eli Friedman [Wed, 13 Sep 2017 21:48:00 +0000 (21:48 +0000)]
[ARM] Add more CPUs to host detection
This returns "cortex-a73" for second-generation Kryo; not precisely
correct, but close enough.
Differential Revision: https://reviews.llvm.org/D37724
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313200
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Wei Mi [Wed, 13 Sep 2017 21:47:13 +0000 (21:47 +0000)]
Add a comment for the test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313199
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Eugene Zelenko [Wed, 13 Sep 2017 21:43:53 +0000 (21:43 +0000)]
[Transforms] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313198
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Wei Mi [Wed, 13 Sep 2017 21:41:30 +0000 (21:41 +0000)]
[RegAlloc] Keep a copy of live interval for the spilled vregs in HoistSpillHelper.
This is to fix PR34502. After rL311401, the live range of spilled vreg will be
cleared. HoistSpill need to use the live range of the original vreg before splitting
to know the moving range of the spills. The patch saves a copy of live interval for
the spilled vreg inside of HoistSpillHelper.
Differential Revision: https://reviews.llvm.org/D37578
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313197
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Vedant Kumar [Wed, 13 Sep 2017 21:40:59 +0000 (21:40 +0000)]
[Bitcode] Add a compatibility test for 5.0.0 bitcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313196
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Dehao Chen [Wed, 13 Sep 2017 21:22:55 +0000 (21:22 +0000)]
Invoke GetInlineCost for legality check before inline functions in SampleProfileLoader.
Summary: SampleProfileLoader inlines hot functions if it is inlined in the profiled binary. However, the inline needs to be guarded by legality check, otherwise it could lead to correctness issues.
Reviewers: eraman, davidxl
Reviewed By: eraman
Subscribers: sanjoy, llvm-commits
Differential Revision: https://reviews.llvm.org/D37779
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313195
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Eugene Zelenko [Wed, 13 Sep 2017 21:15:20 +0000 (21:15 +0000)]
[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313194
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Kevin Enderby [Wed, 13 Sep 2017 21:01:49 +0000 (21:01 +0000)]
Fix a crash in llvm-nm for a bad Mach-O file that has an N_SECT type symbol and a zero n_sect value.
The code in llvm-nm for Mach-O files to determine the section type for an
N_SECT type symbol it will call getSymbolSection() and check for the error,
but in the case the n_sect value is zero it will return section_end() (aka nullptr).
And the code was using that and crashing instead of just returning a ’s’ for a
section or printing (?,?) as it would if getSymbolSection() returned an error.
rdar://
33136604
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313193
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Adrian McCarthy [Wed, 13 Sep 2017 20:53:55 +0000 (20:53 +0000)]
Mark static member functions as static in CodeViewDebug
Summary:
To improve CodeView quality for static member functions, we need to make the
static explicit. In addition to a small change in LLVM's CodeViewDebug to
return the appropriate MethodKind, this requires a small change in Clang to
note the staticness in the debug info metadata.
Subscribers: aprantl, hiraditya
Differential Revision: https://reviews.llvm.org/D37715
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313192
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Zachary Turner [Wed, 13 Sep 2017 20:49:25 +0000 (20:49 +0000)]
Revert "Determine up front which projects are enabled."
This was intended to be a generic CMake solution to a problem
shared across several projects. It turns out it doesn't interact
very well certain CMake configurations, and furthermore the
"problem" is actually not a problem, as the problematic code
is never executed to begin with. So this really isn't solving
anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313191
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Easwaran Raman [Wed, 13 Sep 2017 20:16:02 +0000 (20:16 +0000)]
[Inliner] Add another way to compute full inline cost.
Summary:
Full inline cost is computed when -inline-cost-full is true or ORE is
non-null. This patch adds another way to compute full inline cost by
adding a field to InlineParams. This will be used by SampleProfileLoader
to check legality of inlining a callee that it wants to inline.
Reviewers: danielcdh, haicheng
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37819
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313185
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Anna Thomas [Wed, 13 Sep 2017 19:35:45 +0000 (19:35 +0000)]
[LV] Avoid computing the register usage for default VF. NFC
These are changes to reduce redundant computations when calculating a
feasible vectorization factor:
1. early return when target has no vector registers
2. don't compute register usage for the default VF.
Suggested during review for D37702.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313176
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Sanjoy Das [Wed, 13 Sep 2017 18:49:22 +0000 (18:49 +0000)]
Fix a misleading phrase in the LangRef
Reviewers: hfinkel, dberlin
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D37432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313170
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Michael Zuckerman [Wed, 13 Sep 2017 18:28:09 +0000 (18:28 +0000)]
Refactoring the stride 4 code in the X86interleavedaccess NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313166
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Adrian Prantl [Wed, 13 Sep 2017 18:22:59 +0000 (18:22 +0000)]
llvm-dwarfdump: support dumping UUIDs of Mach-O binaries.
This is a feature supported by Darwin dwarfdump. UUIDs are used to
associate executables with their .dSYM bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313165
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Brian Gesiak [Wed, 13 Sep 2017 18:02:11 +0000 (18:02 +0000)]
[CFG] Fix typo in docblock: blocsk/blocks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313164
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Vedant Kumar [Wed, 13 Sep 2017 18:00:22 +0000 (18:00 +0000)]
[unittests] Fix up test after rL313156
Bot: http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/42421
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313163
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Sanjay Patel [Wed, 13 Sep 2017 17:39:39 +0000 (17:39 +0000)]
[InstSimplify] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313161
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Simon Atanasyan [Wed, 13 Sep 2017 17:36:16 +0000 (17:36 +0000)]
[mips] Add unitests to check parsing MIPS triples. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313160
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Hiroshi Yamauchi [Wed, 13 Sep 2017 17:20:38 +0000 (17:20 +0000)]
Add options to dump PGO counts in text.
Summary:
Added text options to -pgo-view-counts and -pgo-view-raw-counts that dump block frequency and branch probability info in text.
This is useful when the graph is very large and complex (the dot command crashes, lines/edges too close to tell apart, hard to navigate without textual search) or simply when text is preferred.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313159
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Teresa Johnson [Wed, 13 Sep 2017 17:10:24 +0000 (17:10 +0000)]
[ThinLTO] AliasSummary should not have any references
Summary: References should only be on the aliasee.
Reviewers: pcc
Subscribers: llvm-commits, inglorion
Differential Revision: https://reviews.llvm.org/D37814
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313158
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Peter Collingbourne [Wed, 13 Sep 2017 17:09:20 +0000 (17:09 +0000)]
ThinLTO: Correctly follow aliasee references when dead stripping.
We were previously handling aliases during dead stripping by adding
the aliased global's "original name" GUID to the worklist. This will
lead to incorrect behaviour if the global has local linkage because
the original name GUID will not correspond to the global's GUID in
the summary.
Because an alias is just another name for the global that it
references, there is no need to mark the referenced global as used,
or to follow references from any other copies of the global. So all
we need to do is to follow references from the aliasee's summary
instead of the alias.
Differential Revision: https://reviews.llvm.org/D37789
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313157
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Alexander Kornienko [Wed, 13 Sep 2017 17:03:37 +0000 (17:03 +0000)]
Convenience/safety fix for llvm::sys::Execute(And|No)Wait
Summary:
Change the type of the Redirects parameter of llvm::sys::ExecuteAndWait,
ExecuteNoWait and other APIs that wrap them from `const StringRef **` to
`ArrayRef<Optional<StringRef>>`, which is safer and simplifies the use of these
APIs (no more local StringRef variables just to get a pointer to).
Corresponding clang changes will be posted as a separate patch.
Reviewers: bkramer
Reviewed By: bkramer
Subscribers: vsk, llvm-commits
Differential Revision: https://reviews.llvm.org/D37563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313155
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Teresa Johnson [Wed, 13 Sep 2017 15:35:35 +0000 (15:35 +0000)]
Fix bot failures by requiring x86 target in new test
The test added in r313151 requires a target triple since it is
running through code generation. Fix bot failures by requiring
an x86 target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313153
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Teresa Johnson [Wed, 13 Sep 2017 15:16:38 +0000 (15:16 +0000)]
[ThinLTO] For SamplePGO, need to handle ICP targets consistently in thin link
Summary:
SamplePGO indirect call profiles record the target as the original GUID
for statics. The importer had special handling to map to the normal GUID
in that case. The dead global analysis needs the same treatment or
inconsistencies arise, resulting in linker unsats due to some dead
symbols being exported and kept, leaving in references to other dead
symbols that are removed.
This can happen when a SamplePGO profile collected by one binary is used
for a different binary, so the indirect call profiles may not accurately
reflect live targets.
Reviewers: danielcdh
Subscribers: mehdi_amini, inglorion, llvm-commits, eraman
Differential Revision: https://reviews.llvm.org/D37783
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313151
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Petar Jovanovic [Wed, 13 Sep 2017 14:09:13 +0000 (14:09 +0000)]
[mips] correct operand range for DINSM instruction
This patch corrects the definition of the DINSM instruction.
Specification for DINSM instruction for Mips64 says that size operand should
be 2 <= size <= 64, but it is defined as uimm5_inssize_plus1 which gives
range of 1 .. 32.
Patch by Aleksandar Beserminji.
Differential Revision: https://reviews.llvm.org/D37683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313149
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Mikael Holmen [Wed, 13 Sep 2017 14:07:47 +0000 (14:07 +0000)]
[MachineScheduler] Put SchedRegion in an anonymous namespace.
Summary: It pollutes the global namespace otherwise.
Patch by: Bevin Hansson
Reviewers: jonpa
Reviewed By: jonpa
Subscribers: MatzeB, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D37555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313148
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Stefan Pintilie [Wed, 13 Sep 2017 14:05:27 +0000 (14:05 +0000)]
[Power9] Add missing instructions: extswsli, popcntb
Added the following P9 instructions: extswsli, extswsli., popcntb
Differential Revision: https://reviews.llvm.org/D37342
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313147
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Francis Ricci [Wed, 13 Sep 2017 13:57:45 +0000 (13:57 +0000)]
[llvm-objdump] Fix memory leaks in macho dump
Summary: Detected by LeakSanitizer for Darwin
Reviewers: enderby, rafael
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313146
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Jonas Devlieghere [Wed, 13 Sep 2017 13:43:01 +0000 (13:43 +0000)]
[MachO] Prevent heap overflow when load command extends past EOF
This patch fixes a heap-buffer-overflow when a malformed Mach-O has a
load command who's size extends past the end of the binary.
Fixes: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3225
Differential revision: https://reviews.llvm.org/D37439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313145
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Gadi Haber [Wed, 13 Sep 2017 12:39:18 +0000 (12:39 +0000)]
[X86][Skylake] Replacing -mcpu=skx by -mattr in a codegen test. NFC.
NFC.
Replacing -mcpu=skx by -mattr in the run command of the codegen test: avx512-gather-scatter-intrin.ll.
Reviewers: delena
Revision: https://reviews.llvm.org/D37799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313144
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Simon Pilgrim [Wed, 13 Sep 2017 11:21:38 +0000 (11:21 +0000)]
[X86][FMA4] Test FMA4 commutation with repeated ops as well as FMA3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313143
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Simon Pilgrim [Wed, 13 Sep 2017 11:12:56 +0000 (11:12 +0000)]
[X86][FMA] Added *213 fma instructions to scheduling tests
Annoyingly the 132/231 variants are pretty tricky to create when you need to due to weak FMA commutation patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313142
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Javed Absar [Wed, 13 Sep 2017 10:31:10 +0000 (10:31 +0000)]
[MiSched|TableGen] : Tidy up and modernise. NFC.
Replacing with range-based loop and substituting 'using'.
Reviewed by: @MatzeB
Differential Revision: https://reviews.llvm.org/D37748
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313140
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Jonas Devlieghere [Wed, 13 Sep 2017 09:43:05 +0000 (09:43 +0000)]
[dwarfdump] Rename Brief to Verbose in DIDumpOptions
This patches renames "brief" to "verbose" in de DIDumpOptions and
inverts the logic to match the new behavior where brief is the default.
Changing the default value uncovered some bugs related to the
DIDumpOptions not being propagated and have been fixed as well.
Differential revision: https://reviews.llvm.org/D37745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313139
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Gadi Haber [Wed, 13 Sep 2017 09:28:25 +0000 (09:28 +0000)]
[X86][Skylake][KNL] Updating code gen regression test to use the KNL and SKYLAKE prefixes. NFC.
NFC.
Updating the code gen regression test bmi2-schedule.ll to use the KNL and SKYLAKE prefixes for the run commands that use the knl and Skylake mcpu options.
The fix is in preparation for a large patch of adding all SKL scheduling information.
Reviewers: delena, zvi, RKSimon
Revision: https://reviews.llvm.org/D37796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313138
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Gadi Haber [Wed, 13 Sep 2017 09:28:18 +0000 (09:28 +0000)]
[X86][Skylake][KNL] Updating code gen regression test to use the KNL and SKYLAKE prefixes. NFC.
NFC.
Updating the code gen regression test bmi2-schedule.ll to use the KNL and SKYLAKE prefixes for the run commands that use the knl and Skylake mcpu options.
The fix is in preparation for a large patch of adding all SKL scheduling information.
Reviewers: delena, zvi
Revision: https://reviews.llvm.org/D37796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313137
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Gadi Haber [Wed, 13 Sep 2017 09:27:39 +0000 (09:27 +0000)]
NFC.
Updating codegen test bmi2-schedule.ll to use the SKYLAKE and KNL prefix as preparatipn for an upcoming patch to add all SKL scheduling information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313136
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Igor Breger [Wed, 13 Sep 2017 09:05:23 +0000 (09:05 +0000)]
[GlobalISel][X86] support G_FPEXT operation.
Summary: Support G_FPEXT operation. Selection done via TableGen'erated code.
Reviewers: zvi, guyblank, aymanmus, m_zuckerman
Reviewed By: zvi
Subscribers: rovka, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D34816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313135
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Uriel Korach [Wed, 13 Sep 2017 09:02:36 +0000 (09:02 +0000)]
[X86] [PATCH] [intrinsics] Lowering X86 ABS intrinsics to IR. (llvm)
This patch, together with a matching clang patch (https://reviews.llvm.org/D37694), implements the lowering of X86 ABS intrinsics to IR.
differential revision: https://reviews.llvm.org/D37693.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313134
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Mohammed Agabaria [Wed, 13 Sep 2017 09:00:27 +0000 (09:00 +0000)]
[X86] Adding X86 Processor Families
Adding x86 Processor families to initialize several uArch properties (based on the family)
This patch shows how gather cost can be initialized based on the proc. family
Differential Revision: https://reviews.llvm.org/D35348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313132
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Uriel Korach [Wed, 13 Sep 2017 08:33:55 +0000 (08:33 +0000)]
[X86] Add explicit mc-encoding checks to X86/viabs.ll. NFC.
Add explicit mc-encoding checks showing that the AVX512VL ABS intrinsics are actually mapped to EVEX encoding.
This is a pre-commit for a soon to come patch which will lower x86 target specific ABS intrinsics to IR.
Differential Revision: https://reviews.llvm.org/D37688
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313131
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Craig Topper [Wed, 13 Sep 2017 07:53:21 +0000 (07:53 +0000)]
[X86] Make sure we emit a SUBREG_TO_REG after the MOV32ri when creating a BEXTR64rr instruction from a shift/and pair.
Fixes PR34589.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313126
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Elena Demikhovsky [Wed, 13 Sep 2017 06:40:26 +0000 (06:40 +0000)]
[X86 CodeGen] Optimization of ZeroExtendLoad for v2i8 vector
Load with zero-extend and sign-extend from v2i8 to v2i32 is "Legal" since SSE4.1 and may be performed using PMOVZXBD , PMOVSXBD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313121
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Ayal Zaks [Wed, 13 Sep 2017 06:28:37 +0000 (06:28 +0000)]
[LV] Fix PR34523 - avoid generating redundant selects
When converting a PHI into a series of 'select' instructions to combine the
incoming values together according their edge masks, initialize the first
value to the incoming value In0 of the first predecessor, instead of
generating a redundant assignment 'select(Cond[0], In0, In0)'. The latter
fails when the Cond[0] mask is null, representing a full mask, which can
happen only when there's a single incoming value.
No functional changes intended nor expected other than surviving null Cond[0]'s.
This fix follows D35725, which introduced using null to represent full masks.
Differential Revision: https://reviews.llvm.org/D37619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313119
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Aditya Kumar [Wed, 13 Sep 2017 05:28:03 +0000 (05:28 +0000)]
[GVNHoist] Factor out reachability to search for anticipable instructions quickly
Factor out the reachability such that multiple queries to find reachability of values are fast. This is based on finding
the ANTIC points
in the CFG which do not change during hoisting. The ANTIC points are basically the dominance-frontiers in the inverse
graph. So we introduce a data structure (CHI nodes)
to keep track of values flowing out of a basic block. We only do this for values with multiple occurrences in the
function as they are the potential hoistable candidates.
This patch allows us to hoist instructions to a basic block with >2 successors, as well as deal with infinite loops in a
trivial way.
Relevant test cases are added to show the functionality as well as regression fixes from PR32821.
Regression from previous GVNHoist:
We do not hoist fully redundant expressions because fully redundant expressions are already handled by NewGVN
Differential Revision: https://reviews.llvm.org/D35918
Reviewers: dberlin, sebpop, gberry,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313116
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Petr Hosek [Wed, 13 Sep 2017 03:04:50 +0000 (03:04 +0000)]
[llvm-objcopy] Add e_machine validity check for reserved section indexes
As discussed on llvm-commits it was decided it would be best to check
e_machine before declaring that a reserved section index is valid. The
only special e_machine value that matters here is EM_HEXAGON. This
change adds a special check for EM_HEXAGON.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D37767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313114
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Craig Topper [Wed, 13 Sep 2017 02:29:59 +0000 (02:29 +0000)]
[X86] Use isUInt<32> to simplify some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313112
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Reid Kleckner [Wed, 13 Sep 2017 01:50:27 +0000 (01:50 +0000)]
Fix dwarfdump cmdline test on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313110
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Leslie Zhai [Wed, 13 Sep 2017 01:49:49 +0000 (01:49 +0000)]
[ARC] Prepare the implementation of relocation for LLD
Reviewers: ruiu, kparzysz, petecoup, rafael
Reviewed By: kparzysz
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313109
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Reid Kleckner [Wed, 13 Sep 2017 01:43:25 +0000 (01:43 +0000)]
[InstCombine] Add a flag to disable LowerDbgDeclare
Summary:
This should improve optimized debug info for address-taken variables at
the cost of inaccurate debug info in some situations.
We patched this into clang and deployed this change to Chromium
developers, and this significantly improved debuggability of optimized
code. The long-term solution to PR34136 seems more and more like it's
going to take a while, so I would like to commit this change under a
flag so that it can be used as a stop-gap measure.
This flag should really help so for C++ aggregates like std::string and
std::vector, which are typically address-taken, even after inlining, and
cannot be SROA-ed.
Reviewers: aprantl, dblaikie, probinson, dberlin
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D36596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313108
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Petr Hosek [Wed, 13 Sep 2017 01:18:06 +0000 (01:18 +0000)]
[Fuchsia] Magenta -> Zircon
Fuchsia's lowest API layer has been renamed from Magenta to Zircon.
In LLVM proper, this is only mentioned in comments.
Patch by Roland McGrath
Differential Revision: https://reviews.llvm.org/D37763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313105
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Derek Schuff [Wed, 13 Sep 2017 00:29:06 +0000 (00:29 +0000)]
[WebAssembly] Add sign extend instructions from atomics proposal
Select them from ISD::SIGN_EXTEND_INREG
Differential Revision: https://reviews.llvm.org/D37603
remove spurious change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313101
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Peter Collingbourne [Tue, 12 Sep 2017 23:40:19 +0000 (23:40 +0000)]
Add Linux target triple to hopefully fix Mac bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313093
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Zachary Turner [Tue, 12 Sep 2017 23:32:34 +0000 (23:32 +0000)]
Determine up front which projects are enabled.
Some projects need to add conditional dependencies on other projects.
compiler-rt is already doing this, and I attempted to add this to
debuginfo-tests when I ran into the ordering problem, that you can't
conditionally add a dependency unless that dependency's CMakeLists.txt
has already been run (which would allow you to say if (TARGET foo).
The solution to this seems to be to determine very early on the entire
set of projects which is enabled. This is complicated by the fact that
there are multiple ways to enable projects, and different tree layouts
(e.g. mono-repo, out of -tree, external, etc). This patch attempts to
centralize all of this into one place, and then updates compiler-rt to
demonstrate as a proof of concept how this can simplify code.
Differential Revision: https://reviews.llvm.org/D37637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313091
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Sanjay Patel [Tue, 12 Sep 2017 23:28:11 +0000 (23:28 +0000)]
[SimplifyCFG] update test comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313090
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Sanjay Patel [Tue, 12 Sep 2017 23:24:05 +0000 (23:24 +0000)]
[x86] eliminate unnecessary vector compare for AVX masked store
The masked store instruction only cares about the sign-bit of each mask element,
so the compare s<0 isn't needed.
As noted in PR11210:
https://bugs.llvm.org/show_bug.cgi?id=11210
...fixing this should allow us to eliminate x86-specific masked store intrinsics in IR.
(Although more testing will be needed to confirm that.)
I filed a bug to track improvements for AVX512:
https://bugs.llvm.org/show_bug.cgi?id=34584
Differential Revision: https://reviews.llvm.org/D37446
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313089
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Adrian Prantl [Tue, 12 Sep 2017 22:32:53 +0000 (22:32 +0000)]
Clean up the --help output of llvm-dwarfdump by hiding irrelevant options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313085
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Dehao Chen [Tue, 12 Sep 2017 21:55:55 +0000 (21:55 +0000)]
Refactor the code to pass down ACT to SampleProfileLoader correctly.
Summary: This change passes down ACT to SampleProfileLoader for the new PM. Also remove the default value for SampleProfileLoader class as it is not used.
Reviewers: eraman, davidxl
Reviewed By: eraman
Subscribers: sanjoy, llvm-commits
Differential Revision: https://reviews.llvm.org/D37773
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313080
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Peter Collingbourne [Tue, 12 Sep 2017 21:50:55 +0000 (21:50 +0000)]
Remove -generate-dwarf-pub-sections flag.
This flag is unnecessary for testing because we can get the coverage
we need by adjusting CU attributes.
Differential Revision: https://reviews.llvm.org/D37725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313079
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Peter Collingbourne [Tue, 12 Sep 2017 21:50:41 +0000 (21:50 +0000)]
IR: Represent -ggnu-pubnames with a flag on the DICompileUnit.
This allows the flag to be persisted through to LTO.
Differential Revision: https://reviews.llvm.org/D37655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313078
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Petar Jovanovic [Tue, 12 Sep 2017 21:43:33 +0000 (21:43 +0000)]
[mips] handle UImm16_AltRelaxed match type
Currently, UImm16_AltRelaxed match type is not handled in
MatchAndEmitInstruction() function, which may result in
llvm_unreachable() behavior.
This patch adds necessary case for this match type.
Patch by Aleksandar Beserminji.
Differential Revision: https://reviews.llvm.org/D37682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313077
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Alina Sbirlea [Tue, 12 Sep 2017 21:18:44 +0000 (21:18 +0000)]
Make promoteLoopAccessesToScalars independent of AliasSet [NFC]
Summary:
The current promoteLoopAccessesToScalars method receives an AliasSet, but
the information used is in fact a list of Value*, known to must alias.
Create the list ahead of time to make this method independent of the AliasSet class.
While there is no functionality change, this adds overhead for creating
a set of Value*, when promotion would normally exit earlier.
This is meant to be as a first refactoring step in order to start replacing
AliasSetTracker with MemorySSA.
And while the end goal is to redesign LICM, the first few steps will focus on
adding MemorySSA as an alternative to the AliasSetTracker using most of the
existing functionality.
Reviewers: mkuper, danielcdh, dberlin
Subscribers: sanjoy, chandlerc, gberry, davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D35439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313075
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Ahmed Bougacha [Tue, 12 Sep 2017 21:04:11 +0000 (21:04 +0000)]
[AArch64][GlobalISel] Select all fpexts.
Tablegen already can select these: mark them as legal, remove the
c++ code, and add tests for all types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313074
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Ahmed Bougacha [Tue, 12 Sep 2017 21:04:10 +0000 (21:04 +0000)]
[AArch64][GlobalISel] Select all fptruncs.
We already support these in tablegen, but we're matching the wrong
operator (libm ftrunc). Fix that.
While there, drop the c++ code, support COPYs of FPR16, and add tests
for the other types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313073
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Roman Lebedev [Tue, 12 Sep 2017 18:59:21 +0000 (18:59 +0000)]
[sancov] coverage-report-server.py: ServerHandler(): open file as UTF8
Summary:
This is nessesary in Python3. Everywhere else we assume that
encoding is UTF8. If we don't specify it here, the defaults
from the environment will be used, which may result in ASCII
decoder being used. And if the file is non-ASCII, then it
will crash:
```
File "/usr/local/bin/coverage-report-server.py", line 168, in do_GET
for line_no, line in enumerate(f, start=1)])
File "/usr/local/bin/coverage-report-server.py", line 165, in <listcomp>
["<span class='{cls}'>{line} </span>".format(
File "/usr/lib/python3.5/encodings/ascii.py", line 26, in decode
return codecs.ascii_decode(input, self.errors)[0]
UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position 106: ordinal not in range(128)
```
Fixes https://bugs.llvm.org/show_bug.cgi?id=33548
Now, how would i add a testcase here?
Reviewers: m.ostapenko, kcc
Reviewed By: kcc
Subscribers: kcc, llvm-commits
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D37661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313063
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Lei Huang [Tue, 12 Sep 2017 18:39:11 +0000 (18:39 +0000)]
Update branch coalescing to be a PowerPC specific pass
Implementing this pass as a PowerPC specific pass. Branch coalescing utilizes
the analyzeBranch method which currently does not include any implicit operands.
This is not an issue on PPC but must be handled on other targets.
Pass is currently off by default. Enabled via -enable-ppc-branch-coalesce.
Differential Revision : https: // reviews.llvm.org/D32776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313061
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Sam Clegg [Tue, 12 Sep 2017 18:31:24 +0000 (18:31 +0000)]
[WebAssembly] Remove flags from MCSectionWasm
Looks like these were copied from the ELF sections but
don't apply to Wasm and were not used anywhere.
Also remove unused Wasm methods in MCContext.
Differential Revision: https://reviews.llvm.org/D37633
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313058
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Robert Lougher [Tue, 12 Sep 2017 18:23:15 +0000 (18:23 +0000)]
Revert "[DWARF] Incorrect prologue end line record."
This reverts commit r313047 as it is causing buildbot failure (lldb inline
stepping tests).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313057
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Yonghong Song [Tue, 12 Sep 2017 17:55:23 +0000 (17:55 +0000)]
bpf: Add BPF AsmParser support in LLVM
Reviewed-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313055
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Craig Topper [Tue, 12 Sep 2017 17:40:25 +0000 (17:40 +0000)]
[X86] Move matching of (and (srl/sra, C), (1<<C) - 1) to BEXTR/BEXTRI instruction to custom isel
Recognizing this pattern during DAG combine hides information about the 'and' and the shift from other combines. I think it should be recognized at isel so its as late as possible. But it can't be done with table based isel because you need to be able to look at both immediates. This patch moves it to custom isel in X86ISelDAGToDAG.cpp.
This does break a couple tests in tbm_patterns because we are now emitting an and_flag node or (cmp and, 0) that we dont' recognize yet. We already had this problem for several other TBM patterns so I think this fine and we can address of them together.
I've also fixed a bug where the combine to BEXTR was preventing us from using a trick of zero extending AH to handle extracts of bits 15:8. We might still want to use BEXTR if it enables load folding. But honestly I hope we narrowed the load instead before got to isel.
I think we should probably also support matching BEXTR from (srl/srl (and mask << C), C). But that should be a different patch.
Differential Revision: https://reviews.llvm.org/D37592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313054
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Elena Demikhovsky [Tue, 12 Sep 2017 17:27:53 +0000 (17:27 +0000)]
Added "zext" from v2i8 to v2i32. In the next patch I'll optimize the sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313052
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Robert Lougher [Tue, 12 Sep 2017 16:35:25 +0000 (16:35 +0000)]
[DWARF] Incorrect prologue end line record.
A prologue-end line record is emitted with an incorrect associated address,
which causes a debugger to show the beginning of function body to be inside
the prologue.
Patch written by Carlos Alberto Enciso.
Differential Revision: https://reviews.llvm.org/D37625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313047
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Anna Thomas [Tue, 12 Sep 2017 16:32:45 +0000 (16:32 +0000)]
[LV] Clamp the VF to the trip count
Summary:
When the MaxVectorSize > ConstantTripCount, we should just clamp the
vectorization factor to be the ConstantTripCount.
This vectorizes loops where the TinyTripCountThreshold >= TripCount < MaxVF.
Earlier we were finding the maximum vector width, which could be greater than
the trip count itself. The Loop vectorizer does all the work for generating a
vectorizable loop, but in the end we would always choose the scalar loop (since
the VF > trip count). This allows us to choose the VF keeping in mind the trip
count if available.
This is a fix on top of rL312472.
Reviewers: Ayal, zvi, hfinkel, dneilson
Reviewed by: Ayal
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313046
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Hans Wennborg [Tue, 12 Sep 2017 16:24:17 +0000 (16:24 +0000)]
Revert r313009 "[ARM] Use ADDCARRY / SUBCARRY"
This was causing PR34045 to fire again.
> This is a preparatory step for D34515 and also is being recommitted as its
> first version caused PR34045.
>
> This change:
> - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32
> - lowering is done by first converting the boolean value into the carry flag
> using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value
> using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two
> operations does the actual addition.
> - for subtraction, given that ISD::SUBCARRY second result is actually a
> borrow, we need to invert the value of the second operand and result before
> and after using ARMISD::SUBE. We need to invert the carry result of
> ARMISD::SUBE to preserve the semantics.
> - given that the generic combiner may lower ISD::ADDCARRY and
> ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering
> as well otherwise i64 operations now would require branches. This implies
> updating the corresponding test for unsigned.
> - add new combiner to remove the redundant conversions from/to carry flags
> to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C
> - fixes PR34045
>
> Differential Revision: https://reviews.llvm.org/D35192
Also revert follow-up r313010:
> [ARM] Fix typo when creating ISD::SUB nodes
>
> In D35192, I accidentally introduced a typo when creating ISD::SUB nodes,
> giving them two values instead of one.
>
> This fails when the merge_values combiner finds one of these nodes.
>
> This change fixes PR34564.
>
> Differential Revision: https://reviews.llvm.org/D37690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313044
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Alexey Bataev [Tue, 12 Sep 2017 16:15:04 +0000 (16:15 +0000)]
[SLP] Test with mutiple uses of conditional op and wrong parent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313042
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Adrian Prantl [Tue, 12 Sep 2017 16:10:24 +0000 (16:10 +0000)]
Statically assert that enum items don't overflow storage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313041
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Simon Pilgrim [Tue, 12 Sep 2017 15:52:01 +0000 (15:52 +0000)]
[X86][AVX2] Add gather/movntdqa/pmaskmov/pmovmskb/pslldq/psrldq instructions to scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313039
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Krzysztof Parzyszek [Tue, 12 Sep 2017 15:47:31 +0000 (15:47 +0000)]
Remove ancient, commented out code from TableGen, NFC
These pieces were commented out in r98534 and r129691, i.e. 6+ years ago.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313038
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Krzysztof Parzyszek [Tue, 12 Sep 2017 15:31:26 +0000 (15:31 +0000)]
Formatting changes, add LLVM_DUMP_METHOD to a dump function, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313037
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Sanjay Patel [Tue, 12 Sep 2017 15:29:28 +0000 (15:29 +0000)]
[InstCombine] move related tests together; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313036
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Alexey Bataev [Tue, 12 Sep 2017 15:13:50 +0000 (15:13 +0000)]
[SLP] Fix for PHINode during horizontal reduction scanning, NFC.
Reduces number of loops during instructions analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313035
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Simon Pilgrim [Tue, 12 Sep 2017 15:01:20 +0000 (15:01 +0000)]
[X86][AVX2] Add further instructions to scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313032
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Krzysztof Parzyszek [Tue, 12 Sep 2017 14:10:48 +0000 (14:10 +0000)]
Fix a couple of comments, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313030
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Simon Pilgrim [Tue, 12 Sep 2017 12:59:20 +0000 (12:59 +0000)]
[X86][AVX2] Add integer broadcast scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313026
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Jonas Paulsson [Tue, 12 Sep 2017 12:11:29 +0000 (12:11 +0000)]
[SystemZ] Add the CoveredBySubRegs bit to GPR64, GPR128 and FPR128 registers.
This bit is needed in order for the CalleeSavedRegs list to automatically
include the super registers if all of their subregs are present.
Thanks to Wei Mi for initially indicating this deficiency in the SystemZ
backend.
Review: Ulrich Weigand.
https://bugs.llvm.org/show_bug.cgi?id=34550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313023
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Simon Pilgrim [Tue, 12 Sep 2017 11:17:01 +0000 (11:17 +0000)]
[X86][AVX2] Add additional fp-broadcast/subvector/shuffle scheduling tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313022
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Simon Pilgrim [Tue, 12 Sep 2017 11:10:59 +0000 (11:10 +0000)]
[X86][AVX] Add vperm2f128 scheduling test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313021
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Simon Pilgrim [Tue, 12 Sep 2017 11:09:30 +0000 (11:09 +0000)]
[X86][AVX2] Remove old (unused) intrinsic declarations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313020
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