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Bjorn Pettersson [Tue, 3 Jul 2018 12:39:52 +0000 (12:39 +0000)]
[IR] Strip trailing whitespace. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336194
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Sjoerd Meijer [Tue, 3 Jul 2018 12:09:20 +0000 (12:09 +0000)]
[AArch64] Armv8.4-A: system registers
This adds the following system registers:
- RAS registers,
- MPAM registers,
- Activitiy monitor registers,
- Trace Extension registers,
- Timing insensitivity of data processing instructions,
- Enhanced Support for Nested Virtualization.
Differential Revision: https://reviews.llvm.org/D48871
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336193
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Hans Wennborg [Tue, 3 Jul 2018 11:30:01 +0000 (11:30 +0000)]
build_llvm_package.bat: Re-try the build steps
The build on Windows has been extra flaky recently; retrying helps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336192
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Bjorn Pettersson [Tue, 3 Jul 2018 11:29:00 +0000 (11:29 +0000)]
[DebugInfo] Corrections for salvageDebugInfo
Summary:
When salvaging a dbg.declare/dbg.addr we should not add
DW_OP_stack_value to the DIExpression
(see test/Transforms/InstCombine/salvage-dbg-declare.ll).
Consider this example
%vla = alloca i32, i64 2
call void @llvm.dbg.declare(metadata i32* %vla, metadata !1, metadata !DIExpression())
Instcombine will turn it into
%vla1 = alloca [2 x i32]
%vla1.sub = getelementptr inbounds [2 x i32], [2 x i32]* %vla, i64 0, i64 0
call void @llvm.dbg.declare(metadata [2 x i32]* %vla1.sub, metadata !19, metadata !DIExpression())
If the GEP can be eliminated, then the dbg.declare will be salvaged
and we should get
%vla1 = alloca [2 x i32]
call void @llvm.dbg.declare(metadata [2 x i32]* %vla1, metadata !19, metadata !DIExpression())
The problem was that salvageDebugInfo did not recognize dbg.declare
as being indirect (%vla1 points to the value, it does not hold the
value), so we incorrectly got
call void @llvm.dbg.declare(metadata [2 x i32]* %vla1, metadata !19, metadata !DIExpression(DW_OP_stack_value))
I also made sure that llvm::salvageDebugInfo and
DIExpression::prependOpcodes do not add DW_OP_stack_value to
the DIExpression in case no new operands are added to the
DIExpression. That way we avoid to, unneccessarily, turn a
register location expression into an implicit location expression
in some situations (see test11 in test/Transforms/LICM/sinking.ll).
Reviewers: aprantl, vsk
Reviewed By: aprantl, vsk
Subscribers: JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D48837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336191
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Benjamin Kramer [Tue, 3 Jul 2018 11:15:17 +0000 (11:15 +0000)]
Revert "[X86][SSE] Blend any v8i16/v4i32 shift with 2 shift unique values"
This reverts commit r336113. It causes crashes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336189
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John Brawn [Tue, 3 Jul 2018 10:52:20 +0000 (10:52 +0000)]
[llvm-exegesis] Adjust AArch64 unit test
The signature of setRegToConstant changed in r336171, so adjust the AArch64
unit test in a similar way to how the X86 unit test was changed in that commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336188
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John Brawn [Tue, 3 Jul 2018 10:10:29 +0000 (10:10 +0000)]
[llvm-exegesis] Add an AArch64 target
The target does just enough to be able to run llvm-exegesis in latency mode for
at least some opcodes.
Differential Revision: https://reviews.llvm.org/D48780
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336187
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Sander de Smalen [Tue, 3 Jul 2018 09:48:22 +0000 (09:48 +0000)]
[AArch64][SVE] Asm: Support for saturing ADD/SUB instructions.
The variants added are:
signed Saturating ADD/SUB (immediate) e.g. sqadd z0.h, z0.h, #42
unsigned Saturating ADD/SUB (immediate) e.g. uqadd z0.h, z0.h, #42
signed Saturating ADD/SUB (vectors) e.g. sqadd z0.h, z0.h, z1.h
unsigned Saturating ADD/SUB (vectors) e.g. uqadd z0.h, z0.h, z1.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336186
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Petar Jovanovic [Tue, 3 Jul 2018 09:31:48 +0000 (09:31 +0000)]
[MIPS GlobalISel] Lower arguments using stack
Lower more than 4 arguments using stack. This patch targets MIPS32.
It supports only functions with arguments of type i32.
Patch by Petar Avramovic.
Differential Revision: https://reviews.llvm.org/D47934
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336185
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Chandler Carruth [Tue, 3 Jul 2018 09:13:27 +0000 (09:13 +0000)]
[PM/LoopUnswitch] Fix PR37651 by correctly invalidating SCEV when
unswitching loops.
Original patch trying to address this was sent in D47624, but that
didn't quite handle things correctly. There are two key principles used
to select whether and how to invalidate SCEV-cached information about
loops:
1) We must invalidate any info SCEV has cached before unswitching as we
may change (or destroy) the loop structure by the act of unswitching,
and make it hard to recover everything we want to invalidate within
SCEV.
2) We need to invalidate all of the loops whose CFGs are mutated by the
unswitching. Notably, this isn't the *entire* loop nest, this is
every loop contained by the outermost loop reached by an exit block
relevant to the unswitch.
And we need to do this even when doing trivial unswitching.
I've added more focused tests that directly check that SCEV starts off
with imprecise information and after unswitching (and simplifying
instructions) re-querying SCEV will produce precise information. These
tests also specifically work to check that an *outer* loop's information
becomes precise.
However, the testing here is still a bit imperfect. Crafting test cases
that reliably fail to be analyzed by SCEV before unswitching and succeed
afterward proved ... very, very hard. It took me several hours and
careful work to build these, and I'm not optimistic about necessarily
coming up with more to cover more elaborate possibilities. Fortunately,
the code pattern we are testing here in the pass is really
straightforward and reliable.
Thanks to Max Kazantsev for the initial work on this as well as the
review, and to Hal Finkel for helping me talk through approaches to test
this stuff even if it didn't come to much.
Differential Revision: https://reviews.llvm.org/D47624
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336183
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Sander de Smalen [Tue, 3 Jul 2018 09:07:23 +0000 (09:07 +0000)]
[AArch64][SVE] Asm: Support for vector element FP compare.
Contains the following variants:
- Compare with (elements from) other vector
instructions: fcmeq, fcmgt, fcmge, fcmne, fcmuo.
aliases: fcmle, fcmlt.
e.g. fcmle p0.h, p0/z, z0.h, z1.h => fcmge p0.h, p0/z, z1.h, z0.h
- Compare absolute values with (absolute values from) other vector.
instructions: facge, facgt.
aliases: facle, faclt.
e.g. facle p0.h, p0/z, z0.h, z1.h => facge p0.h, p0/z, z1.h, z0.h
- Compare vector elements with #0.0
instructions: fcmeq, fcmgt, fcmge, fcmle, fcmlt, fcmne.
e.g. fcmle p0.h, p0/z, z0.h, #0.0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336182
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Chandler Carruth [Tue, 3 Jul 2018 08:19:10 +0000 (08:19 +0000)]
[ADT] Disable the single callback optimization on Windows.
It appears that the function pointer we use there isn't reliably 4-byte
aligned. I have no idea why or how we could correct this, so for now we
just regress the Windows performance some.
Someone with access to Windows could try working on a fix. At the very
least we could use a double indirection rather than a table, but maybe
there is some way to fully restore this optimization. I don't want to
play too much with this when I don't have access to the platform and
this at least should restore the last bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336178
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Shiva Chen [Tue, 3 Jul 2018 07:56:04 +0000 (07:56 +0000)]
[DebugInfo] Fix PR37395.
DbgLabelInst has no address as its operands.
Differential Revision: https://reviews.llvm.org/D46738
Patch by Hsiangkai Wang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336176
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Chandler Carruth [Tue, 3 Jul 2018 07:51:01 +0000 (07:51 +0000)]
[Support] This sanity check in the test only works with certain versions
of libstdc++, not just certain versions of GCC. The original macros
broke when using Clang + libstdc++4.9 sadly.
Sadly, testing for versions of libstdc++ has been extremely problematic
in the past, so I'm just narrowing this down to Windows and when using
libc++ as that seems at least very unlikely to keep build bots broken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336174
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Max Kazantsev [Tue, 3 Jul 2018 06:23:57 +0000 (06:23 +0000)]
[InstCombine] Delay foldICmpUsingKnownBits until simple transforms are done
This patch changes order of transform in InstCombineCompares to avoid
performing transforms based on ranges which produce complex bit arithmetics
before more simple things (like folding with constants) are done. See PR37636
for the motivating example.
Differential Revision: https://reviews.llvm.org/D48584
Reviewed By: spatel, lebedev.ri
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336172
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Clement Courbet [Tue, 3 Jul 2018 06:17:05 +0000 (06:17 +0000)]
[llvm-exegesis] ExegisX86Target::setRegToConstant() should depend on the subtarget features.
Summary: This fixes PR38008.
Reviewers: gchatelet, RKSimon
Subscribers: tschuett, craig.topper, llvm-commits
Differential Revision: https://reviews.llvm.org/D48820
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336171
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Chandler Carruth [Tue, 3 Jul 2018 05:46:20 +0000 (05:46 +0000)]
[ADT] Try to work around a crash in MSVC.
Putting `sizeof(T) <= 16` into the parameter of a `std::conditional`
causes every version of MSVC I've tried to crash:
https://godbolt.org/g/eqVULL
Really frustrating, but an extra layer of indirection through an
instantiated type gives a working way to access this computed constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336170
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Craig Topper [Tue, 3 Jul 2018 04:43:49 +0000 (04:43 +0000)]
[X86] Add avx512vl command line to break-false-dep.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336169
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Chandler Carruth [Tue, 3 Jul 2018 04:07:26 +0000 (04:07 +0000)]
[ADT] Switch another place to `llvm::is_trivially_move_constructible`.
I missed this the first time around, sorry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336166
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Jakub Kuderski [Tue, 3 Jul 2018 02:06:23 +0000 (02:06 +0000)]
Reappl "[Dominators] Add the DomTreeUpdater class"
Summary:
This patch is the first in a series of patches related to the [[ http://lists.llvm.org/pipermail/llvm-dev/2018-June/123883.html | RFC - A new dominator tree updater for LLVM ]].
This patch introduces the DomTreeUpdater class, which provides a cleaner API to perform updates on available dominator trees (none, only DomTree, only PostDomTree, both) using different update strategies (eagerly or lazily) to simplify the updating process.
—Prior to the patch—
- Directly calling update functions of DominatorTree updates the data structure eagerly while DeferredDominance does updates lazily.
- DeferredDominance class cannot be used when a PostDominatorTree also needs to be updated.
- Functions receiving DT/DDT need to branch a lot which is currently necessary.
- Functions using both DomTree and PostDomTree need to call the update function separately on both trees.
- People need to construct an additional DeferredDominance class to use functions only receiving DDT.
—After the patch—
Patch by Chijun Sima <simachijun@gmail.com>.
Reviewers: kuhar, brzycki, dmgreen, grosser, davide
Reviewed By: kuhar, brzycki
Author: NutshellySima
Subscribers: vsk, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D48383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336163
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Erik Pilkington [Tue, 3 Jul 2018 01:30:53 +0000 (01:30 +0000)]
Revert r336159, r336157. Some bots failed on qualified std::max_align_t, and other on unqualified max_align_t.
I'll take another stab at this tomorrow. Any ideas for fixing this would be appreciated!
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/23071/steps/build_Lld/logs/stdio
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/11185/steps/build-stage1-compiler/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336162
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Chandler Carruth [Tue, 3 Jul 2018 01:18:21 +0000 (01:18 +0000)]
[Support] Fix llvm::unique_function when building with GCC 4.9 by
introducing llvm::trivially_{copy,move}_constructible type traits.
This uses a completely portable implementation of these traits provided
by Richard Smith. You can see it on compiler explorer in all its glory:
https://godbolt.org/g/QEDZjW
I have transcribed it, clang-formatted it, added some comments, and made
the tests fit into a unittest file.
I have also switched llvm::unique_function over to use these new, much
more portable traits. =D
Hopefully this will fix the build bot breakage from my prior commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336161
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Teresa Johnson [Tue, 3 Jul 2018 01:11:43 +0000 (01:11 +0000)]
[ThinLTO] Fix printing of aliases for distributed backend indexes
Summary:
When we import an alias (which will import a copy of the aliasee), but
aren't going to import the aliasee directly, the distributed backend
index will not contain the aliasee summary. Handle this in the summary
assembly printer by printing "null" as the aliasee.
Reviewers: davidxl, dexonsmith
Subscribers: mehdi_amini, inglorion, eraman, steven_wu, llvm-commits
Differential Revision: https://reviews.llvm.org/D48699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336160
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Erik Pilkington [Tue, 3 Jul 2018 00:48:27 +0000 (00:48 +0000)]
Some buildbots were choking on std::max_align_t, try using the global alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336159
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Erik Pilkington [Tue, 3 Jul 2018 00:23:18 +0000 (00:23 +0000)]
[demangler] Fix a MSVC alignment warning.
This should fix llvm.org/PR37944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336157
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Chandler Carruth [Mon, 2 Jul 2018 23:57:29 +0000 (23:57 +0000)]
[ADT] Add llvm::unique_function which is like std::function but
supporting move-only closures.
Most of the core optimizations for std::function are here plus
a potentially novel one that detects trivially movable and destroyable
functors and implements those with fewer indirections.
This is especially useful as we start trying to add concurrency
primitives as those often end up with move-only types (futures,
promises, etc) and wanting them to work through lambdas.
As further work, we could add better support for things like const-qualified
operator()s to support more algorithms, and r-value ref qualified operator()s
to model call-once. None of that is here though.
We can also provide our own llvm::function that has some of the optimizations
used in this class, but with copy semantics instead of move semantics.
This is motivated by increasing usage of things like executors and the task
queue where it is useful to embed move-only types like a std::promise within
a type erased function. That isn't possible without this version of a type
erased function.
Differential Revision: https://reviews.llvm.org/D48349
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336156
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Teresa Johnson [Mon, 2 Jul 2018 23:02:07 +0000 (23:02 +0000)]
Remove absolute path in test
My test change in r336148 accidentally included an absolute path, clean
that up to fix bot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336151
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Lang Hames [Mon, 2 Jul 2018 22:30:18 +0000 (22:30 +0000)]
[ORC] Verify modules when running LLLazyJIT in LLI, and deal with fallout.
The verifier identified several modules that were broken due to incorrect
linkage on declarations. To fix this, CompileOnDemandLayer2::extractFunction
has been updated to change decls to external linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336150
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Teresa Johnson [Mon, 2 Jul 2018 22:09:23 +0000 (22:09 +0000)]
[ThinLTO] Fix printing of module paths for distributed backend indexes
Summary:
In the individual index files emitted for distributed ThinLTO backends,
the module path ids are not contiguous. Assign slots to module paths in
order to handle this better and also to get contiguous numbering in the
summary assembly.
Reviewers: davidxl, dexonsmith
Subscribers: mehdi_amini, inglorion, eraman, llvm-commits, steven_wu
Differential Revision: https://reviews.llvm.org/D48698
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336148
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Heejin Ahn [Mon, 2 Jul 2018 21:22:59 +0000 (21:22 +0000)]
[WebAssembly] Support for atomic stores
Summary: Add support for atomic store instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D48839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336145
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Vadzim Dambrouski [Mon, 2 Jul 2018 21:05:26 +0000 (21:05 +0000)]
[ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m.
Reviewers: efriedma, rogfer01, javed.absar
Reviewed By: efriedma, rogfer01
Subscribers: kristof.beyls, chrib, llvm-commits
Differential Revision: https://reviews.llvm.org/D48846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336144
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Andrea Di Biagio [Mon, 2 Jul 2018 20:39:57 +0000 (20:39 +0000)]
[llvm-mca] Clear the content of map VariantDescriptors in InstrBuilder before we start analyzing a new CodeBlock. NFCI.
Different CodeBlocks don't overlap. The same MCInst cannot appear in more than
one code block because all blocks are instantiated before the simulation is run.
We should always clear the content of map VariantDescriptors before every
simulation, since VariantDescriptors cannot possibly store useful information
for the next blocks. It is also "safer" to clear its content because `MCInst*`
is used as the key type for map VariantDescriptors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336142
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Tim Shen [Mon, 2 Jul 2018 20:01:54 +0000 (20:01 +0000)]
[SCEV] Strengthen StrengthenNoWrapFlags (reapply r334428).
Summary:
Comment on Transforms/LoopVersioning/incorrect-phi.ll: With the change
SCEV is able to prove that the loop doesn't wrap-self (due to zext i16
to i64), disabling the entire loop versioning pass. Removed the zext and
just use i64.
Reviewers: sanjoy
Subscribers: jlebar, hiraditya, javed.absar, bixia, llvm-commits
Differential Revision: https://reviews.llvm.org/D48409
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336140
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Dan Gohman [Mon, 2 Jul 2018 19:45:57 +0000 (19:45 +0000)]
[WebAssembly] Fix fast-isel optimization of branch conditions.
LLVM doesn't guarantee anything about the high bits of a register holding
an i1 value at the IR level, so don't translate LLVM IR i1 values directly
into WebAssembly conditional branch operands. WebAssembly's conditional
branches do demand all 32 bits be valid.
Fixes PR38019.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336138
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Krzysztof Parzyszek [Mon, 2 Jul 2018 19:05:09 +0000 (19:05 +0000)]
[X86] Add phony registers for high halves of regs with low halves
Add registers still missing after r328016 (D43353):
- for bits 15-8 of SI, DI, BP, SP (*H), and R8-R15 (*BH),
- for bits 31-16 of R8-R15 (*WH).
Thanks to Craig Topper for pointing it out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336134
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Alina Sbirlea [Mon, 2 Jul 2018 18:53:40 +0000 (18:53 +0000)]
Replace "Replacable" with "Replaceable". [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336133
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Fangrui Song [Mon, 2 Jul 2018 18:16:44 +0000 (18:16 +0000)]
Replace unused output filenames with /dev/null in tests
Similar to rLLD336129
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336131
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Farhana Aleen [Mon, 2 Jul 2018 17:55:31 +0000 (17:55 +0000)]
[SLP] Recognize min/max pattern using instructions producing same values.
Summary: It is common to have the following min/max pattern during the intermediate stages of SLP since we only optimize at the end. This patch tries to catch such patterns and allow more vectorization.
%1 = extractelement <2 x i32> %a, i32 0
%2 = extractelement <2 x i32> %a, i32 1
%cond = icmp sgt i32 %1, %2
%3 = extractelement <2 x i32> %a, i32 0
%4 = extractelement <2 x i32> %a, i32 1
%select = select i1 %cond, i32 %3, i32 %4
Author: FarhanaAleen
Reviewed By: ABataev, RKSimon, spatel
Differential Revision: https://reviews.llvm.org/D47608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336130
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Sanjay Patel [Mon, 2 Jul 2018 17:42:29 +0000 (17:42 +0000)]
[InstCombine] reverse canonicalization of add --> or to allow more shuffle folding
This extends D48485 to allow another pair of binops (add/or) to be combined either
with or without a leading shuffle:
or X, C --> add X, C (when X and C have no common bits set)
Here, we need value tracking to determine that the 'or' can be reversed into an 'add',
and we've added general infrastructure to allow extending to other opcodes or moving
to where other passes could use that functionality.
Differential Revision: https://reviews.llvm.org/D48662
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336128
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Francis Visoiu Mistrih [Mon, 2 Jul 2018 17:29:43 +0000 (17:29 +0000)]
[MC] Error on a .zerofill directive in a non-virtual section
On darwin, all virtual sections have zerofill type, and having a
.zerofill directive in a non-virtual section is not allowed. Instead of
asserting, show a nicer error.
In order to use the equivalent of .zerofill in a non-virtual section,
the usage of .zero of .space is required.
This patch replaces the assert with an error.
Differential Revision: https://reviews.llvm.org/D48517
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336127
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Dave Lee [Mon, 2 Jul 2018 17:24:37 +0000 (17:24 +0000)]
nm: Add -no-weak flag for hiding weak symbols
Summary:
This adds a new -no-weak flag to nm to hide weak symbols in its output.
This also adds a -W alias for this which is analogous to -U.
Patch by Keith Smiley
Reviewers: kastiglione, enderby, compnerd
Reviewed By: kastiglione
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48751
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336126
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Simon Pilgrim [Mon, 2 Jul 2018 17:23:45 +0000 (17:23 +0000)]
[SLPVectorizer][X86] Begin adding alternate tests for call operators
Alternate opcode handling only supports binary operators, these tests demonstrate a missed opportunity to vectorize ceil/floor calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336125
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Vedant Kumar [Mon, 2 Jul 2018 17:08:36 +0000 (17:08 +0000)]
Tighten up a test for -check-debugify, NFC
Use an -implicit-check-not to make sure an error which should not occur
in fact does not occur before the first CHECK line.
Suggested by Paul Robinson in post-commit feedback for r335897.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336123
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Simon Pilgrim [Mon, 2 Jul 2018 17:07:01 +0000 (17:07 +0000)]
[CostModel][X86] Add cost tests for fp rounding intrinsics
Add cost tests for fp ceil, floor, nearbyint, rint and trunc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336122
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Craig Topper [Mon, 2 Jul 2018 17:01:54 +0000 (17:01 +0000)]
[X86] Don't use aligned load/store instructions for fp128 if the load/store isn't aligned.
Similarily, don't fold fp128 loads into SSE instructions if the load isn't aligned. Unless we're targeting an AMD CPU that doesn't check alignment on arithmetic instructions.
Should fix PR38001
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336121
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Amara Emerson [Mon, 2 Jul 2018 16:39:09 +0000 (16:39 +0000)]
[AArch64][GlobalISel] Any-extend vararg parameters to stack slot size on Darwin.
We currently don't any-extend vararg parameters before storing them to the stack
locations on Darwin. However, SelectionDAG however does this, and so user code
is in the wild which inadvertently relies on this extension. This can manifest
in cases where the value stored is (int)0, but the actual parameter is interpreted
by va_arg as a pointer, and so not extending to 64 bits causes the callee to
load additional undefined bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336120
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Jakub Kuderski [Mon, 2 Jul 2018 16:10:49 +0000 (16:10 +0000)]
Revert "[Dominators] Add the DomTreeUpdater class"
Temporary revert because of a failing test on some buildbots.
This reverts commit r336114.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336117
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Sam Clegg [Mon, 2 Jul 2018 16:03:49 +0000 (16:03 +0000)]
[WebAssembly] Convert remaining tests from elf to wasm output format
Differential Revision: https://reviews.llvm.org/D48748
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336116
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Sjoerd Meijer [Mon, 2 Jul 2018 15:38:37 +0000 (15:38 +0000)]
Follow up of r335953 - [ARM][AArch64] Armv8.4-A Enablement
Imply dotprod for armv8.4-a, because it is mandatory from v8.4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336115
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Jakub Kuderski [Mon, 2 Jul 2018 15:37:41 +0000 (15:37 +0000)]
[Dominators] Add the DomTreeUpdater class
Summary:
This patch is the first in a series of patches related to the [[ http://lists.llvm.org/pipermail/llvm-dev/2018-June/123883.html | RFC - A new dominator tree updater for LLVM ]].
This patch introduces the DomTreeUpdater class, which provides a cleaner API to perform updates on available dominator trees (none, only DomTree, only PostDomTree, both) using different update strategies (eagerly or lazily) to simplify the updating process.
—Prior to the patch—
- Directly calling update functions of DominatorTree updates the data structure eagerly while DeferredDominance does updates lazily.
- DeferredDominance class cannot be used when a PostDominatorTree also needs to be updated.
- Functions receiving DT/DDT need to branch a lot which is currently necessary.
- Functions using both DomTree and PostDomTree need to call the update function separately on both trees.
- People need to construct an additional DeferredDominance class to use functions only receiving DDT.
—After the patch—
Patch by Chijun Sima <simachijun@gmail.com>.
Reviewers: kuhar, brzycki, dmgreen, grosser, davide
Reviewed By: kuhar, brzycki
Subscribers: vsk, mgorny, llvm-commits
Author: NutshellySima
Differential Revision: https://reviews.llvm.org/D48383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336114
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Simon Pilgrim [Mon, 2 Jul 2018 15:14:07 +0000 (15:14 +0000)]
[X86][SSE] Blend any v8i16/v4i32 shift with 2 shift unique values
We were only doing this for basic blends, despite shuffle lowering now being good enough to handle more complex blends. This means that the two v8i16 splat shifts are performed in parallel instead of serially as the general shift case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336113
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Simon Pilgrim [Mon, 2 Jul 2018 14:53:41 +0000 (14:53 +0000)]
[X86][SSE] Add v8i16 shift test for 2 shift values that doesn't match basic blend
We have special case support for 2 shift values for basic blends, but irregular shift patterns end up using the generic lowering, despite shuffle lowering being good enough to handle more complex blends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336112
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Sanjay Patel [Mon, 2 Jul 2018 14:43:40 +0000 (14:43 +0000)]
[ValueTracking] allow undef elements when matching vector abs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336111
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Yaron Keren [Mon, 2 Jul 2018 14:39:32 +0000 (14:39 +0000)]
Disable failing test on x86_64-pc-windows-gnu, see PR38006.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336110
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David Stenberg [Mon, 2 Jul 2018 14:23:48 +0000 (14:23 +0000)]
[CodeGen] Make block removal order deterministic in CodeGenPrepare
Summary:
Replace use of a SmallPtrSet with a SmallSetVector to make the worklist
iteration order deterministic. This is done as the order the blocks are
removed may affect whether or not PHI nodes in successor blocks are
removed.
For example, consider the following case where %bb1 and %bb2 are
removed:
bb1:
br i1 undef, label %bb3, label %bb4
bb2:
br i1 undef, label %bb4, label %bb3
bb3:
pv1 = phi type [ undef, %bb1 ], [ undef, %bb2], [ v0, %other ]
br label %bb4
bb4:
pv2 = phi type [ undef, %bb1 ], [ undef, %bb2 ],
[ pv1, %bb3 ], [ v0, %other ]
If %bb2 is removed before %bb1, the incoming values from %bb1 and %bb2
to pv1 will be removed before %bb1 is removed as a predecessor to %bb4.
The pv1 node will thus be optimized out (to v0) at the time %bb1 is
removed as a predecessor to %bb4, leaving the blocks as following when
the incoming value from %bb1 has been removed:
bb3: ; pv1 optimized out, incoming value to pv2 is v0
br label %bb4
bb4:
pv2 = phi type [ v0, %bb3 ], [ v0, %other ]
The pv2 PHI node will be optimized away by removePredecessor() as all
incoming values are identical.
In case %bb2 is removed after %bb1, pv1 will not be optimized out at the
time %bb2 is removed as a predecessor to %bb4, leaving the blocks as
following when the incoming value from %bb2 to pv2 has been removed:
bb3:
pv1 = phi type [ undef, %bb2 ], [ v0, %other ]
br label %bb4
bb4:
pv2 = phi type [ pv1, %bb3 ], [ v0, %other ]
The pv2 PHI node will thus not be removed in this case, ultimately
leading to the following output
bb3: ; pv1 optimized out, incoming value to pv2 is v0
br label %bb4
bb4:
pv2 = phi type [ v0, %bb3 ], [ v0, %other ]
I have not looked into changing DeleteDeadBlock() so that the redundant
PHI nodes are removed.
I have not added a test case, as I was not able to create a particularly
small and (not messy) reproducer. This is likely due to SmallPtrSet
behaving deterministically when in small mode.
Reviewers: void, dexonsmith, spatel, skatkov, fhahn, bkramer, nhaehnle
Reviewed By: fhahn
Subscribers: mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D48369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336109
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Alex Bradbury [Mon, 2 Jul 2018 14:13:27 +0000 (14:13 +0000)]
[X86] Fix test/MC/AsmParser/exprs-invalid.s after rL336104
This was my mistake for only running test/MC/X86 and test/CodeGen/X86.
Arguably .word should be removed from this test, as it is not supported
universally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336107
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John Brawn [Mon, 2 Jul 2018 13:53:46 +0000 (13:53 +0000)]
[llvm-exegesis] Change how the native architecture is determined
Currently the llvm-exegesis native architecture is determined by comparing the
llvm native architecture with X86, so to add a new target would mean adding a
new check. Change this to building up a list of the targets llvm-exegesis
supports then using that, as this means that when adding a new target you just
add the target to the list of supported targets.
Differential Revision: https://reviews.llvm.org/D48778
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336105
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Alex Bradbury [Mon, 2 Jul 2018 13:49:52 +0000 (13:49 +0000)]
[X86] Use addAliasForDirective to support the .word directive (reland)
The X86 asm parser currently has custom parsing logic for .word. Rather than
use this custom logic, we can just use addAliasForDirective to enable the
reuse of AsmParser::parseDirectiveValue.
See also similar changes to Sparc (rL333078), AArch64 (rL333077), and Hexagon
(rL332607) backends.
Differential Revision: https://reviews.llvm.org/D47004
This is a fixed reland of rL336100. This should have been caught in
pre-commit testing so apologies for the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336104
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Alex Bradbury [Mon, 2 Jul 2018 13:43:45 +0000 (13:43 +0000)]
Revert r336100
This was a bad change. .word == 2byte on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336103
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Simon Pilgrim [Mon, 2 Jul 2018 13:41:29 +0000 (13:41 +0000)]
[SLPVectorizer] Remove nullptr early-outs from Instruction::ShuffleVector getEntryCost
This code is only used by alternate opcodes so the InstructionsState has already confirmed that every Value is an Instruction, plus we use cast<Instruction> which will assert on failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336102
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Sanjay Patel [Mon, 2 Jul 2018 13:40:54 +0000 (13:40 +0000)]
[InstCombine] adjust shuffle tests with IR flags; NFC
Due to current limitations in constant analysis, we need flags
on add or mul to show propagation for the potential transform
suggested in these tests (no other binops currently report
identity constants).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336101
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Alex Bradbury [Mon, 2 Jul 2018 13:37:15 +0000 (13:37 +0000)]
[X86] Use addAliasForDirective to support the .word directive
The X86 asm parser currently has custom parsing logic for .word. Rather than
use this custom logic, we can just use addAliasForDirective to enable the
reuse of AsmParser::parseDirectiveValue.
See also similar changes to Sparc (rL333078), AArch64 (rL333077), and Hexagon
(rL332607) backends.
Differential Revision: https://reviews.llvm.org/D47004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336100
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John Brawn [Mon, 2 Jul 2018 13:14:49 +0000 (13:14 +0000)]
[llvm-exegesis] Delegate the decision of cycle counter name to the target
Currently the cycle counter is taken from the subtarget schedule model, which
isn't any use if the subtarget doesn't have one. Delegate the decision to the
target benchmark runner, as it may know better what to do in that case, with
the default being the current behaviour.
Differential Revision: https://reviews.llvm.org/D48779
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336099
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Florian Hahn [Mon, 2 Jul 2018 12:44:04 +0000 (12:44 +0000)]
Recommit r328307: [IPSCCP] Use constant range information for comparisons of parameters.
This version contains a fix to add values for which the state in ParamState change
to the worklist if the state in ValueState did not change. To avoid adding the
same value multiple times, mergeInValue returns true, if it added the value to
the worklist. The value is added to the worklist depending on its state in
ValueState.
Original message:
For comparisons with parameters, we can use the ParamState lattice
elements which also provide constant range information. This improves
the code for PR33253 further and gets us closer to use
ValueLatticeElement for all values.
Also, as we are using the range information in the solver directly, we
do not need tryToReplaceWithConstantRange afterwards anymore.
Reviewers: dberlin, mssimpso, davide, efriedma
Reviewed By: mssimpso
Differential Revision: https://reviews.llvm.org/D43762
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336098
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Sanjay Patel [Mon, 2 Jul 2018 12:30:46 +0000 (12:30 +0000)]
[InstCombine] add tests for shuffle-binop; NFC
This is another pattern mentioned in PR37806.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336096
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Simon Pilgrim [Mon, 2 Jul 2018 11:28:01 +0000 (11:28 +0000)]
[SLPVectorizer] Fix alternate opcode + shuffle cost function to correct handle SK_Select patterns.
We were always using the opcodes of the first 2 scalars for the costs of the alternate opcode + shuffle. This made sense when we used SK_Alternate and opcodes were guaranteed to be alternating, but this fails for the more general SK_Select case.
This fix exposes an issue demonstrated by the fmul_fdiv_v4f32_const test - the SLM model has v4f32 fdiv costs which are more than twice those of the f32 scalar cost, meaning that the cost model determines that the vectorization is not performant. Unfortunately it completely ignores the fact that the fdiv by a constant will be changed into a fmul by InstCombine for a much lower cost vectorization. But at least we're seeing this now...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336095
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Simon Pilgrim [Mon, 2 Jul 2018 10:54:19 +0000 (10:54 +0000)]
[SLPVectorizer] Only Alternate opcodes use ShuffleVector cases for getEntryCost/vectorizeTree. NFCI.
Add assertions - we're already assuming this in how we use the AltOpcode and treat everything as BinaryOperators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336092
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Sander de Smalen [Mon, 2 Jul 2018 10:08:36 +0000 (10:08 +0000)]
[AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector)
Increments/decrements the result with the number of active bits
from the predicate.
The inc/dec variants added are:
- incp x0, p0.h (scalar)
- incp z0.h, p0 (vector)
The unsigned saturating inc/dec variants added are:
- uqincp x0, p0.h (scalar)
- uqincp w0, p0.h (scalar, 32bit)
- uqincp z0.h, p0 (vector)
The signed saturating inc/dec variants added are:
- sqincp x0, p0.h (scalar)
- sqincp x0, p0.h, w0 (scalar, 32bit)
- sqincp z0.h, p0 (vector)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336091
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Sander de Smalen [Mon, 2 Jul 2018 09:31:11 +0000 (09:31 +0000)]
[AArch64][SVE] Asm: Support for (saturating) vector INC/DEC instructions.
Increment/decrement vector by multiple of predicate constraint
element count.
The variants added by this patch are:
- INCH, INCW, INC
and (saturating):
- SQINCH, SQINCW, SQINCD
- UQINCH, UQINCW, UQINCW
- SQDECH, SQINCW, SQINCD
- UQDECH, UQINCW, UQINCW
For example:
incw z0.s, all, mul #4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336090
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Simon Pilgrim [Mon, 2 Jul 2018 09:15:01 +0000 (09:15 +0000)]
[X86][BtVer2] Added Jaguar FPU Pipe0/1 uop counters to permit basic llvm-exegesis uop testing
We don't have PMCs to cover many of the Jaguar resources but we can at least monitor the FPU issue pipes which give an indication of the fpu uop count, just not the execution resources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336089
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Petar Jovanovic [Mon, 2 Jul 2018 08:56:57 +0000 (08:56 +0000)]
[Mips][FastISel] Do not duplicate condition while lowering branches
This change fixes the issue that arises when we duplicate condition from
the predecessor block. If the condition's arguments are not considered alive
across the blocks, fast regalloc gets confused and starts generating reloads
from the slots that have never been spilled to. This change also leads to
smaller code given that, unlike on architectures with condition codes, on
Mips we can branch directly on register value, thus we gain nothing by
duplication.
Patch by Dragan Mladjenovic.
Differential Revision: https://reviews.llvm.org/D48642
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336084
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Sander de Smalen [Mon, 2 Jul 2018 08:20:59 +0000 (08:20 +0000)]
[AArch64][SVE] Asm: Support for vector element compares (immediate).
Compare vector elements with a signed/unsigned immediate, e.g.
cmpgt p0.s, p0/z, z0.s, #-16
cmphi p0.s, p0/z, z0.s, #127
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336081
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Sander de Smalen [Mon, 2 Jul 2018 07:34:52 +0000 (07:34 +0000)]
Reapply r334980 and r334983.
These patches were previously reverted as they led to
buildbot time-outs caused by large switch statement in
printAliasInstr when using UBSan and O3. The issue has
been addressed with a workaround (r335525).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336079
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Max Kazantsev [Mon, 2 Jul 2018 06:55:00 +0000 (06:55 +0000)]
[NFC] Test that shows unprofitability of instcombine with bit ranges
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336078
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Craig Topper [Mon, 2 Jul 2018 06:42:42 +0000 (06:42 +0000)]
[X86] Put some cases in switch statements back on one line to be more compact and make it easier to see the similarities. NFC
It looks like someone ran clang-format over this entire file which reformatted these switches into a multiline form. But I think the single line form is more useful here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336077
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Clement Courbet [Mon, 2 Jul 2018 06:39:55 +0000 (06:39 +0000)]
[llvm-exegesis][NFC] Cleanup useless braces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336076
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Craig Topper [Mon, 2 Jul 2018 06:23:39 +0000 (06:23 +0000)]
[X86] Remove FMA3Info DenseMap. Break into sorted tables that we can binary search.
I separated out the rounding and broadcast groups into their own tables because it made the ordering in the main table easier.
Further splitting of the tables might make it possible to directly index using bits from the TSFlags, but its probably not worth it right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336075
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QingShan Zhang [Mon, 2 Jul 2018 05:46:09 +0000 (05:46 +0000)]
[PowerPC] Don't make it as pre-inc candidate if displacement isn't 4's multiple for i64 pre-inc load/store
For the below case, pre-inc prep think it's a good candidate to use pre-inc for the bucket, but 64bit integer load/store update (pre-inc) instruction on Power requires the displacement field should be DS-form (4's multiple). Since it can't satisfy the constraint, we have to do some fix ups later. As below, the original load/stores could be well-form, it makes things worse.
unsigned long long result = 0;
unsigned long long foo(char *p, unsigned long long n) {
for (unsigned long long i = 0; i < n; i++) {
unsigned long long x1 = *(unsigned long long *)(p - 50000 + i);
unsigned long long x2 = *(unsigned long long *)(p - 61024 + i);
unsigned long long x3 = *(unsigned long long *)(p - 62048 + i);
unsigned long long x4 = *(unsigned long long *)(p - 64096 + i);
result *= x1 * x2 * x3 * x4;
}
return result;
}
Patch by jedilyn(Kewen Lin).
Differential Revision: https://reviews.llvm.org/D48813
--This line, and those below, will be ignored--
M lib/Target/PowerPC/PPCLoopPreIncPrep.cpp
A test/CodeGen/PowerPC/preincprep-i64-check.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336074
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Piotr Padlewski [Mon, 2 Jul 2018 04:49:30 +0000 (04:49 +0000)]
Implement strip.invariant.group
Summary:
This patch introduce new intrinsic -
strip.invariant.group that was described in the
RFC: Devirtualization v2
Reviewers: rsmith, hfinkel, nlopes, sanjoy, amharc, kuhar
Subscribers: arsenm, nhaehnle, JDevlieghere, hiraditya, xbolva00, llvm-commits
Differential Revision: https://reviews.llvm.org/D47103
Co-authored-by: Krzysztof Pszeniczny <krzysztof.pszeniczny@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336073
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Eric Christopher [Mon, 2 Jul 2018 00:16:39 +0000 (00:16 +0000)]
Add an entry for rodata constant merge sections to the default
section flags in the ELF assembler. This matches the defaults
given in the rest of MC.
Fixes PR37997 where we couldn't assemble our own assembly output
without warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336072
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Craig Topper [Sun, 1 Jul 2018 23:49:06 +0000 (23:49 +0000)]
[X86] Fix a few test names in avx512-intrinsics-fast-isel.ll to match their clang intrinsic names.
I thought I fixed these yesterday, but I guess I missed a few.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336071
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Craig Topper [Sun, 1 Jul 2018 23:27:41 +0000 (23:27 +0000)]
[X86] Remove the places that return nullptr from X86InstrInfo::commuteInstructionImpl.
findCommutedOpIndices does the pre-checking for whether commuting is possible. There should be no reason left to fail in commuteInstructionImpl. There was a missing pre-check that I've added there and changed the check to an assert in commuteInstructionImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336070
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Simon Pilgrim [Sun, 1 Jul 2018 20:22:46 +0000 (20:22 +0000)]
[SLPVectorizer] Call InstructionsState.isOpcodeOrAlt with Instruction instead of an opcode. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336069
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Simon Pilgrim [Sun, 1 Jul 2018 20:07:30 +0000 (20:07 +0000)]
[SLPVectorizer] Replace sameOpcodeOrAlt with InstructionsState.isOpcodeOrAlt helper. NFCI.
This is a basic step towards matching more general instructions types than just opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336068
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Craig Topper [Sun, 1 Jul 2018 17:50:29 +0000 (17:50 +0000)]
[X86][Disassembler] Remove TYPE_BNDR from translateImmediate.
I've check the disassembler tables and this shouldn't be reachable. Which is good since if it was reachable there should have been a 'return' after the addOperand line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336066
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Sanjay Patel [Sun, 1 Jul 2018 17:14:37 +0000 (17:14 +0000)]
[InstCombine] add abs tests with undef elts; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336065
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Sanjay Patel [Sun, 1 Jul 2018 13:42:57 +0000 (13:42 +0000)]
[PatternMatch] allow undef elements in vectors with m_Neg
This is similar to the m_Not change from D44076.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336064
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Simon Pilgrim [Sun, 1 Jul 2018 13:41:58 +0000 (13:41 +0000)]
[SLPVectorizer] Use InstructionsState Op/Alt opcodes directly. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336063
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David Green [Sun, 1 Jul 2018 12:47:30 +0000 (12:47 +0000)]
[UnrollAndJam] New Unroll and Jam pass
This is a simple implementation of the unroll-and-jam classical loop
optimisation.
The basic idea is that we take an outer loop of the form:
for i..
ForeBlocks(i)
for j..
SubLoopBlocks(i, j)
AftBlocks(i)
Instead of doing normal inner or outer unrolling, we unroll as follows:
for i... i+=2
ForeBlocks(i)
ForeBlocks(i+1)
for j..
SubLoopBlocks(i, j)
SubLoopBlocks(i+1, j)
AftBlocks(i)
AftBlocks(i+1)
Remainder Loop
So we have unrolled the outer loop, then jammed the two inner loops into
one. This can lead to a simpler inner loop if memory accesses can be shared
between the now jammed loops.
To do this we have to prove that this is all safe, both for the memory
accesses (using dependence analysis) and that ForeBlocks(i+1) can move before
AftBlocks(i) and SubLoopBlocks(i, j).
Differential Revision: https://reviews.llvm.org/D41953
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336062
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Paul Semel [Sun, 1 Jul 2018 11:54:09 +0000 (11:54 +0000)]
Revert "[llvm-readobj] Fix printing format"
There is a problem with the formatting on windows build.
I need to investigate on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336061
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Simon Pilgrim [Sun, 1 Jul 2018 11:29:46 +0000 (11:29 +0000)]
[SLPVectorizer][X86] Add some alternate tests for cast operators
Alternate opcode handling only supports binary operators, these tests demonstrate missed opportunities to vectorize some sitofp/uitofp and fptosi/fptoui style casts as well as some (successful) float bits manipulations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336060
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Eugene Leviant [Sun, 1 Jul 2018 11:02:07 +0000 (11:02 +0000)]
[Evaluator] Improve evaluation of call instruction
Recommit of r335324 after buildbot failure fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336059
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Paul Semel [Sun, 1 Jul 2018 09:51:59 +0000 (09:51 +0000)]
[llvm-readobj] Fix printing format
We were printing every character, even those that weren't printable. It
doesn't really make sense for this option.
The string content was sticked to its address, added two spaces in
between.
Differential Revision: https://reviews.llvm.org/D48271
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336058
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Craig Topper [Sun, 1 Jul 2018 05:54:22 +0000 (05:54 +0000)]
[X86] Remove unnecessary include. NFC
Leftover from when the pass contained a DenseMap before it switched to binary search.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336057
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Craig Topper [Sun, 1 Jul 2018 05:47:49 +0000 (05:47 +0000)]
[X86] Move the memory unfolding table creation into its own class and make it a ManagedStatic.
Also move the static folding tables, their search functions and the new class into new cpp/h files.
The unfolding table is effectively static data. It's just a different ordering and a subset of the static folding tables.
By putting it in a separate ManagedStatic we ensure we only have one copy instead of one per X86InstrInfo object. This way also makes it only get initialized when really needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336056
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Craig Topper [Sat, 30 Jun 2018 22:38:42 +0000 (22:38 +0000)]
[X86] Move the X86InstrFMA3Info class into the cpp file. Expose only a getFMA3Group free function. NFCI
The class only exists to hold a DenseMap and is only created as a ManagedStatic. It used to expose a single static method that outside code was expected to use.
This patch moves that static function out of the class and moves it implementation into the cpp file. It can now access the ManagedStatic directly by name without the need for the other static method that accessed the ManagedStatic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336055
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Craig Topper [Sat, 30 Jun 2018 22:38:41 +0000 (22:38 +0000)]
[X86] Remove the AsmName from the HAX,HDX,HCX,HBX,HSI,HDI,HBP,HSP,HIP artificial registers so they can't be parsed by the assembly parser.
There are no instructions that use them so they weren't causing any bad matches. But they weren't being diagnosed as "invalid register name" if they were used and would instead trigger some form of invalid operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336054
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Craig Topper [Sat, 30 Jun 2018 18:30:31 +0000 (18:30 +0000)]
[X86] Use MVT::i8 for scalar shift amounts since that is what they ultimately need to legalize to.
I believe all of these are constants so legalizing them should be pretty trivial, but this saves a step.
In one case it looks like we may have been creating a shift amount larger than the shift input itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336052
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Craig Topper [Sat, 30 Jun 2018 17:49:42 +0000 (17:49 +0000)]
[X86] When combining load to BZHI, make sure we create the shift instruction with an i8 type.
This combine runs pretty late and causes us to introduce a shift after the op legalization phase has run. We need to be sure we create the shift with the proper type for the shift amount. If we don't do this, we will still re-legalize the operation properly, but we won't get a chance to fully optimize the truncate that gets inserted.
So this patch adds the necessary truncate when the shift is created. I've also narrowed the subtract that gets created to always be an i32 type. The truncate would have trigered SimplifyDemandedBits to optimize it anyway. But using a more appropriate VT here is free and saves an optimization step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336051
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Sanjay Patel [Sat, 30 Jun 2018 14:11:46 +0000 (14:11 +0000)]
[InstCombine] add tests for negate vector with undef elts; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336050
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