OSDN Git Service
Quentin Colombet [Thu, 21 Jul 2016 22:25:57 +0000 (22:25 +0000)]
[MIRTesting] Abort when failing to parse a function.
When we failed to parse a function in the mir parser, we should abort
the whole compilation instead of continuing in a weird state. Indeed,
this was creating strange machine function passes failures that were
hard to understand, until we notice that the function actually did not
get parsed correctly!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276348
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Michael Kuperstein [Thu, 21 Jul 2016 22:24:08 +0000 (22:24 +0000)]
[X86] Do not use AND8ri8 in AVX512 pattern
This variant is (as documented in the TD) for disassembler use only, and should
not be used in patterns - it is longer, and is broken on 64-bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276347
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Sanjay Patel [Thu, 21 Jul 2016 21:56:00 +0000 (21:56 +0000)]
[InstSimplify] don't crash handling a pointer or aggregate type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276345
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Akira Hatanaka [Thu, 21 Jul 2016 21:39:05 +0000 (21:39 +0000)]
[AArch64][Inline-Asm] Return the 32-bit floating point register class
when constraint "w" is used on a 32-bit operand.
This enables compiling the following code, which used to error out in
the backend:
void foo1(int a) {
asm volatile ("sqxtn h0, %s0\n" : : "w"(a):);
}
Fixes PR28633.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276344
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Michael Gottesman [Thu, 21 Jul 2016 21:35:23 +0000 (21:35 +0000)]
[cmake] Move the including of utils/unittests under LLVM_INCLUDE_UTILS instead of LLVM_INCLUDE_TESTS.
This does not change anything by default since LLVM_INCLUDE_UTILS is already set
to TRUE by default. In addition, since LLVM_INCLUDE_TESTS => LLVM_INCLUDE_UTILS,
the only way that this can cause changes is in the case where LLVM_INCLUDE_UTILS
is set to TRUE, but LLVM_INCLUDE_TESTS is FALSE. In that case, building gtest is
not a huge cost.
The reason to do this is that without this change, one can not turn off
LLVM_INCLUDE_TESTS in downstream projects that also use gtest for unittests. It
also just in general makes more sense since LLVM_INCLUDE_UTILS gates FileCheck
and other utilities that are along the lines of gtest.
Additionally from talking with chandlerc, this was not done for any specific
reason, so there is no reason not to do it and lots of benefit to doing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276342
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Sanjay Patel [Thu, 21 Jul 2016 21:26:45 +0000 (21:26 +0000)]
[InstSimplify] recognize trunc + icmp sgt/slt variants of select simplifications (PR28466)
rL245171 exposed a hole in InstSimplify that manifested in a strange way in PR28466:
https://llvm.org/bugs/show_bug.cgi?id=28466
It's possible to use trunc + icmp sgt/slt in place of an and + icmp eq/ne, so we need to
recognize that pattern to eliminate selects that are choosing between some value and some
bitmasked version of that value.
Note that there is significant room for improvement (refactoring) and enhancement (more
patterns, possibly in InstCombine rather than here).
Differential Revision: https://reviews.llvm.org/D22537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276341
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Adam Nemet [Thu, 21 Jul 2016 21:21:34 +0000 (21:21 +0000)]
[OptDiag,LDist] Convert remaining opt remarks to use the new API
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276340
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Matthew Simpson [Thu, 21 Jul 2016 21:20:15 +0000 (21:20 +0000)]
[LV] Move vector int induction update to end of latch
This patch moves the update instruction for vectorized integer induction phi
nodes to the end of the latch block. This ensures consistent placement of all
induction updates across all the kinds of int inductions we create (scalar,
splat vector, or vector phi).
Differential Revision: https://reviews.llvm.org/D22416
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276339
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Reid Kleckner [Thu, 21 Jul 2016 21:06:04 +0000 (21:06 +0000)]
Fix the clang-cl self-host with VS 2013 headers
std::numeric_limits<int64_t>::max() is not constexpr in VC 2013 headers,
and Clang complains that it isn't. MSVC 2013 itself is emitting a
dynamic initializer for this thing. Instead, use an enum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276334
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George Burgess IV [Thu, 21 Jul 2016 20:52:35 +0000 (20:52 +0000)]
Normalize file docs. NFC.
Having the added `\brief` made doxygen interpret it as the summary for
the `llvm` namespace (visible at:
http://llvm.org/doxygen/namespaces.html).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276331
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Rong Xu [Thu, 21 Jul 2016 20:50:02 +0000 (20:50 +0000)]
[PGO] Make needsComdatForCounter() available (NFC)
Move needsComdatForCounter() to lib/ProfileData/InstrProf.cpp from
lib/Transforms/Instrumentation/InstrProfiling.cpp to make is available for
other files.
Differential Revision: https://reviews.llvm.org/D22643
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276330
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Sanjay Patel [Thu, 21 Jul 2016 20:11:08 +0000 (20:11 +0000)]
add vector tests and a simpler version of the negative tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276328
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Renato Golin [Thu, 21 Jul 2016 19:52:27 +0000 (19:52 +0000)]
[docs] Move GitHub to GitHubSubMod
Given that other proposals are making their way through, it's better if we
specify what GitHub proposal this is, in case there are others that also
involve GitHub, but not sub-modules.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276325
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Richard Osborne [Thu, 21 Jul 2016 19:20:57 +0000 (19:20 +0000)]
Transfer ownership of the XCore backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276321
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Anna Thomas [Thu, 21 Jul 2016 19:06:28 +0000 (19:06 +0000)]
Revert "Invariant start/end intrinsics overloaded for address space"
This reverts commit r276316.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276320
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Sanjoy Das [Thu, 21 Jul 2016 18:58:01 +0000 (18:58 +0000)]
[IndVars] Reflow oddly formatted condition; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276319
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Anna Thomas [Thu, 21 Jul 2016 18:41:44 +0000 (18:41 +0000)]
Invariant start/end intrinsics overloaded for address space
Summary:
The llvm.invariant.start and llvm.invariant.end intrinsics currently
support specifying invariant memory objects only in the default address space.
With this change, these intrinsics are overloaded for any adddress space for memory objects
and we can use these llvm invariant intrinsics in non-default address spaces.
Example: llvm.invariant.start.p1i8(i64 4, i8 addrspace(1)* %ptr)
This overloaded intrinsic is needed for representing final or invariant memory in managed languages.
Reviewers: tstellarAMD, reames, apilipenko
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D22519
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276316
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Sanjay Patel [Thu, 21 Jul 2016 18:07:40 +0000 (18:07 +0000)]
make InstCombine compare helper functions private; NFC
Also, rename some of them for consistency and to follow current conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276312
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Vedant Kumar [Thu, 21 Jul 2016 17:50:07 +0000 (17:50 +0000)]
Avoid a string copy, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276310
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Quentin Colombet [Thu, 21 Jul 2016 17:26:50 +0000 (17:26 +0000)]
[IRTranslator] Add G_SUB opcode.
This commit adds a generic SUB opcode to global-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276308
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Quentin Colombet [Thu, 21 Jul 2016 17:26:47 +0000 (17:26 +0000)]
[llvm-config][GlobalISel] Canonicalize LLVM_HAS_GLOBAL_ISEL on ON/OFF.
Previously LLVM_HAS_GLOBAL_ISEL would directly get the value of
LLVM_BUILD_GLOBAL_ISEL. This could be any integer value and not just ON
and OFF. The problem is that lit.cfg was checking for ON to define that
global-isel was supported, thus if we were setting
LLVM_BUILD_GLOBAL_ISEL with an integer value, say 1, this test would
fail whereas we do build global-isel and want to test it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276307
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Quentin Colombet [Thu, 21 Jul 2016 17:26:45 +0000 (17:26 +0000)]
[CMake][GlobalISel] Turn LLVM_BUILD_GLOBAL_ISEL into an option. NFC.
Previously LLVM_BUILD_GLOBAL_ISEL was a boolean variable and although,
this is strictly identical to an option, it did not convey the
information that the user may set it. Options are here for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276306
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Quentin Colombet [Thu, 21 Jul 2016 17:26:41 +0000 (17:26 +0000)]
[IRTranslator] Add comments to explain the ordering of the switch. NFC.
Group arithmetic operations, bitwise operations, and branch operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276305
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Sanjay Patel [Thu, 21 Jul 2016 17:15:49 +0000 (17:15 +0000)]
[InstCombine] break up visitICmpInstWithInstAndIntCst(); NFCI
Making smaller pieces out of some of these ~1000 line functions should make
it easier to incrementally upgrade them to handle vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276304
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Renato Golin [Thu, 21 Jul 2016 16:46:44 +0000 (16:46 +0000)]
Adding RELEASE_TESTERS.TXT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276302
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Konstantin Zhuravlyov [Thu, 21 Jul 2016 15:59:23 +0000 (15:59 +0000)]
[AMDGPU] Emit read-only data to .rodata for hsa
Differential Revision: https://reviews.llvm.org/D22538
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276298
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Quentin Colombet [Thu, 21 Jul 2016 15:50:42 +0000 (15:50 +0000)]
[IRTranslator] Add G_AND opcode.
This commit adds a generic AND opcode to global-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276297
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Konstantin Zhuravlyov [Thu, 21 Jul 2016 15:29:19 +0000 (15:29 +0000)]
AMDGPU/SI: Add support for R_AMDGPU_ABS32
Differential Revision: https://reviews.llvm.org/D21646
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276294
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Geoff Berry [Thu, 21 Jul 2016 15:20:25 +0000 (15:20 +0000)]
[AArch64] Load/store opt: Don't count transient instructions towards search limits.
Summary:
This change also changes findMatchingInsn and
findMatchingUpdateInsnForward to take DBG_VALUE opcodes into account
when tracking register defs and uses, which could potentially inhibit
these optimizations in the presence of debug information.
Reviewers: mcrosier
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D22582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276293
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Benjamin Kramer [Thu, 21 Jul 2016 15:06:50 +0000 (15:06 +0000)]
Weaken ThreadSafeRefCountedBase atomics.
Doesn't make a difference on x86, but avoids memory barriers on
weakly-ordered archs like PowerPC and ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276291
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Simon Pilgrim [Thu, 21 Jul 2016 14:54:17 +0000 (14:54 +0000)]
[X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element
Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW.
But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register.
This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41).
Fix for PR27265.
Differential Revision: https://reviews.llvm.org/D22509
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276289
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Simon Pilgrim [Thu, 21 Jul 2016 14:36:41 +0000 (14:36 +0000)]
Fixed line endings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276287
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Simon Pilgrim [Thu, 21 Jul 2016 14:30:17 +0000 (14:30 +0000)]
[X86][SSE] Pull out duplicate EXTRW lowering code. NFCI.
As requested on D22509, I've pulled out the v8i16 extraction lowering as the SSE41 and pre-SSE41 implementations are effectively the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276285
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Benjamin Kramer [Thu, 21 Jul 2016 14:29:11 +0000 (14:29 +0000)]
[profdata] Remove constructor that MSVC 2013 pretends to not understand.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276284
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Simon Pilgrim [Thu, 21 Jul 2016 14:10:54 +0000 (14:10 +0000)]
[X86][AVX] Added support for lowering to VBROADCASTF128/VBROADCASTI128
As reported on PR26235, we don't currently make use of the VBROADCASTF128/VBROADCASTI128 instructions (or the AVX512 equivalents) to load+splat a 128-bit vector to both lanes of a 256-bit vector.
This patch enables lowering from subvector insertion/concatenation patterns and auto-upgrades the llvm.x86.avx.vbroadcastf128.pd.256 / llvm.x86.avx.vbroadcastf128.ps.256 intrinsics to match.
We could possibly investigate using VBROADCASTF128/VBROADCASTI128 to load repeated constants as well (similar to how we already do for scalar broadcasts).
Differential Revision: https://reviews.llvm.org/D22460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276281
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Benjamin Kramer [Thu, 21 Jul 2016 13:37:55 +0000 (13:37 +0000)]
[DemandedBits] Reduce number of duplicated DenseMap lookups.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276278
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Benjamin Kramer [Thu, 21 Jul 2016 13:37:53 +0000 (13:37 +0000)]
[DenseMap] Add a C++17-style try_emplace method.
This provides an elegant pattern to solve the "construct if not in map
already" problem we have many times in LLVM. Without try_emplace we
either have to rely on a sentinel value (nullptr) or do two lookups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276277
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Benjamin Kramer [Thu, 21 Jul 2016 13:37:48 +0000 (13:37 +0000)]
Rename StringMap::emplace_second to try_emplace.
Coincidentally this function maps to the C++17 try_emplace. Rename it
for consistentcy with C++17 std::map. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276276
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Sam Kolton [Thu, 21 Jul 2016 13:29:57 +0000 (13:29 +0000)]
[AMDGPU] Some code cleaning in SIRegisterInfo.td
Reviewers: tstellarAMD, vpykhtin
Subscribers: arsenm, kzhuravl
Differential Revision: https://reviews.llvm.org/D22620
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276274
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Marina Yatsina [Thu, 21 Jul 2016 12:37:07 +0000 (12:37 +0000)]
ExecutionDepsFix - Fix bug in clearance calculation
The clearance calculation did not take into account registers defined as outputs or clobbers in inline assembly machine instructions because these register defs are implicit.
Differential Revision: http://reviews.llvm.org/D22580
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276266
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Benjamin Kramer [Thu, 21 Jul 2016 12:06:31 +0000 (12:06 +0000)]
[GCOV] Remove a layer of indirection.
StringMap is designed to hold large values. No functionality change
intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276265
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Renato Golin [Thu, 21 Jul 2016 12:00:50 +0000 (12:00 +0000)]
[docs] Update release docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276264
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Matt Arsenault [Thu, 21 Jul 2016 09:40:57 +0000 (09:40 +0000)]
AMDGPU: Fix phis from blocks split due to register indexing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276257
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David Majnemer [Thu, 21 Jul 2016 07:16:26 +0000 (07:16 +0000)]
[GVNHoist] Preserve optimization hints which agree
If we have optimization hints with agree with each other along different
paths, preserve them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276248
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David Majnemer [Thu, 21 Jul 2016 05:59:53 +0000 (05:59 +0000)]
[GVNHoist] Don't wrongly preserve TBAA
We hoisted loads/stores without taking into account which can cause
miscompiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276240
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David Majnemer [Thu, 21 Jul 2016 05:59:51 +0000 (05:59 +0000)]
[MergedLoadStoreMotion] Remove out of date comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276239
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Amaury Sechet [Thu, 21 Jul 2016 04:31:38 +0000 (04:31 +0000)]
Add missing import to fix the build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276237
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Amaury Sechet [Thu, 21 Jul 2016 04:25:06 +0000 (04:25 +0000)]
Expose AttributeSetNode, use it to provide aggregate getter for attribute in the C API.
Summary: See D19181 for context.
Reviewers: whitequark, Wallbraker, jyknight, echristo, bkramer, void
Subscribers: mehdi_amini
Differential Revision: http://reviews.llvm.org/D21265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276236
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Matthias Braun [Thu, 21 Jul 2016 03:50:39 +0000 (03:50 +0000)]
IPRA: Fix RegMask calculation for alias registers
This patch fixes a very subtle bug in regmask calculation. Thanks to zan
jyu Wong <zyfwong@gmail.com> for bringing this to notice.
For example if CL is only clobbered than CH should not be marked
clobbered but CX, RCX and ECX should be mark clobbered. Previously for
each modified register all of its aliases are marked clobbered by
markRegClobbred() in RegUsageInfoCollector.cpp but that is wrong because
when CL is clobbered then MRI::isPhysRegModified() will return true for
CL, CX, ECX, RCX which is correct behavior but then for CX, EXC, RCX we
mark CH also clobbered as CH is aliased to CX,ECX,RCX so
markRegClobbred() is not required because isPhysRegModified already take
cares of proper aliasing register. A very simple test case has been
added to verify this change.
Please find relevant bug report here :
http://llvm.org/PR28567
Patch by Vivek Pandya <vivekvpandya@gmail.com>
Differential Revision: https://reviews.llvm.org/D22400
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276235
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Adam Nemet [Thu, 21 Jul 2016 01:11:12 +0000 (01:11 +0000)]
[OptDiag] Missed these when making the IR Value a const pointer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276224
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Adam Nemet [Thu, 21 Jul 2016 01:07:13 +0000 (01:07 +0000)]
[OptDiag,LV] Add hotness attribute to applied-optimization remarks
Test coverage is provided by modifying the function in the FP-math
testcase that we are allowed to vectorize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276223
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Matthias Braun [Thu, 21 Jul 2016 00:33:38 +0000 (00:33 +0000)]
X86InstrInfo: No need for liveness analysis in classifyLEAReg()
classifyLEAReg() deals with switching operands from 32bit to 64bit in
order to use a LEA64_32 instruction (for three address code goodness).
It currently performs a liveness analysis to determine the kill/undef
flag for the newly added operand. This should not be necessary:
- If the previous operand had a kill flag, then the 32bit part of the
register gets killed, this will kill the super register as well.
- If the previous operand had an undef flag then we didn't care what
value we read, just use the same flag on the new operand.
(No matter what an operand with an undef flag won't affect liveness)
This makes the code independent of the presence of kill flags because it
avoids a call to MachineBasicBlock::computeRegisterLiveness().
Differential Revision: http://reviews.llvm.org/D22283
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276222
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Sanjay Patel [Thu, 21 Jul 2016 00:24:18 +0000 (00:24 +0000)]
[InstCombine] LogicOpc (zext X), C --> zext (LogicOpc X, C) (PR28476)
The benefits of this change include:
1. Remove DeMorgan-matching code that was added specifically to work-around
the missing transform in http://reviews.llvm.org/rL248634.
2. Makes the DeMorgan transform work for vectors too.
3. Fix PR28476: https://llvm.org/bugs/show_bug.cgi?id=28476
Extending this transform to other casts and other associative operators may
be useful too. See https://reviews.llvm.org/D22421 for a prerequisite for
doing that though.
Differential Revision: https://reviews.llvm.org/D22271
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276221
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Adam Nemet [Wed, 20 Jul 2016 23:50:32 +0000 (23:50 +0000)]
[OptDiag,LV] Add hotness attribute to the derived analysis remarks
This includes FPCompute and Aliasing.
Testcase is based on no_fpmath.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276211
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Sanjay Patel [Wed, 20 Jul 2016 23:40:01 +0000 (23:40 +0000)]
[InstSimplify][InstCombine] don't crash when folding vector selects of icmp
Differential Revision: https://reviews.llvm.org/D22602
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276209
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George Burgess IV [Wed, 20 Jul 2016 23:14:29 +0000 (23:14 +0000)]
Make help text more consistent. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276205
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Tim Northover [Wed, 20 Jul 2016 22:58:01 +0000 (22:58 +0000)]
GlobalISel: Remove explicit enumerator values from .def file.
They were all auto-incremented from 0 anyway, and I'm getting really annoying
conflicts and runtime failures when different people add more for GlobalISel
(and even when I'm refactoring my own patches).
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276204
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Xinliang David Li [Wed, 20 Jul 2016 22:53:39 +0000 (22:53 +0000)]
Fix test failure on Win
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276202
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George Burgess IV [Wed, 20 Jul 2016 22:53:30 +0000 (22:53 +0000)]
[CFLAA] Add offset tracking in CFLGraph.
(Also, refactor our constexpr handling to be less insane).
This patch lets us track field offsets in the CFL Graph, which is the
first step to making CFLAA field/offset sensitive. Woohoo! Note that
this patch shouldn't visibly change our behavior (since we make no use
of the offsets we're now tracking), so we can't quite add tests for this
yet.
Patch by Jia Chen.
Differential Revision: https://reviews.llvm.org/D22598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276201
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Vedant Kumar [Wed, 20 Jul 2016 22:44:16 +0000 (22:44 +0000)]
[utils] Add script to check for code coverage regressions
Differential Revision: https://reviews.llvm.org/D22544
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276199
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Xinliang David Li [Wed, 20 Jul 2016 22:24:52 +0000 (22:24 +0000)]
Reapply r276185
Fix the test case that should not depend on dir iteration order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276197
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Justin Lebar [Wed, 20 Jul 2016 22:11:36 +0000 (22:11 +0000)]
[NVPTX] Enable the load-store vectorizer on nvptx.
Reviewers: tra
Subscribers: jholewinski, arsenm, asbirlea
Differential Revision: https://reviews.llvm.org/D22592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276196
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Xinliang David Li [Wed, 20 Jul 2016 21:50:38 +0000 (21:50 +0000)]
Revert r276185 -- build bot failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276194
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Geoff Berry [Wed, 20 Jul 2016 21:45:58 +0000 (21:45 +0000)]
[AArch64] Register AArch64LoadStoreOptimizer so it can be run by llc -run-pass. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276193
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Adam Nemet [Wed, 20 Jul 2016 21:44:26 +0000 (21:44 +0000)]
[OptDiag,LV] Add hotness attribute to analysis remarks
The earlier change added hotness attribute to missed-optimization
remarks. This follows up with the analysis remarks (the ones explaining
the reason for the missed optimization).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276192
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Adam Nemet [Wed, 20 Jul 2016 21:44:22 +0000 (21:44 +0000)]
[OptDiag] Take the IR Value as a const pointer
This helps because LoopAccessReport is passed around as a const
reference and we derive the basic block passed as the Value parameter
from the instruction in LoopAccessReport.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276191
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Adam Nemet [Wed, 20 Jul 2016 21:44:18 +0000 (21:44 +0000)]
[OptDiag] Wrap a long line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276190
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Artem Belevich [Wed, 20 Jul 2016 21:44:07 +0000 (21:44 +0000)]
[NVPTX] Renamed NVPTXLowerKernelArgs -> NVPTXLowerArgs. NFC.
After r276153 the pass applies to both kernels and regular functions.
Differential Revision: https://reviews.llvm.org/D22583
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276189
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Xinliang David Li [Wed, 20 Jul 2016 21:31:29 +0000 (21:31 +0000)]
[Profile] support directory reading in profile merging
Differential Revision: http://reviews.llvm.org/D22560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276185
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Tim Northover [Wed, 20 Jul 2016 21:13:29 +0000 (21:13 +0000)]
GlobalISel: implement Legalization querying framework.
This adds an (incomplete, inefficient) framework for deciding what to do with
some operation on a given type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276184
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Ahmed Bougacha [Wed, 20 Jul 2016 21:12:32 +0000 (21:12 +0000)]
[AArch64][FastISel] Select -O0 legal cmpxchg.
At -O0, cmpxchg survives AtomicExpand: it's mostly straightforward
to select it in fast-isel, and let the pseudo be expanded later.
extractvalues on the result are the tricky part: the generic logic
only works for legal types (and it would be painful to make it
support illegal types), so we can only support i32/i64 cmpxchg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276183
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Ahmed Bougacha [Wed, 20 Jul 2016 21:12:27 +0000 (21:12 +0000)]
[AArch64][FastISel] Select atomic stores into STLR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276182
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David Majnemer [Wed, 20 Jul 2016 21:05:01 +0000 (21:05 +0000)]
[GVNHoist] Don't hoist PHI nodes
We hoisted PHIs without respecting their special insertion point in the
block, leading to verfier errors.
This fixes PR28626.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276181
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Davide Italiano [Wed, 20 Jul 2016 20:17:13 +0000 (20:17 +0000)]
[SCCP] Zap multiple return values.
We can replace the return values with undef if we replaced all
the call uses with a constant/undef.
Differential Revision: https://reviews.llvm.org/D22336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276174
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Justin Lebar [Wed, 20 Jul 2016 20:07:37 +0000 (20:07 +0000)]
[LSV] Don't move stores across may-load instrs, and loosen restrictions on moving loads.
Summary:
Previously we wouldn't move loads/stores across instructions that had
side-effects, where that was defined as may-write or may-throw. But
this is not sufficiently restrictive: Stores can't safely be moved
across instructions that may load.
This patch also adds a DEBUG check that all instructions in our chain
are either loads or stores.
Reviewers: asbirlea
Subscribers: llvm-commits, jholewinski, arsenm, mzolotukhin
Differential Revision: https://reviews.llvm.org/D22547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276171
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Justin Lebar [Wed, 20 Jul 2016 20:07:34 +0000 (20:07 +0000)]
[LSV] Vectorize up to side-effecting instructions.
Summary:
Previously if we had a chain that contained a side-effecting
instruction, we wouldn't vectorize it at all. Now we'll vectorize
everything that comes before the side-effecting instruction.
Reviewers: asbirlea
Subscribers: arsenm, jholewinski, llvm-commits, mzolotukhin
Differential Revision: https://reviews.llvm.org/D22536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276170
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George Burgess IV [Wed, 20 Jul 2016 19:51:34 +0000 (19:51 +0000)]
[MSSA] Add an overload for getClobberingMemoryAccess.
A seemingly common use for the walker's getClobberingMemoryAccess
function is:
```
MemoryAccess *getClobber(MemorySSAWalker *W, MemoryUseOrDef *MUD) {
const Instruction *I = MUD->getMemoryInst();
return W->getClobberingMemoryAccess(I);
}
```
Which is kind of redundant, since walkers will ultimately query MSSA to
find out which MemoryAccess `I` maps to (...which is always `MUD`).
So, this patch adds an overload of getClobberingMemoryAccess that
accepts MemoryAccesses directly. As a result, the Instruction overload
of getClobberingMemoryAccess becomes a lightweight wrapper around our
new overload.
Additionally, this patch un`virtual`izes the Instruction overload of
getClobberingMemoryAccess, since there doesn't seem to be a walker that
benefits from that being virtual, and I can't think of how else one
would implement it. Happy to make it virtual again if we would benefit
from doing so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276169
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Rui Ueyama [Wed, 20 Jul 2016 19:41:47 +0000 (19:41 +0000)]
[pdbdump] Use the "flow" style to print out a sequence of uint32_t.
Summary: Lists can be written either with "-" or "[]" in YAML.
Differential Revision: https://reviews.llvm.org/D22579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276168
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Tim Northover [Wed, 20 Jul 2016 19:17:29 +0000 (19:17 +0000)]
GlobalISel: properly conditionalize LLT use.
We can't guard the include of LowLevelType.h because getType and setType are
(trivial) functions even when GlobalISel isn't built.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276160
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Tim Northover [Wed, 20 Jul 2016 19:09:30 +0000 (19:09 +0000)]
GlobalISel: implement low-level type with just size & vector lanes.
This should be all the low-level instruction selection needs to determine how
to implement an operation, with the remaining context taken from the opcode
(e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276158
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Alina Sbirlea [Wed, 20 Jul 2016 18:54:26 +0000 (18:54 +0000)]
Properly ifdef the use of cpuid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276156
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Artem Belevich [Wed, 20 Jul 2016 18:39:52 +0000 (18:39 +0000)]
[NVPTX] deal with all aggregate return types.
Fixes a crash in llvm_unreachable when a function has array return type.
Differential Revision: https://reviews.llvm.org/D22524
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276154
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Artem Belevich [Wed, 20 Jul 2016 18:39:47 +0000 (18:39 +0000)]
[NVPTX] Improve lowering of byval args of device functions.
Avoid unnecessary spills of byval arguments of device functions to
local space on SASS level and subsequent pointer conversion to generic
address space that follows. Instead, make a local copy in IR, provide
a way to access arguments directly, and let LLVM optimize the copy away
when possible.
Differential Review: https://reviews.llvm.org/D21421
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276153
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Adam Nemet [Wed, 20 Jul 2016 18:16:45 +0000 (18:16 +0000)]
[OptDiag] Fix function comment
Function is not passed unlike in the original of this
(llvm::emitOptimizationRemarkMissed).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276150
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Alina Sbirlea [Wed, 20 Jul 2016 18:15:29 +0000 (18:15 +0000)]
[cpu-detection] Cleanup of Host.cpp.
Summary:
Mirroring most cleanup changed from compiler-rt/lib/builtins/cpu_model.
x86 methods are still returning a bool.
Reviewers: llvm-commits, echristo, craig.topper, sanjoy
Subscribers: mehdi_amini
Differential Revision: https://reviews.llvm.org/D22480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276149
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Sanjay Patel [Wed, 20 Jul 2016 17:58:20 +0000 (17:58 +0000)]
minimize tests and auto-generate checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276147
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Sanjay Patel [Wed, 20 Jul 2016 17:18:45 +0000 (17:18 +0000)]
move decomposeBitTestICmp() to Transforms/Utils; NFC
As noted in https://reviews.llvm.org/D22537 , we can use this functionality in
visitSelectInstWithICmp() and InstSimplify, but currently we have duplicated
code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276140
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Wei Mi [Wed, 20 Jul 2016 16:54:58 +0000 (16:54 +0000)]
Fix test/Analysis/ScalarEvolution/scev-expander-existing-value-offset.ll for rL276136.
The content in this testcase was accidentally duplicated. Fix the error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276139
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Wei Mi [Wed, 20 Jul 2016 16:40:33 +0000 (16:40 +0000)]
Use ValueOffsetPair to enhance value reuse during SCEV expansion.
In D12090, the ExprValueMap was added to reuse existing value during SCEV expansion.
However, const folding and sext/zext distribution can make the reuse still difficult.
A simplified case is: suppose we know S1 expands to V1 in ExprValueMap, and
S1 = S2 + C_a
S3 = S2 + C_b
where C_a and C_b are different SCEVConstants. Then we'd like to expand S3 as
V1 - C_a + C_b instead of expanding S2 literally. It is helpful when S2 is a
complex SCEV expr and S2 has no entry in ExprValueMap, which is usually caused
by the fact that S3 is generated from S1 after const folding.
In order to do that, we represent ExprValueMap as a mapping from SCEV to
ValueOffsetPair. We will save both S1->{V1, 0} and S2->{V1, C_a} into the
ExprValueMap when we create SCEV for V1. When S3 is expanded, it will first
expand S2 to V1 - C_a because of S2->{V1, C_a} in the map, then expand S3 to
V1 - C_a + C_b.
Differential Revision: https://reviews.llvm.org/D21313
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276136
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Sanjay Patel [Wed, 20 Jul 2016 16:30:55 +0000 (16:30 +0000)]
fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276135
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Matt Arsenault [Wed, 20 Jul 2016 15:20:35 +0000 (15:20 +0000)]
AMDGPU: Add missing test coverage for control flow breaks
None of the current lit tests hit si_break handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276129
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Yaxun Liu [Wed, 20 Jul 2016 14:38:06 +0000 (14:38 +0000)]
AMDGPU: Fix bug causing crash due to invalid opencl version metadata.
Differential Revision: https://reviews.llvm.org/D22526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276119
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Renato Golin [Wed, 20 Jul 2016 12:16:38 +0000 (12:16 +0000)]
[docs] Fixing Sphinx warnings to unclog the buildbot
Lots of blocks had "llvm" or "nasm" syntax types but either weren't following
the syntax, or the syntax has changed (and sphinx hasn't keep up) or the type
doesn't even exist (nasm?).
Other documents had :options: what were invalid. I only removed those that had
warnings, and left the ones that didn't, in order to follow the principle of
least surprise.
This is like this for ages, but the buildbot is now failing on errors. It may
take a while to upgrade the buildbot's sphinx, if that's even possible, but
that shouldn't stop us from getting docs updates (which seem down for quite
a while).
Also, we're not losing any syntax highlight, since when it doesn't parse, it
doesn't colour. Ie. those blocks are not being highlighted anyway.
I'm trying to get all docs in one go, so that it's easy to revert later if we
do fix, or at least easy to know what's to fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276109
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Benjamin Kramer [Wed, 20 Jul 2016 11:40:16 +0000 (11:40 +0000)]
Revert "[InstCombine] Enable cast-folding in logic(cast(icmp), cast(icmp))"
Makes InstCombine infloop when compiling v8.
This reverts commit r275989 and r276105.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276106
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Tobias Grosser [Wed, 20 Jul 2016 11:24:27 +0000 (11:24 +0000)]
[InstCombine] Provide more test cases for cast-folding [NFC]
Summary: In r275989 we enabled the folding of `logic(cast(icmp), cast(icmp))` to `cast(logic(icmp, icmp))`. Here we add more test cases to assure this folding works for all logical operations `and`/`or`/`xor`.
Reviewers: grosser
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D22561
Contributed-by: Matthias Reisinger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276105
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Simon Pilgrim [Wed, 20 Jul 2016 10:41:28 +0000 (10:41 +0000)]
[X86][SSE] Add cost model values for CTPOP of vectors
This patch adds costs for the vectorized implementations of CTPOP, the default values were seriously underestimating the cost of these and was encouraging vectorization on targets where serialized use of POPCNT would be much better.
Differential Revision: https://reviews.llvm.org/D22456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276104
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Diana Picus [Wed, 20 Jul 2016 09:48:24 +0000 (09:48 +0000)]
[ARM] Skip inline asm memory operands in DAGToDAGISel
Retry r275776 (no changes, we suspect the issue was with another commit).
The current logic for handling inline asm operands in DAGToDAGISel interprets
the operands by looking for constants, which should represent the flags
describing the kind of operand we're dealing with (immediate, memory, register
def etc). The operands representing actual data are skipped only if they are
non-const, with the exception of immediate operands which are skipped explicitly
when a flag describing an immediate is found.
The oversight is that memory operands may be const too (e.g. for device drivers
reading a fixed address), so we should explicitly skip the operand following a
flag describing a memory operand. If we don't, we risk interpreting that
constant as a flag, which is definitely not intended.
Fixes PR26038
Differential Revision: https://reviews.llvm.org/D22103
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276101
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Renato Golin [Wed, 20 Jul 2016 09:47:09 +0000 (09:47 +0000)]
[docs] fix cmake code-block warning
This will unblock the llvm-sphinx-buildbot, which is currently failing due
to a warning being treated as error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276100
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Renato Golin [Wed, 20 Jul 2016 09:38:04 +0000 (09:38 +0000)]
[docs] Add proposals to index file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276099
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Renato Golin [Wed, 20 Jul 2016 09:09:58 +0000 (09:09 +0000)]
[docs] GitHub Proposal for LLVM
This document was crafted from the various (320+) emails between 2nd June and
20th July regarding the move to GitHub. It tried to consolidate every issue that
was raised and every solution that was presented to have a GitHub repository
with sub-modules.
It *does not* try to argue whether sub-modules are better or worse than any other
Git solution, nor if Git is better than any other VCS, nor if GitHub is better
than any other free code hosting service. This is just the final conclusions of
48 days and 320 emails (plus a lot of IRC discussions) on the LLVM community.
This document will be presented at the survey that the foundation will setup for
us to decide if we move to this solution or not. It reflects what was discussed
on the lists, but it's not authoritative. If something is not clear enough,
please refer to the mailing list discussions (hint: search for "GitHub").
Review: https://reviews.llvm.org/D22463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276097
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