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Sanjay Patel [Mon, 12 Feb 2018 19:23:39 +0000 (19:23 +0000)]
[InstCombine] add tests for missing fdiv fold; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324926
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Sanjay Patel [Mon, 12 Feb 2018 19:14:01 +0000 (19:14 +0000)]
[InstCombine] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324924
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Sanjay Patel [Mon, 12 Feb 2018 18:38:35 +0000 (18:38 +0000)]
[InstCombine] various clean-ups for div transforms; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324922
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Jun Bum Lim [Mon, 12 Feb 2018 17:56:55 +0000 (17:56 +0000)]
[LICM] update BlockColors after splitting predecessors
Update BlockColors after splitting predecessors. Do not allow splitting
EHPad for sinking when the BlockColors is not empty, so we can
simply assign predecessor's color to the new block.
Fixes PR36184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324916
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Abderrazek Zaafrani [Mon, 12 Feb 2018 17:35:42 +0000 (17:35 +0000)]
[AArch64] Fixes for ARMv8.2-A FP16 scalar intrinsic - llvm portion
https://reviews.llvm.org/D42993
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324912
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Simon Pilgrim [Mon, 12 Feb 2018 17:21:28 +0000 (17:21 +0000)]
[X86] Add missing scheduling class tag for i64 absolute address moves
Expand existing SchedRW to encompass these like it did for the other memory offset movs - added comments to closing braces to keep track of def scopes.
We only tagged it with the itinerary class, so completeness checks were erroneously passed (PR35639).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324910
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Oliver Stannard [Mon, 12 Feb 2018 17:03:11 +0000 (17:03 +0000)]
[AArch64] Improve v8.1-A code-gen for atomic load-and
Armv8.1-A added an atomic load-clear instruction (which performs bitwise
and with the complement of it's operand), but not a load-and
instruction. Our current code-generation for atomic load-and always
inserts an MVN instruction to invert its argument, even if it could be
folded into a constant or another instruction.
This adds lowering early in selection DAG to convert a load-and
operation into an xor with -1 and a load-clear, allowing the normal DAG
optimisations to work on it.
To do this, I've had to add a new ISD opcode, ATOMIC_LOAD_CLR. I don't
see any easy way to do this with an AArch64-specific ISD node, because
the code-generation for atomic operations assumes the SDNodes are of
type AtomicSDNode.
I've left the old tablegen patterns in because they are still needed for
global isel.
Differential revision: https://reviews.llvm.org/D42478
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324908
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Simon Pilgrim [Mon, 12 Feb 2018 16:59:04 +0000 (16:59 +0000)]
[X86][AVX512] Add missing scheduling class tag for KMOVB/KMOVW/KMOVD/KMOVQ moves/loads/stores.
We only tagged it with the itinerary class, so completeness checks were erroneously passed (PR35639).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324905
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Evandro Menezes [Mon, 12 Feb 2018 16:41:41 +0000 (16:41 +0000)]
[AArch64] Refactor identification of SIMD immediates
Get rid of icky goto loops and make the code easier to maintain (NFC).
Differential revision: https://reviews.llvm.org/D42723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324903
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Simon Pilgrim [Mon, 12 Feb 2018 16:18:36 +0000 (16:18 +0000)]
[X86][AVX512] Add missing scheduling class tag for VMOVQ/VMOVHLPS/VMOVLHPS/VMOVHPD/VMOVHPS/VMOVLPD/VMOVLPS
Tag AVX512 variants to match SSE/AVX originals.
We only tagged it with the itinerary class, so completeness checks were erroneously passed (PR35639).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324901
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Momchil Velikov [Mon, 12 Feb 2018 16:10:09 +0000 (16:10 +0000)]
Re-commit r324489: [DebugInfo] Improvements to representation of enumeration types (PR36168)
Differential Revision: https://reviews.llvm.org/D42734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324899
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Simon Pilgrim [Mon, 12 Feb 2018 15:57:00 +0000 (15:57 +0000)]
[X86] Tag CET-IBT instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324898
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Simon Pilgrim [Mon, 12 Feb 2018 15:52:59 +0000 (15:52 +0000)]
[X86][MMX] Add missing scheduling class tag for EMMS/FEMMS
We only tagged it with the itinerary class, so completeness checks were erroneously passed (PR35639).
AMD targets can perform these a lot quicker than WriteMicrocoded so will need an override in the models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324897
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Krzysztof Parzyszek [Mon, 12 Feb 2018 15:02:49 +0000 (15:02 +0000)]
[NFC] Fix comment of class InstrStage
Patch by Wei-Ren Chen.
Differential Revision: https://reviews.llvm.org/D42905
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324894
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Alexey Bataev [Mon, 12 Feb 2018 14:54:48 +0000 (14:54 +0000)]
[SLP] Take user instructions cost into consideration in insertelement vectorization.
Summary:
For better vectorization result we should take into consideration the
cost of the user insertelement instructions when we try to
vectorize sequences that build the whole vector. I.e. if we have the
following scalar code:
```
<Scalar code>
insertelement <ScalarCode>, ...
```
we should consider the cost of the last `insertelement ` instructions as
the cost of the scalar code.
Reviewers: RKSimon, spatel, hfinkel, mkuper
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D42657
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324893
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Oliver Stannard [Mon, 12 Feb 2018 14:22:03 +0000 (14:22 +0000)]
[AArch64] Improve v8.1-A code-gen for atomic load-subtract
Armv8.1-A added an atomic load-add instruction, but not a load-subtract
instruction. Our current code-generation for atomic load-subtract always
inserts a NEG instruction to negate it's argument, even if it could be
folded into a constant or another instruction.
This adds lowering early in selection DAG to convert a load-subtract
operation into a subtract and a load-add, allowing the normal DAG
optimisations to work on it.
I've left the old tablegen patterns in because they are still needed for
global isel.
Some of the tests in this patch are copied from D35375 by Chad Rosier (which
was abandoned).
Differential revision: https://reviews.llvm.org/D42477
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324892
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Sanjay Patel [Mon, 12 Feb 2018 14:14:56 +0000 (14:14 +0000)]
[InstCombine] various clean-ups for commonIDivTransforms; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324891
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Nicholas Wilson [Mon, 12 Feb 2018 13:17:09 +0000 (13:17 +0000)]
Test commit: reformat comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324889
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Hans Wennborg [Mon, 12 Feb 2018 12:43:39 +0000 (12:43 +0000)]
Revert r324835 "[X86] Reduce Store Forward Block issues in HW"
It asserts building Chromium; see PR36346.
(This also reverts the follow-up r324836.)
> If a load follows a store and reloads data that the store has written to memory, Intel microarchitectures can in many cases forward the data directly from the store to the load, This "store forwarding" saves cycles by enabling the load to directly obtain the data instead of accessing the data from cache or memory.
> A "store forward block" occurs in cases that a store cannot be forwarded to the load. The most typical case of store forward block on Intel Core microarchiticutre that a small store cannot be forwarded to a large load.
> The estimated penalty for a store forward block is ~13 cycles.
>
> This pass tries to recognize and handle cases where "store forward block" is created by the compiler when lowering memcpy calls to a sequence
> of a load and a store.
>
> The pass currently only handles cases where memcpy is lowered to XMM/YMM registers, it tries to break the memcpy into smaller copies.
> breaking the memcpy should be possible since there is no atomicity guarantee for loads and stores to XMM/YMM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324887
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Simon Atanasyan [Mon, 12 Feb 2018 12:21:55 +0000 (12:21 +0000)]
[mips] Fix 'l' constraint handling for types smaller than 32 bits
In case of correct using of the 'l' constraint llvm now generates valid
code; otherwise it shows an error message. Initially these triggers an
assertion.
This commit is the same as r324869 with fixed the test's file name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324885
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Simon Atanasyan [Mon, 12 Feb 2018 11:15:37 +0000 (11:15 +0000)]
[mips] Revert rL324869
This commit adds inlineasm-cnstrnt-bad-l.ll which is clashing
with inlineasm-cnstrnt-bad-L.ll on case insensitive file systems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324882
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Florian Hahn [Mon, 12 Feb 2018 11:10:58 +0000 (11:10 +0000)]
[LoopInterchange] Simplify splitInnerLoopHeader logic (NFC).
We can use SplitBlock for both cases, which makes the code slightly
simpler and updates both LoopInfo and the dominator tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324881
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David Green [Mon, 12 Feb 2018 11:06:27 +0000 (11:06 +0000)]
[CodeGen] Add a -trap-unreachable option for debugging
Add a common -trap-unreachable option, similar to the target
specific hexagon equivalent, which has been replaced. This
turns unreachable instructions into traps, which is useful for
debugging.
Differential Revision: https://reviews.llvm.org/D42965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324880
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Sam McCall [Mon, 12 Feb 2018 10:20:09 +0000 (10:20 +0000)]
[gtest] Support raw_ostream printing functions more comprehensively.
Summary:
These are functions like operator<<(raw_ostream&, Foo).
Previously these were only supported for messages. In the assertion
EXPECT_EQ(A, B) << C;
the local modifications would explicitly try to use raw_ostream printing for C.
However A and B would look for a std::ostream printing function, and often fall
back to gtest's default "168 byte object <00 01 FE 42 ...>".
This patch pulls out the raw_ostream support into a new header under `custom/`.
I changed the mechanism: instead of a convertible stream, we wrap the printed
value in a proxy object to allow it to be sent to a std::ostream.
I think the new way is clearer.
I also changed the policy: we prefer raw_ostream printers over std::ostream
ones. This is because the fallback printers are defined using std::ostream,
while all the raw_ostream printers should be "good".
Reviewers: ilya-biryukov, chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43091
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324876
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Simon Atanasyan [Mon, 12 Feb 2018 07:51:21 +0000 (07:51 +0000)]
[mips] Fix 'l' constraint handling for types smaller than 32 bits
In case of correct using of the 'l' constraint llvm now generates valid
code; otherwise it shows an error message. Initially these triggers an
assertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324869
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Gerolf Hoflehner [Mon, 12 Feb 2018 07:19:05 +0000 (07:19 +0000)]
[MC] Issue error message when data region is not terminated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324868
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Max Kazantsev [Mon, 12 Feb 2018 05:16:28 +0000 (05:16 +0000)]
[NFC] Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324867
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Max Kazantsev [Mon, 12 Feb 2018 05:09:38 +0000 (05:09 +0000)]
[SCEV] Make getPostIncExpr guaranteed to return AddRec
The current implementation of `getPostIncExpr` invokes `getAddExpr` for two recurrencies
and expects that it always returns it a recurrency. But this is not guaranteed to happen if we
have reached max recursion depth or refused to make SCEV simplification for other reasons.
This patch changes its implementation so that now it always returns SCEVAddRec without
relying on `getAddExpr`.
Differential Revision: https://reviews.llvm.org/D42953
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324866
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Craig Topper [Mon, 12 Feb 2018 03:02:02 +0000 (03:02 +0000)]
[X86] Don't look for TEST instruction shrinking opportunities when the root node is a X86ISD::SUB.
I don't believe we ever create an X86ISD::SUB with a 0 constant which is what the TEST handling needs. The ternary operator at the end of this code shows up as only going one way in the llvm-cov report from the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324865
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Craig Topper [Mon, 12 Feb 2018 03:02:01 +0000 (03:02 +0000)]
[X86] Remove check for X86ISD::AND with no flag users from the TEST instruction immediate shrinking code.
We turn X86ISD::AND with no flag users back to ISD::AND in PreprocessISelDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324864
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Craig Topper [Mon, 12 Feb 2018 02:48:42 +0000 (02:48 +0000)]
[X86] Change some compare patterns to use loadi8/loadi16/loadi32/loadi64 helper fragments.
This enables CMP8mi to fold zextloadi8i1 which in all tests allows us to avoid creating a TEST8rr that peephole can't fold.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324863
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Craig Topper [Mon, 12 Feb 2018 02:03:36 +0000 (02:03 +0000)]
[X86] Autogenerate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324862
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Craig Topper [Mon, 12 Feb 2018 01:33:38 +0000 (01:33 +0000)]
[X86] Add KADD X86ISD opcode instead of reusing ISD::ADD.
ISD::ADD implies individual vector element addition with no carries between elements. But for a vXi1 type that would be the same as XOR. And we already turn ISD::ADD into ISD::XOR for all vXi1 types during lowering. So the ISD::ADD pattern would never be able to match anyway.
KADD is different, it adds the elements but also propagates a carry between them. This just a way of doing an add in k-register without bitcasting to the scalar domain. There's still no way to match the pattern, but at least its not obviously wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324861
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Craig Topper [Mon, 12 Feb 2018 01:33:36 +0000 (01:33 +0000)]
[X86] Allow zextload/extload i1->i8 to be folded into instructions during isel
Previously we just emitted this as a MOV8rm which would likely get folded during the peephole pass anyway. This just makes it explicit earlier.
The gpr-to-mask.ll test changed because the kaddb instruction has no memory form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324860
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Charles Saternos [Mon, 12 Feb 2018 00:20:16 +0000 (00:20 +0000)]
Follow on to rL324854 (Added tests)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324859
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Craig Topper [Sun, 11 Feb 2018 22:32:30 +0000 (22:32 +0000)]
[X86] Remove MASK_BINOP intrinsic type. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324858
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Craig Topper [Sun, 11 Feb 2018 22:32:29 +0000 (22:32 +0000)]
[X86] Remove dead code from getMaskNode that looked for a i64 mask with a maskVT that wasn't v64i1. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324857
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Craig Topper [Sun, 11 Feb 2018 22:32:27 +0000 (22:32 +0000)]
[X86] Remove LowerBoolVSETCC_AVX512, we get this with a target independent DAG combine now. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324856
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Charles Saternos [Sun, 11 Feb 2018 22:06:20 +0000 (22:06 +0000)]
[ThinLTO] Add GraphTraits for FunctionSummaries
Add GraphTraits definitions to the FunctionSummary and ModuleSummaryIndex classes. These GraphTraits will be used to construct find SCC's in ThinLTO analysis passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324854
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Brock Wyma [Sun, 11 Feb 2018 21:26:46 +0000 (21:26 +0000)]
[CodeView] Allow variable names to be as long as the codeview format supports
Instead of reserving 0xF00 bytes for the fixed length portion of the CodeView
symbol name, calculate the actual length of the fixed length portion.
Differential Revision: https://reviews.llvm.org/D42125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324850
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Craig Topper [Sun, 11 Feb 2018 18:52:16 +0000 (18:52 +0000)]
[X86] Update some required-vector-width.ll test cases to not pass 512-bit vectors in arguments or return.
ABI for these would require 512 bits support so we don't want to test that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324845
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Simon Pilgrim [Sun, 11 Feb 2018 17:29:42 +0000 (17:29 +0000)]
[X86][SSE] Use SplitBinaryOpsAndApply to recognise PSUBUS patterns before they're split on AVX1
This needs to be generalised further to support AVX512BW cases but I want to add non-uniform constants first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324844
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Sanjay Patel [Sun, 11 Feb 2018 17:20:32 +0000 (17:20 +0000)]
[InstCombine] X / (X * Y) -> 1 / Y if the multiplication does not overflow
The related cases for (X * Y) / X were handled in rL124487.
https://rise4fun.com/Alive/6k9
The division in these tests is subsequently eliminated by existing instcombines
for 1/X.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324843
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Craig Topper [Sun, 11 Feb 2018 17:11:40 +0000 (17:11 +0000)]
[X86] Use min/max for vector ult/ugt compares if avoids a sign flip.
Summary:
Currently we only use min/max to help with ule/uge compares because it removes an invert of the result that would otherwise be needed. But we can also use it for ult/ugt compares if it will prevent the need for a sign bit flip needed to use pcmpgt at the cost of requiring an invert after the compare.
I also refactored the code so that the max/min code is self contained and does its own return instead of setting up a flag to manipulate the rest of the function's behavior.
Most of the test cases look ok with this. I did notice that we added instructions when one of the operands being sign flipped is a constant vector that we were able to constant fold the flip into.
I also noticed that sometimes the SSE min/max clobbers a register that is needed after the compare. This resulted in an extra move being inserted before the min/max to preserve the register. We could try to detect this and switch from min to max and change the compare operands to use the operand that gets reused in the compare.
Reviewers: spatel, RKSimon
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42935
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324842
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Simon Pilgrim [Sun, 11 Feb 2018 17:01:43 +0000 (17:01 +0000)]
[X86][SSE] Moved SplitBinaryOpsAndApply earlier so more methods can use it. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324841
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Sanjay Patel [Sun, 11 Feb 2018 16:52:44 +0000 (16:52 +0000)]
[InstCombine] add tests for div-mul folds; NFC
The related cases for (X * Y) / X were handled in rL124487.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324840
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Sanjay Patel [Sun, 11 Feb 2018 14:38:23 +0000 (14:38 +0000)]
[TargetLowering] try to create -1 constant operand for math ops via demanded bits
This reverses instcombine's demanded bits' transform which always tries to clear bits in constants.
As noted in PR35792 and shown in the test diffs:
https://bugs.llvm.org/show_bug.cgi?id=35792
...we can do better in codegen by trying to form -1. The x86 sub test shows a missed opportunity.
I did investigate changing instcombine's behavior, but it would be more work to change
canonicalization in IR. Clearing bits / shrinking constants can allow killing instructions,
so we'd have to figure out how to not regress those cases.
Differential Revision: https://reviews.llvm.org/D42986
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324839
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Simon Pilgrim [Sun, 11 Feb 2018 13:12:50 +0000 (13:12 +0000)]
[X86] Add PR33747 test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324838
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Simon Pilgrim [Sun, 11 Feb 2018 10:52:37 +0000 (10:52 +0000)]
[X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types
This allows us to recognise more saturation patterns and also simplify some MINMAX codegen that was failing to combine CMPGE comparisons to a legal CMPGT.
Differential Revision: https://reviews.llvm.org/D43014
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324837
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Lama Saba [Sun, 11 Feb 2018 10:33:06 +0000 (10:33 +0000)]
fix test/CodeGen/X86/fixup-sfb.ll test failure after commit https://reviews.llvm.org/rL324835
Change-Id: I2526c2f342654e85ce054237de03ae9db9ab4994
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324836
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Lama Saba [Sun, 11 Feb 2018 09:34:12 +0000 (09:34 +0000)]
[X86] Reduce Store Forward Block issues in HW
If a load follows a store and reloads data that the store has written to memory, Intel microarchitectures can in many cases forward the data directly from the store to the load, This "store forwarding" saves cycles by enabling the load to directly obtain the data instead of accessing the data from cache or memory.
A "store forward block" occurs in cases that a store cannot be forwarded to the load. The most typical case of store forward block on Intel Core microarchiticutre that a small store cannot be forwarded to a large load.
The estimated penalty for a store forward block is ~13 cycles.
This pass tries to recognize and handle cases where "store forward block" is created by the compiler when lowering memcpy calls to a sequence
of a load and a store.
The pass currently only handles cases where memcpy is lowered to XMM/YMM registers, it tries to break the memcpy into smaller copies.
breaking the memcpy should be possible since there is no atomicity guarantee for loads and stores to XMM/YMM.
Change-Id: I620b6dc91583ad9a1444591e3ddc00dd25d81748
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324835
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Craig Topper [Sun, 11 Feb 2018 08:06:27 +0000 (08:06 +0000)]
[X86] Don't make 512-bit vectors legal when preferred vector width is 256 bits and 512 bits aren't required
This patch adds a new function attribute "required-vector-width" that can be set by the frontend to indicate the maximum vector width present in the original source code. The idea is that this would be set based on ABI requirements, intrinsics or explicit vector types being used, maybe simd pragmas, etc. The backend will then use this information to determine if its save to make 512-bit vectors illegal when the preference is for 256-bit vectors.
For code that has no vectors in it originally and only get vectors through the loop and slp vectorizers this allows us to generate code largely similar to our AVX2 only output while still enabling AVX512 features like mask registers and gather/scatter. The loop vectorizer doesn't always obey TTI and will create oversized vectors with the expectation the backend will legalize it. In order to avoid changing the vectorizer and potentially harm our AVX2 codegen this patch tries to make the legalizer behavior similar.
This is restricted to CPUs that support AVX512F and AVX512VL so that we have good fallback options to use 128 and 256-bit vectors and still get masking.
I've qualified every place I could find in X86ISelLowering.cpp and added tests cases for many of them with 2 different values for the attribute to see the codegen differences.
We still need to do frontend work for the attribute and teach the inliner how to merge it, etc. But this gets the codegen layer ready for it.
Differential Revision: https://reviews.llvm.org/D42724
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324834
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Craig Topper [Sun, 11 Feb 2018 07:44:33 +0000 (07:44 +0000)]
[X86] Remove setOperationAction lines for promoting vXi1 SINT_TO_FP/UINT_TO_FP.
We promote these via a DAG combine now before lowering gets the chance.
Also remove the v2i1 custom handling since it will no longer be triggered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324833
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Craig Topper [Sun, 11 Feb 2018 04:58:58 +0000 (04:58 +0000)]
[SelectionDAG] Remove TargetLowering::getConstTrueVal. Use SelectionDAG::getBoolConstant in the one place it was used.
SelectionDAG::getBoolConstant was recently introduced. At the time I didn't know getConstTrueVal existed, but I think getBoolConstant is better as it will use the source VT to make sure it can properly detect floating point if it is configured differently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324832
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Craig Topper [Sun, 11 Feb 2018 03:07:19 +0000 (03:07 +0000)]
[X86] Remove some redundant qualifications from the setOperationAction blocks. NFC
These were added as part of the refactoring for prefer vector width. At the time I thought the hasAVX512 here would be replaced with "allow 512 bit vectors" so that it would read "allow 512 bit vectors OR VLX". But now the plan is to only give the option of disabling 512 bit vectors when VLX is enabled. So we don't need this qualification at all
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324831
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Simon Pilgrim [Sat, 10 Feb 2018 23:38:50 +0000 (23:38 +0000)]
[X86][SSE] Add SMIN/SMAX combine test
As discussed on D43014, we need the ability to flip SMIN/SMAX to (legal) UMIN/UMAX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324829
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Craig Topper [Sat, 10 Feb 2018 23:33:55 +0000 (23:33 +0000)]
[X86] Change signatures of avx512 packed fp compare intrinsics to return a vXi1 mask type to be closer to an fcmp.
Summary:
This patch changes the signature of the avx512 packed fp compare intrinsics to return a vXi1 vector and no longer take a mask as input. The casts to scalar type will now need to be explicit in the IR. The masking node will now be an explicit and in the IR.
This makes the intrinsic look much more similar to an fcmp instruction that we wish we could use for these but can't. We already use icmp instructions for integer compares.
Previously the lowering step of isel would turn the intrinsic into an X86 specific ISD node and a emit the masking nodes as well as some bitcasts. This means DAG combines can't see the vXi1 type until somewhat late, making it more difficult to combine out gpr<->mask transition sequences. By exposing the vXi1 type explicitly in the IR and initial SelectionDAG we give earlier DAG combines and even InstCombine the chance to see it and optimize it.
This should make any issues with gpr<->mask sequences the same between integer and fp. Meaning we only have to fix them once.
Reviewers: spatel, delena, RKSimon, zvi
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43137
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324827
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Simon Pilgrim [Sat, 10 Feb 2018 22:27:35 +0000 (22:27 +0000)]
[X86][SSE] Add UMIN/UMAX combine test
As discussed on D43014, we need the ability to flip UMIN/UMAX to (legal) SMIN/SMAX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324826
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Simon Pilgrim [Sat, 10 Feb 2018 21:46:09 +0000 (21:46 +0000)]
[InstCombine] Add constant vector support for ~(C >> Y) --> ~C >> Y
Includes adding m_NonNegative constant pattern matcher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324825
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Simon Pilgrim [Sat, 10 Feb 2018 19:27:10 +0000 (19:27 +0000)]
[X86][SSE] Increase PMULLD costs to better match hardware
Until Skylake, most hardware could only issue a PMULLD op every other cycle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324823
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Craig Topper [Sat, 10 Feb 2018 19:12:58 +0000 (19:12 +0000)]
[X86] Custom legalize (v2i32 (setcc (v2f32))) so that we don't end up with a (v4i1 (setcc (v4f32)))
Undef VLX, getSetCCResultType returns v2i1/v4i1 for v2f32/v4f32 so default type legalization will end up changing the setcc result type back to vXi1 if it had been extended. The resulting extend gets messed up further by type legalization and is difficult to recombine back to (v4i32 (setcc (v4f32))) after legalization.
I went ahead and enabled this for SSE2 and later since its always the result we want and this helps type legalization get there in less steps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324822
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Craig Topper [Sat, 10 Feb 2018 17:58:58 +0000 (17:58 +0000)]
[X86] Extend inputs with elements smaller than i32 to sint_to_fp/uint_to_fp before type legalization.
This prevents extends of masks being introduced during lowering where it become difficult to combine them out.
There are a few oddities in here.
We sometimes concatenate two k-registers produced by two compares, sign_extend the combined pair, then extract two halves. This worked better previously because the sign_extend wasn't created until after the fp_to_sint was split which led to a split sign_extend being created.
We probably also need to custom type legalize (v2i32 (sext v2i1)) via widening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324820
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Craig Topper [Sat, 10 Feb 2018 17:58:56 +0000 (17:58 +0000)]
[X86] Remove some check-prefixes from avx512-cvt.ll to prepare for an upcoming patch.
The update script sometimes has trouble when there are check-prefixes representing every possible combination of feature flags. I have a patch where the update script was generating something that didn't pass lit.
This patch just removes some check-prefixes and expands out some of the checks to workaround this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324819
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Sanjay Patel [Sat, 10 Feb 2018 15:36:23 +0000 (15:36 +0000)]
[x86] preserve test intent by removing undef
D43141 proposes to correct undef folding in the DAG,
and this test would not survive that change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324817
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Sanjay Patel [Sat, 10 Feb 2018 15:28:08 +0000 (15:28 +0000)]
[x86] preserve test intent by removing undef
D43141 proposes to correct undef folding in the DAG,
and this test would not survive that change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324816
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Simon Pilgrim [Sat, 10 Feb 2018 15:14:00 +0000 (15:14 +0000)]
Fix Wdocumentation warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324815
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Sanjay Patel [Sat, 10 Feb 2018 15:14:00 +0000 (15:14 +0000)]
[ARM] preserve test intent by removing undef
D43141 proposes to correct undef folding in the DAG,
and this test would not survive that change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324814
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Simon Pilgrim [Sat, 10 Feb 2018 15:02:07 +0000 (15:02 +0000)]
Fix Wdocumentation warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324813
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Simon Pilgrim [Sat, 10 Feb 2018 14:45:58 +0000 (14:45 +0000)]
[X86][SSE] Regenerate old sitofp v2i32 test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324812
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Craig Topper [Sat, 10 Feb 2018 08:39:31 +0000 (08:39 +0000)]
[X86] Custom legalize (v2i1 (fp_to_uint/fp_to_sint v2f64)) without AVX512VL.
Strangely the code was already present, just the setOperationAction wasn't being called without VLX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324806
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Craig Topper [Sat, 10 Feb 2018 08:06:52 +0000 (08:06 +0000)]
[X86] Legalize zero extends from vXi1 to vXi16/vXi32/vXi64 using a sign extend and a shift.
This avoids a constant pool load to create 1.
The int->float are showing converts to mask and back. We probably need to widen inputs to sint_to_fp/uint_to_fp before type legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324805
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Craig Topper [Sat, 10 Feb 2018 08:06:49 +0000 (08:06 +0000)]
[X86] Teach combineExtSetcc to handle ZERO_EXTEND by widening the setcc and then masking. A later DAG combine will convert to a shift.
This helps to avoid a constant pool load needed to zero extend from the mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324804
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Fangrui Song [Sat, 10 Feb 2018 05:01:33 +0000 (05:01 +0000)]
[utils] Refactor utils/update_{,llc_}test_checks.py to share more code
Summary:
This revision refactors 1. parser 2. CHECK line adder of utils/update_{,llc_}test_checks.py
so that thir functionality can be re-used by other utility scripts (e.g. D42712)
Reviewers: asb, craig.topper, RKSimon, echristo
Subscribers: llvm-commits, spatel
Differential Revision: https://reviews.llvm.org/D42805
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324803
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Nirav Dave [Sat, 10 Feb 2018 02:41:22 +0000 (02:41 +0000)]
[DAG] Make early exit hasPredecessorHelper return true. NFCI.
All uses conservatively assume in early exit case that it will be a
predecessor. Changing default removes checking code in all uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324797
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Craig Topper [Sat, 10 Feb 2018 01:00:41 +0000 (01:00 +0000)]
[X86] Teach combineInsertSubvector how to combine some k-register insert_subvectors and extract_subvector sequences to remove extra zeroing.wq
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324791
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George Karpenkov [Sat, 10 Feb 2018 00:38:21 +0000 (00:38 +0000)]
Make LLVM timer reprintable: that is, make more than one print action on the same timer feasible
Currently, each LLVM timer can be only printed once, as the act of
printing clears the timer.
Moreover, the current printing mechanism implicitly assumes that the
timer is stopped -- and prints zero otherwise.
This patch relaxes this assumption and makes printing statistics
multiple time a possibility.
Differential Revision: https://reviews.llvm.org/D43136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324788
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David Blaikie [Sat, 10 Feb 2018 00:14:54 +0000 (00:14 +0000)]
REQUIRES: shell a couple of tests that require the shell
One test uses diff, the other tries to change the PATH which doesn't
seem to work well ('not' is no longer accessible/found after the PATH is
changed - I think $PATH isn't expanded when setting PATH).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324787
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Mircea Trofin [Sat, 10 Feb 2018 00:07:45 +0000 (00:07 +0000)]
[LV] Fix analyzeInterleaving when -pass-remarks enabled
Summary:
If -pass-remarks=loop-vectorize, atomic ops will be seen by
analyzeInterleaving(), even though canVectorizeMemory() == false. This
is because we are requesting extra analysis instead of bailing out.
In such a case, we end up with a Group in both Load- and StoreGroups,
and then we'll try to access freed memory when traversing LoadGroups after having had released the Group when iterating over StoreGroups.
The fix is to include mayWriteToMemory() when validating that two
instructions are the same kind of memory operation.
Reviewers: mssimpso, davidxl
Reviewed By: davidxl
Subscribers: hsaito, fhahn, llvm-commits
Differential Revision: https://reviews.llvm.org/D43064
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324786
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Daniel Neilson [Fri, 9 Feb 2018 23:33:35 +0000 (23:33 +0000)]
[Hexagon] Update uses of deprecated IRBuilder CreateMemCpy/Move calls
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
Hexagon LoopIdiom pass to cease using the old IRBuilder createMemCpy/createMemMove
single-alignment APIs in favour of the new API that allows setting source and
destination alignments independently.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774,
rL324781 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324784
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Alexander Shaposhnikov [Fri, 9 Feb 2018 23:33:31 +0000 (23:33 +0000)]
[llvm-objcopy] Make modifications in-place if output is not specified
If the output file is not specified make the modifications in-place
(like binutils objcopy does). In particular, this fixes
the behavior of Clang -gsplit-dwarf (if Clang is configured to use llvm-objcopy),
previously it was creating .dwo files, but still leaving *dwo* sections in
the original binary.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D42873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324783
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Craig Topper [Fri, 9 Feb 2018 23:32:27 +0000 (23:32 +0000)]
[X86] Teach lower1BitVectorShuffle to recognize shuffles that are just filling upper elements with zero. Replace with insert_subvector.
There's still some extra kshifts in one of the modified test cases here, but hopefully that's only a DAG combine away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324782
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Daniel Neilson [Fri, 9 Feb 2018 23:31:37 +0000 (23:31 +0000)]
[ARMFastISel] Replace deprecated calls to MemoryIntrinsic::getAlignment() (NFCI)
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes
ARMFastISel to cease using the old getAlignment() API of MemoryIntrinsic in favour of getting
source & dest specific alignments through the new API.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324781
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Justin Bogner [Fri, 9 Feb 2018 23:25:23 +0000 (23:25 +0000)]
CMake: Allow specifying arbitrary CCACHE parameters
Introduces the LLVM_CCACHE_PARAMS cmake variable, which can be used to
pass arbitrary parameters to ccache invocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324779
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Dan Gohman [Fri, 9 Feb 2018 23:13:22 +0000 (23:13 +0000)]
[WebAssembly] Add mechanisms for specifying an explicit import module name.
This adds a wasm-import-module function attribute and a .import_module
assembler directive, for specifying module import names for WebAssembly.
Currently these may only be used for function symbols; global variables
may be considered in the future.
WebAssembly has a two-level namespace scheme for symbols, and it's
normally the linker's job to assign the module name, which is the
first-level name. The attributes here allow users to specify their
own module names explicitly, which is useful for tools generating
bindings to modules defined in other languages.
This feature is not fully usable yet. It will evolve along with the
ongoing symbol table and lld changes.
Differential Revision: https://reviews.llvm.org/D42520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324778
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Dan Gohman [Fri, 9 Feb 2018 22:59:01 +0000 (22:59 +0000)]
[WebAssembly] Add an LLVM_FALLTHROUGH to address a warning. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324777
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Daniel Neilson [Fri, 9 Feb 2018 21:56:15 +0000 (21:56 +0000)]
[AMDGPUPromoteAlloca] Replace deprecated memory intrinsic APIs (NFCI)
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
AMDGPUPromoteAlloca pass to cease using:
1) The old getAlignment() API of MemoryIntrinsic in favour of getting source & dest specific
alignments through the new API.
2) The old IRBuilder createMemCpy/createMemMove single-alignment APIs in favour of the new
API that allows setting source and destination alignments independently.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, r323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324774
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Daniel Neilson [Fri, 9 Feb 2018 21:49:29 +0000 (21:49 +0000)]
[AArch64FastISel] Replace deprecated calls to MemoryIntrinsic::getAlignment() (NFCI)
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes
AArch64FastISel to cease using the old getAlignment() API of MemoryIntrinsic in favour of getting
source & dest specific alignments through the new API.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, r323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324773
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Francis Visoiu Mistrih [Fri, 9 Feb 2018 21:47:07 +0000 (21:47 +0000)]
[X86][MC] Fix assembling rip-relative addressing + immediate displacements
In the rare case where the input contains rip-relative addressing with
immediate displacements, *and* the instruction ends with an immediate,
we encode the instruction in the wrong way:
movl $
12345678, 0x400(%rdi) // all good, no rip-relative addr
movl %eax, 0x400(%rip) // all good, no immediate at the end of the instruction
movl $
12345678, 0x400(%rip) // fails, encodes address as 0x3fc(%rip)
Offset is a label:
movl $
12345678, foo(%rip)
we want to account for the size of the immediate (in this case,
$
12345678, 4 bytes).
Offset is an immediate:
movl $
12345678, 0x400(%rip)
we should not account for the size of the immediate, assuming the
immediate offset is what the user wanted.
Differential Revision: https://reviews.llvm.org/D43050
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324772
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Matt Davis [Fri, 9 Feb 2018 21:34:34 +0000 (21:34 +0000)]
[CodeGen] Add lifetime markers to the list of meta-instructions.
Summary:
Since the lifetime markers are metadata instructions, they should probably be treated as such by the isMetaInstruction predicate.
There was no issue that provoked this change, I just ran across it while investigating another issue.
Reviewers: aprantl, MatzeB
Reviewed By: aprantl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43111
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324771
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Sam Clegg [Fri, 9 Feb 2018 20:21:50 +0000 (20:21 +0000)]
[WebAssebmly] Report undefined symbols correctly in objdump
Peviously we were reporting undefined symbol as being defined
by the IMPORT sections.
This change reports undefined symbols in the same that other
formats do, and also removes the need to store the section
with each symbol (since it can be derived from the symbol
type).
Differential Revision: https://reviews.llvm.org/D43101
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324770
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Francis Visoiu Mistrih [Fri, 9 Feb 2018 19:46:02 +0000 (19:46 +0000)]
[CodeGen] Print predecessors as MIR comments in -debug output
Make -debug MBB headers more copy-pastable into mir files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324769
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Kevin Enderby [Fri, 9 Feb 2018 19:31:27 +0000 (19:31 +0000)]
llvm-objdump when printing the Objective-C meta data also prints the Swift ABI
from the value stored in swift_version bits in the flags field in the
objc_image_info struct. ABI version 3 thru 6 were previously added but this
code was not updated to print the Swift version.
rdar://
35624067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324767
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Evandro Menezes [Fri, 9 Feb 2018 19:26:11 +0000 (19:26 +0000)]
[AArch64] Adjust the cost model for Exynos M3
Fix the modeling of transfers between a generic register and a partial ASIMD
one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324766
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Vedant Kumar [Fri, 9 Feb 2018 19:19:55 +0000 (19:19 +0000)]
[Utils] Salvage debug info from dead 'or' instructions
Extend salvageDebugInfo to preserve the debug info from a dead 'or'
with a constant.
Patch by Ismail Badawi!
Differential Revision: https://reviews.llvm.org/D43129
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324764
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Krzysztof Parzyszek [Fri, 9 Feb 2018 19:10:46 +0000 (19:10 +0000)]
[Hexagon] Add code to select QTRUE and QFALSE
Fixes http://llvm.org/PR36320.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324763
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Matt Arsenault [Fri, 9 Feb 2018 18:41:42 +0000 (18:41 +0000)]
Declare PostDominatorTree as a class
Before it was declared at a struct, which differs from
DominatorTree. Make it a class so both can be declared
the same way without hitting the warning about mismatched
struct vs. class declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324760
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Artem Belevich [Fri, 9 Feb 2018 18:37:55 +0000 (18:37 +0000)]
[tablegen] Fixed few !foreach evaluation issues.
* !foreach on lists didn't evaluate operands of the RHS operator.
This made nested operators silently fail.
* A typo in the code could result in a wrong value substituted
for an operation which produced a false '!foreach requires an operator' error.
* Keep recursion over the DAG within ForeachHelper. This simplifies
things a bit as we no longer need to pass the Type around in order
to prevent recursion.
Differential Revision: https://reviews.llvm.org/D43083
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324758
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Steven Wu [Fri, 9 Feb 2018 18:34:08 +0000 (18:34 +0000)]
[ThinLTO] Teach ThinLTO about auto hide symbols
Summary:
For symbols that has linkonce_odr linkage and unnamed_addr, it can be
auto hide by linker to avoid weak external symbols. Teach ThinLTO to
perform auto hide so it can safely promote linkonce_odr to weak symbols
without breaking this nice property.
Reviewers: tejohnson, mehdi_amini
Reviewed By: tejohnson
Subscribers: inglorion, eraman, rnk, pcc, llvm-commits
Differential Revision: https://reviews.llvm.org/D43130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324757
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Sanjay Patel [Fri, 9 Feb 2018 17:46:38 +0000 (17:46 +0000)]
[x86] remove duplicate undef tests; NFC
These are incomplete and were made redundant with the consolidation in:
https://reviews.llvm.org/rL324678
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324754
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Simon Pilgrim [Fri, 9 Feb 2018 17:45:45 +0000 (17:45 +0000)]
[InstCombine] Add vector xor tests
This doesn't cover everything in InstCombiner.visitXor yet, but increases coverage for a lot of tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324753
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