OSDN Git Service
whitequark [Fri, 28 Sep 2018 16:48:47 +0000 (16:48 +0000)]
[bindings/go] Add Go bindings for inline assembly
Reviewers: harlanhaskins, whitequark, pcc
Reviewed By: pcc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343339
91177308-0d34-0410-b5e6-
96231b3b80d8
whitequark [Fri, 28 Sep 2018 16:45:18 +0000 (16:45 +0000)]
Revert "[LLVM-C] Add bindings for addCoroutinePassesToExtensionPoints"
This reverts commit
c4baf7c2f06ff5459c4f5998ce980346e72bff97.
Broke the bots, and should really be in Transforms/Coroutines
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343337
91177308-0d34-0410-b5e6-
96231b3b80d8
whitequark [Fri, 28 Sep 2018 16:38:11 +0000 (16:38 +0000)]
[LLVM-C] Add bindings for addCoroutinePassesToExtensionPoints
Summary: This patch adds bindings to C and Go for addCoroutinePassesToExtensionPoints, which is used to add coroutine passes to the correct locations in PassManagerBuilder.
Reviewers: whitequark, deadalnix
Reviewed By: whitequark
Subscribers: mehdi_amini, modocache, llvm-commits
Differential Revision: https://reviews.llvm.org/D51642
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343336
91177308-0d34-0410-b5e6-
96231b3b80d8
Robert Widmann [Fri, 28 Sep 2018 16:02:26 +0000 (16:02 +0000)]
[LLVM-C] Fix broken build bots
Summary: Fix broken bots caused by the merge of D51522.
Reviewers: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52657
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343334
91177308-0d34-0410-b5e6-
96231b3b80d8
Greg Bedwell [Fri, 28 Sep 2018 15:39:18 +0000 (15:39 +0000)]
[utils] Cope with the binary having a .exe extension in update_mca_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343333
91177308-0d34-0410-b5e6-
96231b3b80d8
Greg Bedwell [Fri, 28 Sep 2018 15:39:09 +0000 (15:39 +0000)]
[utils] Stricter checking from update_mca_test_checks.py
If any prefixes have been specified on the RUN lines that do not end up
ever actually getting printed, raise an Error. This is either an
indication that the run lines just need cleaning up, or that something
is more fundamentally wrong with the test.
Also raise an Error if there are any blocks which cannot be checked
because they are not uniquely covered by a prefix.
Fixed up a couple of tests where the extra checking flagged up issues.
Differential Revision: https://reviews.llvm.org/D48276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343332
91177308-0d34-0410-b5e6-
96231b3b80d8
Greg Bedwell [Fri, 28 Sep 2018 15:38:56 +0000 (15:38 +0000)]
[utils] Allow better identification of matching blocks in update_mca_test_checks.py
Insert empty blocks to cause the positions of matching blocks to match
across lists where possible so that later stages of the algorithm can
actually identify them as being identical.
Regenerated all tests with this change.
Differential Revision: https://reviews.llvm.org/D52560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343331
91177308-0d34-0410-b5e6-
96231b3b80d8
Robert Widmann [Fri, 28 Sep 2018 15:35:18 +0000 (15:35 +0000)]
[LLVM-C] Add more debug information accessors to GlobalObject and Instruction
Summary: Adds missing debug information accessors to GlobalObject. This puts the finishing touches on cloning debug info in the echo tests.
Reviewers: whitequark, deadalnix
Reviewed By: whitequark
Subscribers: aprantl, JDevlieghere, llvm-commits, harlanhaskins
Differential Revision: https://reviews.llvm.org/D51522
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343330
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 28 Sep 2018 15:24:41 +0000 (15:24 +0000)]
[InstCombine] don't propagate wider shufflevector arguments to predecessors
InstCombine would propagate shufflevector insts that had wider output vectors onto
predecessors, which would sometimes push undef's onto the divisor of a div/rem and
result in bad codegen.
I've fixed this by just banning propagating shufflevector back if the result of
the shufflevector is wider than the input vectors.
Patch by: @sheredom (Neil Henning)
Differential Revision: https://reviews.llvm.org/D52548
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343329
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 28 Sep 2018 15:20:06 +0000 (15:20 +0000)]
[InstCombine] adjust shuffle undef propagation tests; NFC
These are the updated baseline tests for D52548 -
I'm putting the tests next to the tests where the transform
functions as expected, so we can see the intended/unintended
consequences.
Patch by: @sheredom (Neil Henning)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343328
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Fri, 28 Sep 2018 15:13:41 +0000 (15:13 +0000)]
[ORC] Remove some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343327
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Fri, 28 Sep 2018 15:09:14 +0000 (15:09 +0000)]
[ORC] Fix the unit tests that were broken by r343323.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343326
91177308-0d34-0410-b5e6-
96231b3b80d8
Aditya Nandakumar [Fri, 28 Sep 2018 15:08:49 +0000 (15:08 +0000)]
[GISel]: Remove an incorrect assert in CallLowering
https://reviews.llvm.org/D51147
Asserting if any extend of vectors should be up to the target's
legalizer/target specific code not in CallLowering.
reviewed by : dsanders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343325
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Fri, 28 Sep 2018 15:03:11 +0000 (15:03 +0000)]
[ORC] Improve debugging output for ORC.
(1) Print debugging output under a session lock to avoid garbled messages when
compiling on multiple threads.
(2) Name MaterializationUnits, add an ostream operator for them, and so they can
be easily referenced in debugging output, and have that ostream operator
optionally print code/data/hidden symbols provided by that materialization unit
based on command line options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343323
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 28 Sep 2018 14:20:42 +0000 (14:20 +0000)]
[X86][Btver2] PSUBS/PSUBUS instructions are zero-idioms
Noticed during llvm-exegesis tests, the PSUBS/PSUBUS instructions have the same zero-idiom behaviour to PSUB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343321
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 28 Sep 2018 13:53:11 +0000 (13:53 +0000)]
[X86][Btver2] Add zero-idiom tests for PSUBS/PSUBUS instructions
Noticed during llvm-exegesis tests, the PSUBS/PSUBUS instructions have the same zero-idiom behaviour to PSUB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343319
91177308-0d34-0410-b5e6-
96231b3b80d8
Luke Cheeseman [Fri, 28 Sep 2018 13:37:27 +0000 (13:37 +0000)]
Reapply changes reverted by r343235
- Add fix so that all code paths that create DWARFContext
with an ObjectFile initialise the target architecture in the context
- Add an assert that the Arch is known in the Dwarf CallFrameString method
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343317
91177308-0d34-0410-b5e6-
96231b3b80d8
Sven van Haastregt [Fri, 28 Sep 2018 13:31:55 +0000 (13:31 +0000)]
Fix and modernize StringMatcher comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343316
91177308-0d34-0410-b5e6-
96231b3b80d8
Petar Jovanovic [Fri, 28 Sep 2018 13:28:47 +0000 (13:28 +0000)]
[MIPS GlobalISel] Lower i64 arguments
Lower integer arguments larger then 32 bits for MIPS32.
setMostSignificantFirst is used in order for G_UNMERGE_VALUES and
G_MERGE_VALUES to always hold registers in same order, regardless of
endianness.
Patch by Petar Avramovic.
Differential Revision: https://reviews.llvm.org/D52409
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343315
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 28 Sep 2018 13:19:22 +0000 (13:19 +0000)]
[X86][Btver2] CVTSS2I/CVTSD2I - add missing JFPU0 pipe
We issue JFPU1->JSTC then JFPU0->JFPA then -> JALU0 (integer pipe)
Match AMD Fam16h SOG + llvm-exegesis tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343314
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Fri, 28 Sep 2018 12:08:51 +0000 (12:08 +0000)]
Split invocations in CodeGen/X86/cpus.ll among multiple tests. (NFC)
On GreenDragon `CodeGen/X86/cpus.ll` is timing out on the bot with Asan
and UBSan enabled. With the same configuration on my machine, the test
passes but takes more than 3 minutes to do so. I could increase the
timeout, but I believe it makes more sense to split up the test because
it allows for more parallelism.
Differential revision: https://reviews.llvm.org/D52603
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343313
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Fri, 28 Sep 2018 10:47:24 +0000 (10:47 +0000)]
[llvm-mca] Remove redundant namespace prefixes. NFC
We are already "using" namespace llvm in all the files modified by this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343312
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 28 Sep 2018 10:26:48 +0000 (10:26 +0000)]
[X86][Btver2] Fix BSF/BSR schedule
Double throughput to account for 2 pipes + fix BSF's latency/uop counts
Match AMD Fam16h SOG + llvm-exegesis tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343311
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Fri, 28 Sep 2018 10:20:07 +0000 (10:20 +0000)]
Revert r343308: [LoopInterchange] Turn into a loop pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343310
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Fri, 28 Sep 2018 09:45:50 +0000 (09:45 +0000)]
[LoopInterchange] Turn into a loop pass.
This patch turns LoopInterchange into a loop pass. It now only
considers top-level loops and tries to move the innermost loop to the
optimal position within the loop nest. By only looking at top-level
loops, we might miss a few opportunities the function pass would get
(e.g. if we have a loop nest of 3 loops, in the function pass
we might process loops at level 1 and 2 and move the inner most loop to
level 1, and then we process loops at levels 0, 1, 2 and interchange
again, because we now have a different inner loop). But I think it would
be better to handle such cases by picking the best inner loop from the
start and avoid re-visiting the same loops again.
The biggest advantage of it being a function pass is that it interacts
nicely with the other loop passes. Without this patch, there are some
performance regressions on AArch64 with loop interchanging enabled,
where no loops were interchanged, but we missed out on some other loop
optimizations.
It also removes the SimplifyCFG run. We are just changing branches, so
the CFG should not be more complicated, besides the additional 'unique'
preheaders this pass might create.
Reviewers: chandlerc, efriedma, mcrosier, javed.absar, xbolva00
Reviewed By: xbolva00
Differential Revision: https://reviews.llvm.org/D51702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343308
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Fri, 28 Sep 2018 09:42:06 +0000 (09:42 +0000)]
[llvm-mca] Teach how to track zero registers in class RegisterFile.
This change is in preparation for a future work on improving support for
optimizable register moves. We already know if a write is from a zero-idiom, so
we can propagate that bit of information to the PRF. We use an APInt mask to
identify registers that are set to zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343307
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Smith [Fri, 28 Sep 2018 09:04:27 +0000 (09:04 +0000)]
[ARM] Remove non-existent cpu arm1176j-s and use mpcore for v6k
The ARMTargetParser.def contains an entry for arm1176j-s which is the
default for the ArmV6K architecture. This cpu does not exist, there are
only arm1176jz-s and arm1176jzf-s and they are both architecture ArmV6KZ.
The only CPUs that are actually ArmV6K are the mpcore, mpcore_nofpu and
later revisions of the arm1136 family r1px (which we don't have a table
entry for).
This patch removes the arm1176j-s and makes mpcore the default for armv6k.
Differential Revision: https://reviews.llvm.org/D52594
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343303
91177308-0d34-0410-b5e6-
96231b3b80d8
David Spickett [Fri, 28 Sep 2018 08:55:19 +0000 (08:55 +0000)]
[ARM] Allow execute only code on Cortex-m23
The NoMovt feature prevents the use of MOVW/MOVT
instructions on Cortex-M23 for performance reasons.
These instructions are required for execute only code
so NoMovt should be disabled when that option is enabled.
Differential Revision: https://reviews.llvm.org/D52551
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343302
91177308-0d34-0410-b5e6-
96231b3b80d8
David Spickett [Fri, 28 Sep 2018 08:45:28 +0000 (08:45 +0000)]
Remove extra whitespace. NFC. (test commit)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343301
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Fri, 28 Sep 2018 08:27:56 +0000 (08:27 +0000)]
[ARM][v8.5A] Add speculation barriers SSBB and PSSBB
This adds two new barrier instructions which can be used to restrict
speculative execution of load instructions.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52484
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343300
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 28 Sep 2018 08:21:39 +0000 (08:21 +0000)]
[X86][BtVer2] Fix PHMINPOS schedule resources typo
PHMINPOS can run on either JFPU pipe
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343299
91177308-0d34-0410-b5e6-
96231b3b80d8
Hiroshi Inoue [Fri, 28 Sep 2018 05:27:32 +0000 (05:27 +0000)]
[CodeGen] fix broken successor probability in MBB dump
When printing successor probabilities for a MBB, a human readable value is sometimes shown as 200.0%.
The human readable output is based on getProbabilityIterator, which returns 0xFFFFFFFF for getNumerator() and 0x80000000 for getDenominator() for unknown BranchProbability.
By using getSuccProbability as we do for the non-human readable part, we can avoid this problem.
Differential Revision: https://reviews.llvm.org/D52605
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343297
91177308-0d34-0410-b5e6-
96231b3b80d8
Owen Rodley [Fri, 28 Sep 2018 04:51:45 +0000 (04:51 +0000)]
Test commit. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343296
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 28 Sep 2018 03:35:37 +0000 (03:35 +0000)]
[ScalarizeMaskedMemIntrin] Use MinAlign to calculate alignment for the scalar load/stores to handle element types that are byte-sized but not powers of 2.
This pass doesn't handle non-byte sized types correctly at all, but at least we can make byte sized types work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343294
91177308-0d34-0410-b5e6-
96231b3b80d8
Aaron Smith [Fri, 28 Sep 2018 02:32:07 +0000 (02:32 +0000)]
[pdb] Simplify the code by replacing a few string conversions with calls to invokeBstrMethod()
Reviewers: aleksandr.urakov, zturner, llvm-commits
Reviewed By: zturner
Differential Revision: https://reviews.llvm.org/D52624
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343291
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Fri, 28 Sep 2018 02:30:42 +0000 (02:30 +0000)]
merge-request.sh: Add 7.0 metabug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343290
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Fri, 28 Sep 2018 01:41:33 +0000 (01:41 +0000)]
[ORC] clang-format the ThreadSafeModule code.
Evidently I forgot to do this before committing r343055.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343288
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Fri, 28 Sep 2018 01:41:33 +0000 (01:41 +0000)]
[ORC] Add a const version of ThreadSafeModule::getModule().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343287
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Fri, 28 Sep 2018 01:41:29 +0000 (01:41 +0000)]
[ORC] Lock ThreadSafeContext during module destruction in ThreadSafeModule's
move constructor.
This is basically the same fix as r343261, but applied to the move constructor:
Failure to lock the context during module destruction can lead to data races if
other threads are operating on the context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343286
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 28 Sep 2018 01:06:13 +0000 (01:06 +0000)]
[ScalarizeMaskedMemIntrin] Fix the alignment calculation for the scalar stores of a masked store expansion.
It should be the minimum of the original alignment and the scalar size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343284
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 28 Sep 2018 01:06:09 +0000 (01:06 +0000)]
[ScalarizeMaskedMemIntrin] Add test cases for masked store expansion. Increase alignment of one of the masked load test cases.
The masked store alignment is being miscalculated, but masked load is correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343283
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 27 Sep 2018 23:25:10 +0000 (23:25 +0000)]
[X86] Add the test case from PR38986.
The assembly for this test should be optimal now after changes to the ScalarizeMaskedMemIntrin patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343281
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 27 Sep 2018 22:31:42 +0000 (22:31 +0000)]
[ScalarizeMaskedMemIntrin] Ensure the mask is a vector of ConstantInts before generating the expansion without control flow.
Its possible the mask itself or one of the elements is a ConstantExpr and we shouldn't optimize in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343278
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 27 Sep 2018 22:31:40 +0000 (22:31 +0000)]
[ScalarizeMaskedMemIntrin] Use cast instead of dyn_cast checked by an assert. Consistently make use of the element type variable we already have. NFCI
cast will take care of asserting internally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343277
91177308-0d34-0410-b5e6-
96231b3b80d8
Derek Schuff [Thu, 27 Sep 2018 22:20:33 +0000 (22:20 +0000)]
WebAssembly: Rename GetSignature to GetLibcallSignature [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343275
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 27 Sep 2018 21:28:59 +0000 (21:28 +0000)]
[ScalarizeMaskedMemIntrin] When expanding masked gathers, start with the passthru vector and insert the new load results into it.
Previously we started with undef and did a final merge with the passthru at the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343273
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 27 Sep 2018 21:28:55 +0000 (21:28 +0000)]
[ScalarizeMaskedMemIntrin] Add some IR only test cases for masked gather expansion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343272
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 27 Sep 2018 21:28:52 +0000 (21:28 +0000)]
[ScalarizeMaskedMemIntrin] When expanding masked loads, start with the passthru value and insert each conditional load result over their element.
Previously we started with undef and did one final merge at the end with a select.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343271
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 27 Sep 2018 21:28:46 +0000 (21:28 +0000)]
[ScalarizeMaskedMemIntrin] Handle the case where the mask is an all zero vector.
This shouldn't really happen in practice I hope, but we tried to handle other constant cases. We missed this one because we checked for ConstantVector without realizing that zero becomes ConstantAggregateZero instead.
So instead just check for Constant and use getAggregateElement which will do the dirty work for us.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343270
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 27 Sep 2018 21:28:43 +0000 (21:28 +0000)]
[ScalarizeMaskedMemIntrin] Add dedicated IR only tests for masked load expansion so I can begin making modifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343269
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 27 Sep 2018 21:28:41 +0000 (21:28 +0000)]
[ScalarizeMaskedMemIntrin] Remove some temporary variables that are only used by a single if condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343268
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 27 Sep 2018 21:28:39 +0000 (21:28 +0000)]
[ScalarizeMaskedMemIntrin] Cleanup comments. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343267
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 27 Sep 2018 21:13:07 +0000 (21:13 +0000)]
[ORC] Add definition for IRLayer::setCloneToNewContextOnEmit, use it to set the
flag to true in LLJIT when running in multithreaded mode.
The IRLayer::setCloneToNewContextOnEmit method sets a flag within the IRLayer
that causes modules added to that layer to be moved to a new context (by
serializing to/from a memory buffer) when they are emitted. This allows modules
that were all loaded on the same context to be compiled in parallel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343266
91177308-0d34-0410-b5e6-
96231b3b80d8
Konstantin Zhuravlyov [Thu, 27 Sep 2018 20:49:00 +0000 (20:49 +0000)]
AMDGPU: Split HasExt into HasExtDPP/SDWA/SDWA9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343264
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 27 Sep 2018 20:36:10 +0000 (20:36 +0000)]
[ORC] Make LocalIndirectStubsManager's operations thread-safe.
Locks stub management operations and switches to atomic update for stub
pointers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343262
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 27 Sep 2018 20:36:08 +0000 (20:36 +0000)]
[ORC] Lock ThreadSafeContext during Module destructing in ThreadSafeModule.
Failure to lock the context can lead to data races if other threads are
operating on other ThreadSafeModules that share the same context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343261
91177308-0d34-0410-b5e6-
96231b3b80d8
Konstantin Zhuravlyov [Thu, 27 Sep 2018 19:46:41 +0000 (19:46 +0000)]
AMDGPU: Split VOP2Inst into VOP2Inst_e32/e64/sdwa
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343259
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 27 Sep 2018 19:27:20 +0000 (19:27 +0000)]
[ORC] Coalesce all of ORC's symbol renaming / linkage-promotion utilities into
one SymbolLinkagePromoter utility.
SymbolLinkagePromoter renames anonymous and private symbols, and bumps all
linkages to at least global/hidden-visibility. Modules whose symbols have been
promoted by this utility can be decomposed into sub-modules without introducing
link errors. This is used by the CompileOnDemandLayer to extract single-function
modules for lazy compilation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343257
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 27 Sep 2018 19:27:20 +0000 (19:27 +0000)]
[ORC] LastKey needs to be protected to prevent data races.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343256
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 27 Sep 2018 19:27:19 +0000 (19:27 +0000)]
[lli] Fix ArgV setup bug when running in -jit-kind=orc-lazy mode.
ArgV[ArgC] should be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343255
91177308-0d34-0410-b5e6-
96231b3b80d8
Konstantin Zhuravlyov [Thu, 27 Sep 2018 19:24:05 +0000 (19:24 +0000)]
AMDGPU/NFC: Simplify VOP_MAC_F16/F32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343254
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Thu, 27 Sep 2018 18:55:20 +0000 (18:55 +0000)]
[AMDGPU] Fold copy (copy vgpr)
This allows to reduce a number of used VGPRs in some cases.
Differential Revision: https://reviews.llvm.org/D52577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343249
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 27 Sep 2018 18:01:48 +0000 (18:01 +0000)]
[ScalarizeMaskedMemIntrin] Don't emit 'icmp eq i1 %x, 1' to check mask values. That's just %x so use that directly.
Had we emitted this IR earlier, InstCombine would have removed icmp so I'm going to assume using the i1 directly would be considered canonical.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343244
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 27 Sep 2018 17:29:13 +0000 (17:29 +0000)]
[X86] Remove BT/BTC/BTR/BTS rr/ri overrides
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343241
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 27 Sep 2018 17:13:57 +0000 (17:13 +0000)]
[X86][Btver2] (V)MPSADBW instructions take 3uops not 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343238
91177308-0d34-0410-b5e6-
96231b3b80d8
Luke Cheeseman [Thu, 27 Sep 2018 16:47:30 +0000 (16:47 +0000)]
Revert r343192 as an ubsan build is currently failing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343235
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 27 Sep 2018 16:39:52 +0000 (16:39 +0000)]
[X86][Btver2] BTC/BTR/BTS instructions take 2uops not 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343234
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 27 Sep 2018 16:24:42 +0000 (16:24 +0000)]
[X86] Split BT and BTC/BTR/BTS scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343233
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 27 Sep 2018 16:21:35 +0000 (16:21 +0000)]
[Sparc] EXPENSIVE_CHECKS now passes all machine verifier errors (PR27461)
Now that D51487 has landed, the last machine verifier tests that failed EXPENSIVE_CHECKS builds have now been fixed/removed, so we can remove @MatzeB 's isMachineVerifierClean() hack for sparc targets.
Differential Revision: https://reviews.llvm.org/D52612
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343232
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Thu, 27 Sep 2018 16:19:04 +0000 (16:19 +0000)]
[AArch64] Refactor immediate details out of add/sub tblgen class (NFCI)
Bits [23-22] are used in Add and Sub to specify the shift. The value of the
shift field must be 0x; values of 1x are unallocated. MTE adds some instructions
that use such encodings, and this patch refactors the Add/Sub class so that
another class could derive from this one to implement other encodings and other
formats of bitfields.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343231
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Thu, 27 Sep 2018 16:09:05 +0000 (16:09 +0000)]
[AArch64][v8.5A] Add speculation barriers SSBB and PSSBB
This adds two new barrier instructions which can be used to restrict
speculative execution of load instructions.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52483
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343229
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 27 Sep 2018 15:59:24 +0000 (15:59 +0000)]
[InstCombine] Without infinites, fold (C / X) < 0.0 --> (X < 0)
When C is not zero and infinites are not allowed (C / X) > 0 is a sign
test. Depending on the sign of C, the predicate must be swapped.
E.g.:
foo(double X) {
if ((-2.0 / X) <= 0) ...
}
=>
foo(double X) {
if (X >= 0) ...
}
Patch by: @marels (Martin Elshuber)
Differential Revision: https://reviews.llvm.org/D51942
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343228
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 27 Sep 2018 14:57:57 +0000 (14:57 +0000)]
[X86][Btver2] BLSI/BLSMSK/BLSR instructions take 2uops not 1 (same as TZCNT)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343227
91177308-0d34-0410-b5e6-
96231b3b80d8
Teresa Johnson [Thu, 27 Sep 2018 14:55:32 +0000 (14:55 +0000)]
[WPD] Fix incorrect devirtualization after indirect call promotion
Summary:
Add a dominance check to ensure that the possible devirtualizable
call is actually dominated by the type test/checked load intrinsic being
analyzed. With PGO, after indirect call promotion is performed during
the compile step, followed by inlining, we may have a type test in the
promoted and inlined sequence that allows an indirect call in that
sequence to be devirtualized. That indirect call (inserted by inlining
after promotion) will share the same vtable pointer as the fallback
indirect call that cannot be devirtualized.
Before this patch the code was incorrectly devirtualizing the fallback
indirect call.
See the new test and the example described there for more details.
Reviewers: pcc, vitalybuka
Subscribers: mehdi_amini, Prazek, eraman, steven_wu, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D52514
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343226
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Thu, 27 Sep 2018 14:54:33 +0000 (14:54 +0000)]
[AArch64][v8.5A] Add Branch Target Identification instructions
This adds new instructions used by the Branch Target Identification
feature. When this is enabled, these are the only instructions which can
be targeted by indirect branch instructions.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52485
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343225
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 27 Sep 2018 14:24:29 +0000 (14:24 +0000)]
[InstCombine] add tests for FP sign-bit cmp optimization with fdiv; NFC
These are baseline tests for D51942.
Patch by: @marels (Martin Elshuber)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343222
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Thu, 27 Sep 2018 14:05:46 +0000 (14:05 +0000)]
[AArch64][v8.5A] Add speculation restriction system registers
This adds some new system registers which can be used to restrict
certain types of speculative execution.
Patch by Pablo Barrio and David Spickett!
Differential revision: https://reviews.llvm.org/D52482
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343218
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Thu, 27 Sep 2018 14:01:40 +0000 (14:01 +0000)]
[AArch64][v8.5A] Add Armv8.5-A random number instructions
This adds two new system registers, used to generate random numbers.
This is an optional extension to v8.5-A, and will be controlled by the
"+rng" modifier of the -march= and -mcpu= options.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343217
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Thu, 27 Sep 2018 13:53:35 +0000 (13:53 +0000)]
[AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instruction
This adds a new variant of the DC system instruction for persistent
memory.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343216
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 27 Sep 2018 13:49:52 +0000 (13:49 +0000)]
The llvm-exegesis output file is a html file not a txt file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343215
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Thu, 27 Sep 2018 13:47:40 +0000 (13:47 +0000)]
[AArch64][v8.5A] Add prediction invalidation instructions to AArch64
This adds new system instructions which act as barriers to speculative
execution based on earlier execution within a particular execution
context.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52479
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343214
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Thu, 27 Sep 2018 13:41:14 +0000 (13:41 +0000)]
[ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction sets
This is a new barrier which limits speculative execution of the
instructions following it.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52477
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343213
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Thu, 27 Sep 2018 13:39:06 +0000 (13:39 +0000)]
[AArch64][v8.5A] Add speculation barrier to AArch64 instruction set
This is a new barrier which limits speculative execution of the
instructions following it.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52476
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343211
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Cederman [Thu, 27 Sep 2018 13:32:54 +0000 (13:32 +0000)]
[Sparc] Remove the support for builtin setjmp/longjmp
Summary: It is currently broken and for Sparc there is not much benefit
in using a builtin version compared to a library version. Both versions
needs to store the same four values in setjmp and flush the register
windows in longjmp. If the need for a builtin setjmp/longjmp arises there
is an improved implementation available at https://reviews.llvm.org/D50969.
Reviewers: jyknight, joerg, venkatra
Subscribers: fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D51487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343210
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Thu, 27 Sep 2018 13:32:06 +0000 (13:32 +0000)]
[AArch64][v8.5A] Add FRINT[32,64][Z,X] instructions
These are some new variants of the "Floating-point Round to Integral"
family of instructions, which round to the nearest floating-point value
which fits in a 32- or 64-bit integer.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52475
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343209
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Thu, 27 Sep 2018 13:26:37 +0000 (13:26 +0000)]
[llvm-exegesis] Fix PR39096.
Summary: The key is now the resource name, not the resource id.
Reviewers: gchatelet
Subscribers: tschuett, RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D52607
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343208
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Cederman [Thu, 27 Sep 2018 12:34:53 +0000 (12:34 +0000)]
[Sparc] Add unimp alias
Summary: Use 0 as the default immediate for the UNIMP instruction.
This matches the behavior in gas.
Reviewers: jyknight, venkatra
Subscribers: fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D51526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343203
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Cederman [Thu, 27 Sep 2018 12:34:48 +0000 (12:34 +0000)]
[Sparc] Add support for the partial write PSR instruction
Summary:
Partial write %PSR (WRPSR) is a SPARC V8e option that allows WRPSR
instructions to only affect the %PSR.ET field. It is supported by
the GR740 and GR716.
Reviewers: jyknight, venkatra
Subscribers: fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D48644
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343202
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 27 Sep 2018 12:28:47 +0000 (12:28 +0000)]
[X86][Btver2] TZCNT instructions take 2uops not 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343200
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Thu, 27 Sep 2018 11:49:47 +0000 (11:49 +0000)]
[PowerPC] [NFC] Refactor code for printing register operands
We have an unfortunate situation in our back end where we have to keep pairs of
functions synchronized. Needless to say that this is not an ideal situation as
it is very difficult to enforce. Even without bugs, it's annoying to have to do
the same thing in two places.
This patch just refactors the code so that the two pairs of those functions that
pertain to printing register operands are unified:
- stripRegisterPrefix() - this just removes the letter prefixes from registers
for the InstrPrinter and AsmPrinter. This patch provides this as a static
member of PPCRegisterInfo
- Handling of PPCII::UseVSXReg - there are 3 places where we do something
special for instructions with that flag set. Each of those places does its
own checking of this flag and implements code customization. Any changes to
how we print/encode VSX/VMX registers require modifying all 3 places. This
patch unifies this into a static function in PPCInstrInfo that returns the
register number adjusted as needed.
Differential revision: https://reviews.llvm.org/D52467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343195
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 27 Sep 2018 11:40:26 +0000 (11:40 +0000)]
[X86][Btver2] Add uops counter for exegesis reports
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343194
91177308-0d34-0410-b5e6-
96231b3b80d8
Luke Cheeseman [Thu, 27 Sep 2018 10:39:20 +0000 (10:39 +0000)]
Reapply changes reverted in r343114, lldb patch to follow shortly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343192
91177308-0d34-0410-b5e6-
96231b3b80d8
Nicola Zaghen [Thu, 27 Sep 2018 10:08:38 +0000 (10:08 +0000)]
[InstCombine] Add new tests in preparation for a combine of icmp (mul nsw/nuw X, C2), C
Proof for the future optimisations are here:
- eq/neq: https://rise4fun.com/Alive/9PBA
- sgt/ugt: https://rise4fun.com/Alive/58yr
- slt/ult: https://rise4fun.com/Alive/VCQ
Differential Revision: https://reviews.llvm.org/D51625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343190
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Thu, 27 Sep 2018 09:59:27 +0000 (09:59 +0000)]
Revert r342942 "[MachineCopyPropagation] Reimplement CopyTracker in terms of register units"
It seems to have broken several targets, see comments on the llvm-commits thread.
> Change the copy tracker to keep a single map of register units instead
> of 3 maps of registers. This gives a very significant compile time
> performance improvement to the pass. I measured a 30-40% decrease in
> time spent in MCP on x86 and AArch64 and much more significant
> improvements on out of tree targets with more registers.
>
> Differential Revision: https://reviews.llvm.org/D52374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343189
91177308-0d34-0410-b5e6-
96231b3b80d8
Guillaume Chatelet [Thu, 27 Sep 2018 09:23:04 +0000 (09:23 +0000)]
[llvm-exegesis][NFC] moving code around.
Summary: Renaming InstructionBuilder into InstructionTemplate and moving code generation tools from MCInstrDescView to CodeTemplate.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343188
91177308-0d34-0410-b5e6-
96231b3b80d8
Oliver Stannard [Thu, 27 Sep 2018 09:11:27 +0000 (09:11 +0000)]
[AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlag
These new instructions manipluate the NZCV bits, to convert between the
regular Arm floating-point comare format and an alternative format.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52473
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343187
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Atanasyan [Thu, 27 Sep 2018 08:51:18 +0000 (08:51 +0000)]
[mips] Add support MIPS r6 Debian triples
Debian uses different triples for MIPS r6 and paths. Here we use SubArch
to determine whether it is r6, if we found `r6' in CPU section of triple.
These new triples include:
mipsisa32r6-linux-gnu
mipsisa32r6el-linux-gnu
mipsisa64r6-linux-gnuabi64
mipsisa64r6el-linux-gnuabi64
mipsisa64r6-linux-gnuabin32
mipsisa64r6el-linux-gnuabin32
Patch by YunQiang Su.
Differential revision: https://reviews.llvm.org/D50857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343185
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Thu, 27 Sep 2018 06:10:15 +0000 (06:10 +0000)]
[llvm-exegesis] Remove unused headers and fix naming issues
Reviewers: courbet
Reviewed By: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343177
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Thu, 27 Sep 2018 04:19:32 +0000 (04:19 +0000)]
[ORC] Use ExecutionSession's pre-constructed main JITDylib in LLJIT.
As of r342086 ExecutionSession automatically creates a 'main' JITDylib, so
there is no need for LLJIT to create its own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343167
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Thu, 27 Sep 2018 03:48:04 +0000 (03:48 +0000)]
[docs] Remove reference to makellvm which was removed in rL329041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343165
91177308-0d34-0410-b5e6-
96231b3b80d8