OSDN Git Service
Simon Pilgrim [Tue, 5 Dec 2017 13:49:44 +0000 (13:49 +0000)]
[X86][AVX512] Tag scalar CVT and CMP instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319765
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Dean Michael Berris [Tue, 5 Dec 2017 12:43:12 +0000 (12:43 +0000)]
[XRay][docs] Document xray_mode and log registration API.
This marks certain flags in XRay as deprecated (in particular,
`xray_naive_log=` and `xray_fdr_log=`), and recommends the use of the
`xray_mode=` flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319763
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Igor Laevsky [Tue, 5 Dec 2017 12:18:15 +0000 (12:18 +0000)]
[InstCombine] Don't crash on out of bounds shifts
Differential Revision: https://reviews.llvm.org/D40649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319761
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Simon Pilgrim [Tue, 5 Dec 2017 12:14:36 +0000 (12:14 +0000)]
[X86][AVX512] Tag VPCMP/VPCMPU instruction scheduler classes
Move hardcoded itinerary out to the instruction declarations. Not sure that IIC_SSE_ALU_F32P is the best schedule for integer comparisons, but I'm not going to change it right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319760
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Simon Pilgrim [Tue, 5 Dec 2017 12:02:22 +0000 (12:02 +0000)]
[X86][AVX512] Cleanup VPCMP scheduler classes
Move hardcoded itinerary out to the instruction declarations. Not sure that IIC_SSE_ALU_F32P is the best schedule for integer comparisons, but I'm not going to change it right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319758
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Simon Pilgrim [Tue, 5 Dec 2017 11:46:57 +0000 (11:46 +0000)]
[X86][AVX512] Tag VFIXUPIMM instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319757
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Jonas Paulsson [Tue, 5 Dec 2017 11:24:39 +0000 (11:24 +0000)]
[SystemZ] set 'guessInstructionProperties = 0' and set flags as needed.
This has proven a healthy exercise, as many cases of incorrect instruction
flags were corrected in the process. As part of this, IntrWriteMem was added
to several SystemZ instrinsics.
Furthermore, a bug was exposed in TwoAddress with this change (as incorrect
hasSideEffects flags were removed and instructions could now be sunk), and
the test case for that bugfix (r319646) is included here as
test/CodeGen/SystemZ/twoaddr-sink.ll.
One temporary test regression (one extra copy) which will hopefully go away
in upcoming patches for similar cases:
test/CodeGen/SystemZ/vec-trunc-to-i1.ll
Review: Ulrich Weigand.
https://reviews.llvm.org/D40437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319756
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Jonas Paulsson [Tue, 5 Dec 2017 10:52:24 +0000 (10:52 +0000)]
[Regalloc] Generate and store multiple regalloc hints.
MachineRegisterInfo used to allow just one regalloc hint per virtual
register. This patch extends this to a vector of regalloc hints, which is
filled in by common code with sorted copy hints. Such hints will make for
more ID copies that can be removed.
NB! This improvement is currently (and hopefully temporarily) *disabled* by
default, except for SystemZ. The only reason for this is the big impact this
has on tests, which has unfortunately proven unmanageable. It was a long
while since all the tests were updated and just waiting for review (which
didn't happen), but now targets have to enable this themselves
instead. Several targets could get a head-start by downloading the tests
updates from the Phabricator review. Thanks to those who helped, and sorry
you now have to do this step yourselves.
This should be an improvement generally for any target!
The target may still create its own hint, in which case this has highest
priority and is stored first in the vector. If it has target-type, it will
not be recomputed, as per the previous behaviour.
The temporary hook enableMultipleCopyHints() will be removed as soon as all
targets return true.
Review: Quentin Colombet, Ulrich Weigand.
https://reviews.llvm.org/D38128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319754
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George Rimar [Tue, 5 Dec 2017 10:35:11 +0000 (10:35 +0000)]
Fix build bot after r319750 "[Support/TarWriter] - Don't allow TarWriter to add the same file more than once."
Error was:
error: comparison of integers of different signs: 'const unsigned long' and 'const int' [-Werror,-Wsign-compare]
http://lab.llvm.org:8011/builders/ubuntu-gcc7.1-werror/builds/3469/steps/build-unified-tree/logs/stdio
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/7118/steps/build-stage2-compiler/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319752
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Pavel Labath [Tue, 5 Dec 2017 10:24:15 +0000 (10:24 +0000)]
Re-commit "[cmake] Enable zlib support on windows"
This recommits r319533 which was broken llvm-config --system-libs
output. The reason was that I used find_libraries for searching for the
z library. This returns absolute paths, and when these paths made it
into llvm-config, it made it produce nonsensical flags. To fix this, I
hand-roll a search for the library in the same way that we search for
the terminfo library a couple of lines below.
This is a bit less flexible than the find_library option, as it does not
allow the user to specify the path to the library at configure time
(which is important on windows, as zlib is unlikely to be found in any
of the standard places cmake searches), but I was able to guide the
build to find it with appropriate values of LIB and INCLUDE environment
variables.
Reviewers: compnerd, rnk, beanz, rafael
Subscribers: llvm-commits, mgorny
Differential Revision: https://reviews.llvm.org/D40779
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319751
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George Rimar [Tue, 5 Dec 2017 10:09:59 +0000 (10:09 +0000)]
[Support/TarWriter] - Don't allow TarWriter to add the same file more than once.
This is for PR35460.
Currently when LLD adds files to TarWriter it may pass the same file
multiple times. For example it happens for clang reproduce file which specifies
archive (.a) files more than once in command line.
Patch makes TarWriter to ignore files with the same path, so it will
add only the first one to archive.
Differential revision: https://reviews.llvm.org/D40606
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319750
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Guy Blank [Tue, 5 Dec 2017 09:08:24 +0000 (09:08 +0000)]
[X86] Fix a bug in handling GRXX subclasses in Domain Reassignment pass
When trying to determine the correct Mask register class corresponding
to a GPR register class, not all register classes were handled.
This caused an assertion to be raised on some scenarios.
Differential Revision:
https://reviews.llvm.org/D40290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319745
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Craig Topper [Tue, 5 Dec 2017 08:15:03 +0000 (08:15 +0000)]
[SelectionDAG] Use WidenTargetBoolean in WidenVecRes_MLOAD and WidenVecOp_MSTORE instead of implementing it manually and incorrectly.
The CONCAT_VECTORS operand get its type from getSetCCResultType, but if the mask type and the setcc have different scalar sizes this creates an illegal CONCAT_VECTORS operation. The concat type should be 2x the mask type, and then an extend should be added if needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319744
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Michael Trent [Tue, 5 Dec 2017 07:50:00 +0000 (07:50 +0000)]
Test commit, as per the LLVM Developer Policy.
Commit message, as per the same policy. I added a blank space to the end
of the file. Excelsior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319743
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Craig Topper [Tue, 5 Dec 2017 06:37:21 +0000 (06:37 +0000)]
[X86] Use vector widening to support sign extend from i1 when the dest type is not 512-bits and vlx is not enabled.
Previously we used a wider element type and truncated. But its more efficient to keep the element type and drop unused elements.
If BWI isn't supported and we have a i16 or i8 type, we'll extend it to be i32 and still use a truncate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319740
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Daniel Sanders [Tue, 5 Dec 2017 05:52:07 +0000 (05:52 +0000)]
Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.
Some concerns were raised with the direction. Revert while we discuss it and look into an alternative
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319739
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Kuba Mracek [Tue, 5 Dec 2017 05:22:02 +0000 (05:22 +0000)]
Disable detect_leaks in the ASanified build of LLVM when using Apple LLVM. The released Apple LLVM versions don't support LSan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319738
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Craig Topper [Tue, 5 Dec 2017 04:47:12 +0000 (04:47 +0000)]
[X86] Fix a crash if avx512bw and xop are both enabled when the IR contrains a v32i8 bitreverse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319737
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Matt Arsenault [Tue, 5 Dec 2017 03:15:44 +0000 (03:15 +0000)]
AMDGPU: Fix missing subtarget feature initializer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319733
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Matt Arsenault [Tue, 5 Dec 2017 03:09:23 +0000 (03:09 +0000)]
AMDGPU: Fix crash when scheduling DBG_VALUE
This calls handleMove with a DBG_VALUE instruction,
which isn't tracked by LiveIntervals. I'm not sure
this is the correct place to fix this. The generic
scheduler seems to have more deliberate region
selection that skips dbg_value.
The test is also really hard to reduce. I haven't been able
to figure out what exactly causes this particular case to
try moving the dbg_value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319732
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Craig Topper [Tue, 5 Dec 2017 01:45:46 +0000 (01:45 +0000)]
[X86] Use vector widening to support zero extend from i1 when the dest type is not 512-bits and vlx is not enabled.
Previously we used a wider element type and truncated. But its more efficient to keep the element type and drop unused elements.
If BWI isn't supported and we have a i16 or i8 type, we'll extend it to be i32 and still use a truncate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319728
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Craig Topper [Tue, 5 Dec 2017 01:28:06 +0000 (01:28 +0000)]
[X86] Don't use kunpck for vXi1 concat_vectors if the upper bits are undef.
This can be efficiently selected by a COPY_TO_REGCLASS without the need for an extra instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319726
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Craig Topper [Tue, 5 Dec 2017 01:28:04 +0000 (01:28 +0000)]
[X86] Use getZeroVector and remove an unnecessary creation of an APInt before calling getConstant. NFCI
The getConstant function can take care of creating the APInt internally.
getZeroVector will take care of using the correct type for the build vector to avoid re-lowering.
The test change here is because execution domain constraints apparently pass through undef inputs of a zeroing xor. So the different ordering of register allocation here caused the dependency to change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319725
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Craig Topper [Tue, 5 Dec 2017 01:28:00 +0000 (01:28 +0000)]
[X86] Rearrange some of the code around AVX512 sign/zero extends. NFCI
Move the AVX512 code out of LowerAVXExtend. LowerAVXExtend has two callers but one of them pre-checks for AVX-512 so the code is only live from the other caller. So move the AVX-512 checks up to that caller for symmetry.
Move all of the i1 input type code in Lower_AVX512ZeroExend together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319724
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Shoaib Meenai [Tue, 5 Dec 2017 01:19:48 +0000 (01:19 +0000)]
[cmake] Modernize some conditionals. NFC
The "x${...}" form was a workaround for CMake versions prior to 3.1,
where the if command would interpret arguments as variables even when
quoted [1]. We can drop the workaround now that our minimum CMake
version is 3.4.
[1] https://cmake.org/cmake/help/v3.1/policy/CMP0054.html
Differential Revision: https://reviews.llvm.org/D40744
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319723
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Matthias Braun [Tue, 5 Dec 2017 01:18:15 +0000 (01:18 +0000)]
MachineFrameInfo: Cleanup some parameter naming inconsistencies; NFC
Consistently use the same parameter names as the names of the affected
fields. This avoids some unintuitive abbreviations like `isSS`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319722
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Matthias Braun [Tue, 5 Dec 2017 00:56:14 +0000 (00:56 +0000)]
TwoAddressInstructionPass: Trigger -O0 behavior on optnone
While we cannot skip the whole TwoAddressInstructionPass even for -O0
there are some parts of the pass that are currently skipped at -O0 but
not for optnone. Changing this as there is no reason to have those two
hit different code paths here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319721
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Petr Hosek [Tue, 5 Dec 2017 00:15:18 +0000 (00:15 +0000)]
[CMake] Don't use comma as an alternate separator
Using comma can break in cases when we're passing flags that already
use comma as a separator.
Fixes PR35504.
Differential Revision: https://reviews.llvm.org/D40761
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319719
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Jan Vesely [Mon, 4 Dec 2017 23:07:28 +0000 (23:07 +0000)]
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
Only used by pre-GCN targets
v2: fix predicate setting for FMA_Common
Differential Revision: https://reviews.llvm.org/D40692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319712
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Jan Vesely [Mon, 4 Dec 2017 22:57:29 +0000 (22:57 +0000)]
AMDGPU: Disable fp64 support on pre GCN asics
It's not implemented.
Passing +fp64-fp16-denormal feature enables fp64 even on asics that don't support it
v2: fix hasFP64 query
Differential Revision: https://reviews.llvm.org/D39931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319709
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Evgeniy Stepanov [Mon, 4 Dec 2017 22:50:39 +0000 (22:50 +0000)]
[msan] Add a fixme note for a minor deficiency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319708
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Hans Wennborg [Mon, 4 Dec 2017 22:21:15 +0000 (22:21 +0000)]
Revert r319490 "XOR the frame pointer with the stack cookie when protecting the stack"
This broke the Chromium build (crbug.com/791714). Reverting while investigating.
> Summary: This strengthens the guard and matches MSVC.
>
> Reviewers: hans, etienneb
>
> Subscribers: hiraditya, JDevlieghere, vlad.tsyrklevich, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D40622
>
> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319490
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319706
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Matt Arsenault [Mon, 4 Dec 2017 22:18:27 +0000 (22:18 +0000)]
AMDGPU: Fix creating invalid copy when adjusting dmask
Move the entire optimization to one place. Before it was possible
to adjust dmask without changing the register class of the output
instruction, since they were done in separate places. Fix all
lane sizes and move all of the optimization into the DAG folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319705
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Matt Arsenault [Mon, 4 Dec 2017 22:18:22 +0000 (22:18 +0000)]
AMDGPU: Use return value of MorphNodeTo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319704
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Daniel Sanders [Mon, 4 Dec 2017 21:40:57 +0000 (21:40 +0000)]
Allow similar TargetOpcodes to use inheritance to factor out commonality. NFC.
Summary:
While implementing atomicrmw in https://reviews.llvm.org/D40092 I found that
inheritance is unusable for all the Generic Opcodes in GlobalISel. This is
because the whole header is included inside a 'let mayLoad = 0, mayStore = 0 ... in'
block. In TableGen, the order of precedence for field assignments is:
1. Values from classes the record inherits from.
2. Values from 'let Name=Value in { ... }'
3. Values from 'let Name=Value;'
As such the 'let mayLoad = 0, mayStore = 0, ... in' surrounding the
'include "GenericOpcodes.td"' was overriding any values provided via inheritance.
We hadn't noticed this before because we were only using 'let Name=Value;' to
specialize opcodes.
Fix this by moving the default values to the lowest precedence. This is
accomplished by moving the values to a common base class
(StandardPseudoInstruction for most TargetOpcodes, and GenericOpcode for
GlobalISel specific TargetOpcodes)
Reviewers: qcolombet
Reviewed By: qcolombet
Subscribers: llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D40096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319701
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Paul Robinson [Mon, 4 Dec 2017 21:27:46 +0000 (21:27 +0000)]
Re-submit r289925 (Update .debug_line section version to match DWARF version)
Set the .debug_line version to match the requested DWARF version,
except with a maximum of v4 because we don't support v5 yet.
Previously Chromium had issues with this patch; see PR31407. Chromium
tool issues have been addressed, so hopefully this will go through
this time.
Patch by Katya Romanova!
Differential Revision: https://reviews.llvm.org/D38002
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319699
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Daniel Sanders [Mon, 4 Dec 2017 21:14:34 +0000 (21:14 +0000)]
[globalisel][tablegen] Tests for r319691
I forgot to 'svn add' the test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319698
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Hans Wennborg [Mon, 4 Dec 2017 20:48:50 +0000 (20:48 +0000)]
DAG: Follow-up to r319692 check the truncates inputs have the same type
MatchRotate assumes the types of the types of LHS and RHS are equal,
which is always the case then they come from an OR node, but here
we're getting them from two different TRUNC nodes, so we have to check
the types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319695
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Hans Wennborg [Mon, 4 Dec 2017 20:39:57 +0000 (20:39 +0000)]
DAG: Match truncated rotation (PR35487)
If the truncation has been pushed past the or-node, look through it and
truncate afterwards.
Differential revision: https://reviews.llvm.org/D40792
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319692
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Daniel Sanders [Mon, 4 Dec 2017 20:39:32 +0000 (20:39 +0000)]
[globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64.
This patch splits atomics out of the generic G_LOAD/G_STORE and into their own
G_ATOMIC_LOAD/G_ATOMIC_STORE. This is a pragmatic decision rather than a
necessary one. Atomic load/store has little in implementation in common with
non-atomic load/store. They tend to be handled very differently throughout the
backend. It also has the nice side-effect of slightly improving the common-case
performance at ISel since there's no longer a need for an atomicity check in the
matcher table.
All targets have been updated to remove the atomic load/store check from the
G_LOAD/G_STORE path. AArch64 has also been updated to mark
G_ATOMIC_LOAD/G_ATOMIC_STORE legal.
There is one issue with this patch though which also affects the extending loads
and truncating stores. The rules only match when an appropriate G_ANYEXT is
present in the MIR. For example,
(G_ATOMIC_STORE (G_TRUNC:s16 (G_ANYEXT:s32 (G_ATOMIC_LOAD:s16 X))))
will match but:
(G_ATOMIC_STORE (G_ATOMIC_LOAD:s16 X))
will not. This shouldn't be a problem at the moment, but as we get better at
eliminating extends/truncates we'll likely start failing to match in some
cases. The current plan is to fix this in a patch that changes the
representation of extending-load/truncating-store to allow the MMO to describe
a different type to the operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319691
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Hiroshi Yamauchi [Mon, 4 Dec 2017 20:36:01 +0000 (20:36 +0000)]
Move splitIndirectCriticalEdges() to BasicBlockUtils.h.
Summary:
Move splitIndirectCriticalEdges() from CodeGenPrepare to BasicBlockUtils.h so
that it can be called from other places.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319689
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Matthias Braun [Mon, 4 Dec 2017 20:08:28 +0000 (20:08 +0000)]
Add missing triple args to tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319686
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Haicheng Wu [Mon, 4 Dec 2017 19:56:33 +0000 (19:56 +0000)]
[ConstantFold] Support vector index when factoring out GEP index into preceding dimensions
Follow-up of r316824. This patch supports the vector type for both current and
previous index when factoring out the current one into the previous one.
Differential Revision: https://reviews.llvm.org/D39556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319683
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Sanjoy Das [Mon, 4 Dec 2017 19:22:01 +0000 (19:22 +0000)]
[SCEV] Use a "Discovered" set instead of a "Visited" set; NFC
Suggested by Max Kazantsev in https://reviews.llvm.org/D39361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319679
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Sanjoy Das [Mon, 4 Dec 2017 19:22:00 +0000 (19:22 +0000)]
[SCEV] A different fix for PR33494
Summary:
I don't think rL309080 is the right fix for PR33494 -- caching ExitLimit only
hides the problem[0]. The real issue is that because of how we forget SCEV
expressions ScalarEvolution::getBackedgeTakenInfo, in the test case for PR33494
computing the backedge for any loop invalidates the trip count for every other
loop. This effectively makes the SCEV cache useless.
I've instead made the SCEV expression invalidation in
ScalarEvolution::getBackedgeTakenInfo less aggressive to fix this issue.
[0]: One way to think about this is that rL309080 essentially augmented the
backedge-taken-count cache with another equivalent exit-limit cache. The bug
went away because we were explicitly not clearing the exit-limit cache in
getBackedgeTakenInfo. But instead of doing all of that, we can just avoid
clearing the backedge-taken-count cache.
Reviewers: mkazantsev, mzolotukhin
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D39361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319678
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Sanjoy Das [Mon, 4 Dec 2017 19:21:58 +0000 (19:21 +0000)]
[BypassSlowDivision] Improve our handling of divisions by constants
(This reapplies r314253. r314253 was reverted on r314482 because of a
correctness regression on P100, but that regression was identified to be
something else.)
Summary:
Don't bail out on constant divisors for divisions that can be narrowed without
introducing control flow . This gives us a 32 bit multiply instead of an
emulated 64 bit multiply in the generated PTX assembly.
Reviewers: jlebar
Subscribers: jholewinski, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D38265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319677
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Matthias Braun [Mon, 4 Dec 2017 18:57:48 +0000 (18:57 +0000)]
MachineVerifier: undef phi arg doesn't need to be live-out from predecessor
Differential Revision: https://reviews.llvm.org/D40756
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319674
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Francis Visoiu Mistrih [Mon, 4 Dec 2017 17:18:51 +0000 (17:18 +0000)]
[CodeGen] Unify MBB reference format in both MIR and debug output
As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.
The MIR printer prints the IR name of a MBB only for block definitions.
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix
Differential Revision: https://reviews.llvm.org/D40422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319665
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Pablo Barrio [Mon, 4 Dec 2017 16:55:49 +0000 (16:55 +0000)]
Fix function pointer tail calls in armv8-M.base
Summary:
The compiler fails with the following error message:
fatal error: error in backend: ran out of registers during
register allocation
Tail call optimization for Armv8-M.base fails to meet all the required
constraints when handling calls to function pointers where the
arguments take up r0-r3. This is because the pointer to the
function to be called can only be stored in r0-r3, but these are
all occupied by arguments. This patch makes sure that tail call
optimization does not try to handle this type of calls.
Reviewers: chill, MatzeB, olista01, rengolin, efriedma
Reviewed By: olista01, efriedma
Subscribers: efriedma, aemerson, javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D40706
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319664
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Pavel Labath [Mon, 4 Dec 2017 16:46:20 +0000 (16:46 +0000)]
Revert "[cmake] Enable zlib support on windows"
This reverts commit r319533 as it broke llvm-config --system-libs output
and everything that depends on it (which is mostly out of tree or
downstream folks, but includes a couple of llvm buildbots as well).
I think I have a fix for this in D40779, but I want someone to look
review it first. In the mean time, I am reverting this change, as it
seems to break a lot of people.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319663
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Sam Kolton [Mon, 4 Dec 2017 16:22:32 +0000 (16:22 +0000)]
[AMDGPU] SDWA: add support for PRESERVE into SDWA peephole.
Summary:
Reviewers: arsenm, vpykhtin, rampitec
Subscribers: kzhuravl, wdng, nhaehnle, mgorny, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D37817
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319662
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Sam Parker [Mon, 4 Dec 2017 15:14:59 +0000 (15:14 +0000)]
[ARM] CodeGen test
Add another and + load DAG combine test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319660
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Anna Thomas [Mon, 4 Dec 2017 15:11:48 +0000 (15:11 +0000)]
[Loop Predication] Teach LP about reverse loops
Summary:
Currently, we only support predication for forward loops with step
of 1. This patch enables loop predication for reverse or
countdownLoops, which satisfy the following conditions:
1. The step of the IV is -1.
2. The loop has a singe latch as B(X) = X <pred>
latchLimit with pred as s> or u>
3. The IV of the guard is the decrement
IV of the latch condition (Guard is: G(X) = X-1 u< guardLimit).
This patch was downstream for a while and is the last series of patches
that's from our LP implementation downstream.
Reviewers: apilipenko, mkazantsev, sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40353
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319659
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Jonas Hahnfeld [Mon, 4 Dec 2017 14:19:33 +0000 (14:19 +0000)]
[NVPTX] Assign valid global names
PTX requires that identifiers consist only of [a-zA-Z0-9_$]. The
existing pass already ensured this for globals and this patch adds
the cleanup for functions with local linkage.
However, there was a different problem in the case of collisions
of the adjusted name: The ValueSymbolTable then automatically
appended ".N" with increasing Ns to get a unique name while helping
the ABI demangling. Special case this behavior to omit the dots and
append N directly. This will always give us legal names according
to the PTX requirements.
Differential Revision: https://reviews.llvm.org/D40573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319657
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Jonas Devlieghere [Mon, 4 Dec 2017 14:01:34 +0000 (14:01 +0000)]
[NFC][lit] Use proper semantic versioning names for variables
The variable named `minor` was actually pointing to the patch part of
the version. While I was changing this I also made the check for Apple
clang more robust by checking both patch and minor rather than just
minor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319656
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Oliver Stannard [Mon, 4 Dec 2017 13:42:22 +0000 (13:42 +0000)]
Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands
This is causing a failure in the llvm-clang-x86_64-expensive-checks-win
buildbot, and I can't reproduce it locally, so reverting until I can work out
what is wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319654
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Sam McCall [Mon, 4 Dec 2017 12:51:49 +0000 (12:51 +0000)]
Revert "[ValueTracking] Pass only a single lambda to computeKnownBitsFromShiftOperator by using KnownBits struct instead of separate APInts. NFCI"
This reverts commit r319624, which seems to cause a miscompile (breaks the
multistage PPC buildbots)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319652
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Tim Corringham [Mon, 4 Dec 2017 12:30:49 +0000 (12:30 +0000)]
AMDGPU: fix missing s_waitcnt
Summary:
The pass that inserts s_waitcnt instructions where needed propagated
info used to track dependencies for each block by iterating over the
predecessor blocks. The iteration was terminated when a predecessor
that had not yet been processed was encountered. Any info in blocks
later in the list was therefore not processed, leading to the
possiblility of a required s_waitcnt not being inserted.
The fix is simply to change the "break" to "continue" for the
relevant loops, so that all visited blocks are processed. This
is likely what was intended when the code was written.
There is no test case provided for this fix because:
1) the only example that reproduces this is large and resistant to
being reduced
2) the change is trivial
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D40544
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319651
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Oliver Stannard [Mon, 4 Dec 2017 12:02:32 +0000 (12:02 +0000)]
[Asm, ARM] Add fallback diag for multiple invalid operands
This adds a "invalid operands for instruction" diagnostic for
instructions where there is an instruction encoding with the correct
mnemonic and which is available for this target, but where multiple
operands do not match those which were provided. This makes it clear
that there is some combination of operands that is valid for the current
target, which the default diagnostic of "invalid instruction" does not.
Since this is a very general error, we only emit it if we don't have a
more specific error.
Differential revision: https://reviews.llvm.org/D36747
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319649
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Jonas Paulsson [Mon, 4 Dec 2017 10:03:14 +0000 (10:03 +0000)]
[TwoAddressInstructionPass] Bugfix in handling of sunk instructions.
An instruction returned by TII->convertToThreeAddress() may contain a %noreg
(undef) operand, which is not expected by tryInstructionTransform(). So if
this MI is sunk to a lower point in MBB, it must be skipped when later
encountered.
A new set SunkInstrs is used for this purpose.
Note: there is no test supplied here, as this was triggered on SystemZ while
working on a review of instruction flags. A test case for this bugfix will be
included in the upcoming SystemZ commit.
Review: Quentin Colombet
https://reviews.llvm.org/D40711
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319646
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Sam Parker [Mon, 4 Dec 2017 09:48:26 +0000 (09:48 +0000)]
[DAGCombine] Remove isAndLoadExtLoad arguments
Both LoadedVT and NarrowLoad are passed as references and neither
of them are used by any of its callers.
Differential Revision: https://reviews.llvm.org/D40713
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319645
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Martin Storsjo [Mon, 4 Dec 2017 09:09:04 +0000 (09:09 +0000)]
[AArch64] Allow using emulated tls on platforms other than ELF
This matches how it is done on X86.
This allows using emulated tls on windows; in MinGW environments,
native tls isn't supported at the moment.
Set the right Data*bitsDirective for windows to match the existing
tests for other platforms. Make parts of the existing tests a regex,
to allow matching .section .rdata for windows, to avoid having to
duplicate the rest of the tests for windows.
Differential Revision: https://reviews.llvm.org/D40770
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319644
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Martin Storsjo [Mon, 4 Dec 2017 09:08:55 +0000 (09:08 +0000)]
[ARM] Allow using emulated tls on platforms other than ELF
This matches how it is done on X86.
This allows using emulated tls on windows; in MinGW environments,
native tls isn't supported at the moment.
Differential Revision: https://reviews.llvm.org/D40769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319643
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Craig Topper [Mon, 4 Dec 2017 07:21:01 +0000 (07:21 +0000)]
[X86] Allow VPMAXUQ/VPMAXSQ/VPMINUQ/VPMINSQ to be used with 128/256 bit vectors when AVX512 is enabled.
These instructions can be used by widening to 512-bits and extracting back to 128/256. We do similar to several other instructions already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319641
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Craig Topper [Mon, 4 Dec 2017 05:38:44 +0000 (05:38 +0000)]
[X86] Don't turn UINT_TO_FP into SINT_TO_FP during lowering.
We already do this as a DAG combine. The version during lowering can only trigger if known bits changes something that improves known bits analysis. But this means we should be improving known bits analysis to work on the unlowered form instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319640
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Craig Topper [Mon, 4 Dec 2017 05:38:42 +0000 (05:38 +0000)]
[SelectionDAG] Teach computeKnownBits some improvements to ISD::SRL with a non-splat constant shift amount.
If we have a non-splat constant shift amount, the minimum shift amount can be used to infer the number of zero upper bits of the result. There's probably a lot more that we can do here, but this
fixes a case where I wanted to infer the sign bit as zero when all the shift amounts are non-zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319639
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Simon Pilgrim [Sun, 3 Dec 2017 21:43:54 +0000 (21:43 +0000)]
[X86][AVX512] Tag PH2PS/PS2PH conversion instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319637
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Simon Pilgrim [Sun, 3 Dec 2017 21:16:12 +0000 (21:16 +0000)]
[X86][AVX512] Tag packed F2I/I2F/F2F conversion instructions scheduler class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319636
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Simon Pilgrim [Sun, 3 Dec 2017 21:07:36 +0000 (21:07 +0000)]
[X86][AVX512] Regenerate schedule tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319635
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Simon Pilgrim [Sun, 3 Dec 2017 20:57:04 +0000 (20:57 +0000)]
[X86][SSE] Remove unused IIC_SSE_CVT_PI2PS_RR/IIC_SSE_CVT_PI2PS_RM itineraries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319634
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Yaxun Liu [Sun, 3 Dec 2017 03:31:45 +0000 (03:31 +0000)]
CodeGen: Fix SelectionDAGISel::LowerArguments for sret addr space
SelectionDAGISel::LowerArguments assumes sret addr space is 0, which is
not true for amdgcn---amdgiz target.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D40255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319630
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Craig Topper [Sun, 3 Dec 2017 03:07:09 +0000 (03:07 +0000)]
[SelectionDAG] Use the inlined APInt shift methods since we've already bounds checked the shift.
The version that takes APInt is out of line. The 'unsigned' version optimizes for the common case of single word APInts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319628
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Sam Clegg [Sun, 3 Dec 2017 01:19:23 +0000 (01:19 +0000)]
Reland "[WebAssembly] Add visibility flag to Wasm symbol flags""
Original change was rL319488.
This was reverted rL319602 due to a gcc 7.1 warning.
Differential Revision: https://reviews.llvm.org/D40772
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319626
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Matt Arsenault [Sun, 3 Dec 2017 00:03:01 +0000 (00:03 +0000)]
Fix typo in emitted attribute name
Fixes build when using this attribute combination
on an intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319625
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Craig Topper [Sat, 2 Dec 2017 23:42:17 +0000 (23:42 +0000)]
[ValueTracking] Pass only a single lambda to computeKnownBitsFromShiftOperator by using KnownBits struct instead of separate APInts. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319624
91177308-0d34-0410-b5e6-
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Yaxun Liu [Sat, 2 Dec 2017 22:13:22 +0000 (22:13 +0000)]
CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT
Two issues found when doing codegen for splitting vector with non-zero alloca addr space:
DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT/SplitVecOp_EXTRACT_VECTOR_ELT uses dummy pointer info for creating
SDStore. Since one pointer operand contains multiply and add, InferPointerInfo is unable to
infer the correct pointer info, which ends up with a dummy pointer info for the target to lower
store and results in isel failure. The fix is to introduce MachinePointerInfo::getUnknownStack to
represent MachinePointerInfo which is known in alloca address space but without other information.
TargetLowering::getVectorElementPointer uses value type of pointer in addr space 0 for
multiplication of index and then add it to the pointer. However the pointer may be in an addr
space which has different size than addr space 0. The fix is to use the pointer value type for
index multiplication.
Differential Revision: https://reviews.llvm.org/D39758
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319622
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Don Hinton [Sat, 2 Dec 2017 19:12:38 +0000 (19:12 +0000)]
[cmake] Re-commit: Remove redundant call to cmake when building host tools.
Also pass CMAKE_(C|CXX)_COMPILER to add_custom_command.
Summary:
Remove the redundant, config-time call to cmake when
building host tools for cross compiles or optimized tablegen..
The config-time call to cmake is redundant because it will always get
called again when the CONFIGURE_LLVM_${target_name} target fires at
build-time. This speeds up initial configuration, but has no affect
on build behavior.
Differential Revision: https://reviews.llvm.org/D40229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319620
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Simon Atanasyan [Sat, 2 Dec 2017 13:06:40 +0000 (13:06 +0000)]
[llvm-readobj] Remove redundant local variables to reduce the code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319617
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Simon Atanasyan [Sat, 2 Dec 2017 13:06:35 +0000 (13:06 +0000)]
[llvm-readobj] Print static MIPS GOT
If a linked binary file contains a dynamic section, the GOT layout
defined by the dynamic section entries. In a statically linked file
the GOT is just a series of entries. This change teaches `llvm-readobj`
to print the GOT in that case. That provides a feature parity with GNU
`readelf`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319616
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Simon Atanasyan [Sat, 2 Dec 2017 13:06:27 +0000 (13:06 +0000)]
[llvm-readobj] Delete unused method argument. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319615
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Simon Pilgrim [Sat, 2 Dec 2017 12:27:44 +0000 (12:27 +0000)]
[X86][SSE] Cleanup float/int conversion scheduler itinerary classes
Makes it easier to grok where each is supposed to be used, mainly useful for adding to the AVX512 instructions but hopefully can be used more in SSE/AVX as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319614
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Craig Topper [Sat, 2 Dec 2017 08:39:02 +0000 (08:39 +0000)]
[X86] Fix copy paste mistake in test case for r319612.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319613
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Craig Topper [Sat, 2 Dec 2017 08:27:46 +0000 (08:27 +0000)]
[X86] Teach the assembler to support %db8-%db15 as aliases for %dr8-%dr15.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319612
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Craig Topper [Sat, 2 Dec 2017 08:27:45 +0000 (08:27 +0000)]
[X86] Support %dr8-%dr15 in the assembler.
Apparently I failed to make this work when I fixed it in the disassembler way back in r224862.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319611
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Martell Malone [Sat, 2 Dec 2017 07:17:01 +0000 (07:17 +0000)]
CMAKE: help CheckAtomic find check_library_exists
lldb fails to build standalone on x86
-- Performing Test HAVE_CXX_ATOMICS64_WITHOUT_LIB - Failed
CMake Error at CheckAtomic.cmake:66 (check_library_exists):
Unknown CMake command "check_library_exists".
Call Stack (most recent call first):
LLDBStandalone.cmake:90 (include)
CMakeLists.txt:3 (include)
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D40220
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319610
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Tatyana Krasnukha [Sat, 2 Dec 2017 05:25:17 +0000 (05:25 +0000)]
[ARC] Add instruction subset for the ARC backend.
Reviewers: petecoup, kparzysz
Reviewed By: petecoup
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319609
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Nirav Dave [Sat, 2 Dec 2017 04:01:26 +0000 (04:01 +0000)]
[DAG][AArch64] Disable post-legalization store
Disable post-legalization store for AArch64 backend which is causing
errors out-of-tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319607
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Heejin Ahn [Sat, 2 Dec 2017 02:05:06 +0000 (02:05 +0000)]
[WebAssembly] Revert r319488 "Add visibility flag to Wasm symbol flags"
This patch reportedly broke one of LLVM bots (ubuntu-gcc7.1-werror).
See http://lab.llvm.org:8011/builders/ubuntu-gcc7.1-werror/builds/3369 for
details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319602
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Matt Morehouse [Fri, 1 Dec 2017 22:20:26 +0000 (22:20 +0000)]
Revert "[X86] Improvement in CodeGen instruction selection for LEAs."
This reverts r319543, due to ASan bot breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319591
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Kostya Serebryany [Fri, 1 Dec 2017 22:12:04 +0000 (22:12 +0000)]
[libFuzzer] add a flag -malloc_limit_mb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319590
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Jessica Paquette [Fri, 1 Dec 2017 21:56:56 +0000 (21:56 +0000)]
[MachineOutliner] NFC: Throw out self-intersections on candidates early
Currently, the outliner considers candidates that intersect with themselves in
the candidate pruning step. That is, candidates of the form "AA" in ranges like
"AAAAAA". In that range, it looks like there are 5 instances of "AA" that could
possibly be outlined, and that's considered in the benefit calculation.
However, only at most 3 instances of "AA" could ever be outlined in "AAAAAA".
Thus, it's possible to pass through "AA" to the candidate selection step even
though it's *never* the case that "AA" could be outlined. This makes it so that
when we find candidates, we consider only non-overlapping occurrences of that
candidate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319588
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Nirav Dave [Fri, 1 Dec 2017 21:55:47 +0000 (21:55 +0000)]
[DAG][ARM] Revert "Reenable post-legalize store merge"
due to failures in AArch and ARM code gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319587
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Jake Ehrlich [Fri, 1 Dec 2017 21:44:27 +0000 (21:44 +0000)]
[MC] Handle unknown literal register numbers in .cfi_* directives
r230670 introduced a step to map EH register numbers to standard
DWARF register numbers. This failed to consider the case when a
user .cfi_* directive uses an integer literal rather than a
register name, to specify a DWARF register number that has no
corresponding LLVM register number (e.g. a special register that
the compiler and assembler have no name for).
Fixes PR34028.
Patch by Roland McGrath
Differential Revision: https://reviews.llvm.org/D36493
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319586
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Philip Reames [Fri, 1 Dec 2017 20:57:19 +0000 (20:57 +0000)]
[IndVars] Fix a bug introduced in r317012
Turns out we can have comparisons which are indirect users of the induction variable that we can make invariant. In this case, there is no loop invariant value contributing and we'd fail an assert.
The test case was found by a java fuzzer and reduced. It's a real cornercase. You have to have a static loop which we've already proven only executes once, but haven't broken the backedge on, and an inner phi whose result can be constant folded by SCEV using exit count reasoning but not proven by isKnownPredicate. To my knowledge, only the fuzzer has hit this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319583
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Don Hinton [Fri, 1 Dec 2017 20:46:45 +0000 (20:46 +0000)]
[cmake] Revert (rL319574): Resubmit Remove redundant call to cmake when building host tools.
Still fails for some bots.
Differential Revision: https://reviews.llvm.org/D40229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319582
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Adam Nemet [Fri, 1 Dec 2017 20:41:38 +0000 (20:41 +0000)]
[opt-remarks] If hotness threshold is set, ignore remarks without hotness
These are blocks that haven't not been executed during training. For large
projects this could make a significant difference. For the project, I was
looking at, I got an order of magnitude decrease in the size of the total YAML
files with this and r319235.
Differential Revision: https://reviews.llvm.org/D40678
Re-commit after fixing the failing testcase in rL319576, rL319577 and
rL319578.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319581
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Don Hinton [Fri, 1 Dec 2017 19:35:56 +0000 (19:35 +0000)]
[cmake] Resubmit Remove redundant call to cmake when building host tools.
Only pass Native to LLVM_TARGETS_TO_BUILD.
Summary:
Remove the redundant, config-time call to cmake when
building host tools for cross compiles or optimized tablegen..
The config-time call to cmake is redundant because it will always get
called again when the CONFIGURE_LLVM_${target_name} target fires at
build-time. This speeds up initial configuration, but has no affect
on build behavior.
Differential Revision: https://reviews.llvm.org/D40229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319574
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Eli Friedman [Fri, 1 Dec 2017 19:33:56 +0000 (19:33 +0000)]
[DAGCombine] Simplify ISD::AND handling in ReduceLoadWidth
Followup to D39595. Removes a bunch of redundant checks.
Differential Revision: https://reviews.llvm.org/D40667
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319573
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Simon Pilgrim [Fri, 1 Dec 2017 18:40:32 +0000 (18:40 +0000)]
[X86][AVX512] Tag subvector extract/insert instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319568
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Benjamin Kramer [Fri, 1 Dec 2017 18:39:58 +0000 (18:39 +0000)]
[IR] Avoid dangling else warning. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319567
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