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Reid Kleckner [Thu, 19 Jul 2018 19:58:22 +0000 (19:58 +0000)]
Fix -Wsign-compare in llvm-readobj
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337490
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Roman Tereshin [Thu, 19 Jul 2018 19:42:43 +0000 (19:42 +0000)]
[LSV] Refactoring + supporting bitcasts to a type of different size
This is mostly a preparation work for adding a limited support for
select instructions. It proved to be difficult to do due to size and
irregularity of Vectorizer::isConsecutiveAccess, this is fixed here I
believe.
It also turned out that these changes make it simpler to finish one of
the TODOs and fix a number of other small issues, namely:
1. Looking through bitcasts to a type of a different size (requires
careful tracking of the original load/store size and some math
converting sizes in bytes to expected differences in indices of GEPs).
2. Reusing partial analysis of pointers done by first attempt in proving
them consecutive instead of starting from scratch. This added limited
support for nested GEPs co-existing with difficult sext/zext
instructions. This also required a careful handling of negative
differences between constant parts of offsets.
3. Handing a case where the first pointer index is not an add, but
something else (a function parameter for instance).
I observe an increased number of successful vectorizations on a large
set of shader programs. Only few shaders are affected, but those that
are affected sport >5% less loads and stores than before the patch.
Reviewed By: rampitec
Differential-Revision: https://reviews.llvm.org/D49342
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337489
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Stefan Pintilie [Thu, 19 Jul 2018 19:34:18 +0000 (19:34 +0000)]
[Power9] Code Cleanup - Remove needsAggressiveScheduling()
As we already return true from needsAggressiveScheduling() for the most recent
hardware it would be cleaner to just return true for all PowerPC hardware.
Differential Revision: https://reviews.llvm.org/D48663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337488
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Shoaib Meenai [Thu, 19 Jul 2018 19:11:29 +0000 (19:11 +0000)]
[Analysis] Fix typo in assert. NFC
Test commit to see if my mailing list woes have been resolved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337485
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Mandeep Singh Grang [Thu, 19 Jul 2018 18:10:03 +0000 (18:10 +0000)]
[OpenEmbedded] Add a unittest for aarch64-oe-linux
Summary: Added a unittest for aarch64-oe-linux which was missed in D48861.
Reviewers: compnerd, rengolin, javed.absar
Reviewed By: compnerd
Subscribers: kristof.beyls, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D49314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337479
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Krzysztof Parzyszek [Thu, 19 Jul 2018 18:07:56 +0000 (18:07 +0000)]
[APInt] Keep the original bit width in quotient and remainder
Some trivial cases in udivrem were handled by directly assigning 0 or 1
to APInt objects. This would set the bit width to 1, instead of the bit
width of the inputs. A potentially undesirable side effect of that is
that with the bit width of 1, 1 equals -1.
Differential Revision: https://reviews.llvm.org/D49554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337478
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Matt Morehouse [Thu, 19 Jul 2018 17:59:11 +0000 (17:59 +0000)]
[libFuzzer] Update documentation regarding MSan.
Summary: -fsanitize=fuzzer,memory now works out-of-the-box.
Reviewers: kcc
Reviewed By: kcc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49441
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337476
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Farhana Aleen [Thu, 19 Jul 2018 16:50:27 +0000 (16:50 +0000)]
[LoadStoreVectorizer] Use getMinusScev() to compute the distance between two pointers.
Summary: Currently, isConsecutiveAccess() detects two pointers(PtrA and PtrB) as consecutive by
comparing PtrB with BaseDelta+PtrA. This works when both pointers are factorized or
both of them are not factorized. But isConsecutiveAccess() fails if one of the
pointers is factorized but the other one is not.
Here is an example:
PtrA = 4 * (A + B)
PtrB = 4 + 4A + 4B
This patch uses getMinusSCEV() to compute the distance between two pointers.
getMinusSCEV() allows combining the expressions and computing the simplified distance.
Author: FarhanaAleen
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D49516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337471
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Andrea Di Biagio [Thu, 19 Jul 2018 16:42:15 +0000 (16:42 +0000)]
[X86][BtVer2] correctly model the latency/throughput of LEA instructions.
This patch fixes the latency/throughput of LEA instructions in the BtVer2
scheduling model.
On Jaguar, A 3-operands LEA has a latency of 2cy, and a reciprocal throughput of
1. That is because it uses one cycle of SAGU followed by 1cy of ALU1. An LEA
with a "Scale" operand is also slow, and it has the same latency profile as the
3-operands LEA. An LEA16r has a latency of 3cy, and a throughput of 0.5 (i.e.
RThrouhgput of 2.0).
This patch adds a new TIIPredicate named IsThreeOperandsLEAFn to X86Schedule.td.
The tablegen backend (for instruction-info) expands that definition into this
(file X86GenInstrInfo.inc):
```
static bool isThreeOperandsLEA(const MachineInstr &MI) {
return (
(
MI.getOpcode() == X86::LEA32r
|| MI.getOpcode() == X86::LEA64r
|| MI.getOpcode() == X86::LEA64_32r
|| MI.getOpcode() == X86::LEA16r
)
&& MI.getOperand(1).isReg()
&& MI.getOperand(1).getReg() != 0
&& MI.getOperand(3).isReg()
&& MI.getOperand(3).getReg() != 0
&& (
(
MI.getOperand(4).isImm()
&& MI.getOperand(4).getImm() != 0
)
|| (MI.getOperand(4).isGlobal())
)
);
}
```
A similar method is generated in the X86_MC namespace, and included into
X86MCTargetDesc.cpp (the declaration lives in X86MCTargetDesc.h).
Back to the BtVer2 scheduling model:
A new scheduling predicate named JSlowLEAPredicate now checks if either the
instruction is a three-operands LEA, or it is an LEA with a Scale value
different than 1.
A variant scheduling class uses that new predicate to correctly select the
appropriate latency profile.
Differential Revision: https://reviews.llvm.org/D49436
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337469
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Simon Pilgrim [Thu, 19 Jul 2018 15:32:45 +0000 (15:32 +0000)]
[X86][SSE] Add FPEXT vXf32 - vXf64 tests
Some basic subvector special cases based on PR36761
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337464
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George Rimar [Thu, 19 Jul 2018 14:52:57 +0000 (14:52 +0000)]
[llvm-readobj] - Do not report invalid amount of sections.
When output style is GNU and amount of sections is >= SHN_LORESERVE,
llvm-readobj reports zero number of sections instead of actual value.
The patch fixes that.
Differential revision: https://reviews.llvm.org/D49544
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337462
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Teresa Johnson [Thu, 19 Jul 2018 14:51:32 +0000 (14:51 +0000)]
[ThinLTO] Enable ThinLTO WholeProgramDevirt and LowerTypeTests in new PM
Summary:
Enable these passes for CFI and WPD in ThinLTO and LTO with the new pass
manager. Add a couple of tests for both PMs based on the clang tests
tools/clang/test/CodeGen/thinlto-distributed-cfi*.ll, but just test
through llvm-lto2 and not with distributed ThinLTO.
Reviewers: pcc
Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D49429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337461
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Anastasis Grammenos [Thu, 19 Jul 2018 14:08:54 +0000 (14:08 +0000)]
[Docs] Testing Debug Info Preservation in Optimizations
Differential Revision: https://reviews.llvm.org/D49053
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337457
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Tim Northover [Thu, 19 Jul 2018 12:44:51 +0000 (12:44 +0000)]
ARM: switch armv7em MachO triple to hard-float defaults and libcalls.
We were emitting incorrect calls to libm functions that LLVM had decided it
knew about because the default is soft-float.
Recommitted without breaking ELF this time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337450
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David Green [Thu, 19 Jul 2018 12:37:00 +0000 (12:37 +0000)]
[UnJ] Document unroll and jam pass and loop metadata
Add some quick words for unroll and jam to the list of passes and add
unroll_and_jam metadata to the language ref.
Differential Revision: https://reviews.llvm.org/D49349
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337448
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Chandler Carruth [Thu, 19 Jul 2018 11:13:58 +0000 (11:13 +0000)]
[x86/SLH] Major refactoring of SLH implementaiton. There are two big
changes that are intertwined here:
1) Extracting the tracing of predicate state through the CFG to its own
function.
2) Creating a struct to manage the predicate state used throughout the
pass.
Doing #1 necessitates and motivates the particular approach for #2 as
now the predicate management is spread across different functions
focused on different aspects of it. A number of simplifications then
fell out as a direct consequence.
I went with an Optional to make it more natural to construct the
MachineSSAUpdater object.
This is probably the single largest outstanding refactoring step I have.
Things get a bit more surgical from here. My current goal, beyond
generally making this maintainable long-term, is to implement several
improvements to how we do interprocedural tracking of predicate state.
But I don't want to do that until the predicate state management and
tracing is in reasonably clear state.
Differential Revision: https://reviews.llvm.org/D49427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337446
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Simon Pilgrim [Thu, 19 Jul 2018 09:27:34 +0000 (09:27 +0000)]
[DAGCombiner] Add rotate-extract tests
Add new tests from D47681 to current codegen. Also added i686 codegen tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337445
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Serge Guelton [Thu, 19 Jul 2018 09:24:34 +0000 (09:24 +0000)]
Use std::reference_wrapper instead of llvm::ReferenceStorage
Reviewed By: Bigcheese
Differential Revision: https://reviews.llvm.org/D49298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337444
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Simon Pilgrim [Thu, 19 Jul 2018 09:14:39 +0000 (09:14 +0000)]
Fix spelling mistake in comments. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337442
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Max Kazantsev [Thu, 19 Jul 2018 01:46:21 +0000 (01:46 +0000)]
[SCEV] Fix buggy behavior in getAddExpr with truncs
SCEV tries to constant-fold arguments of trunc operands in SCEVAddExpr, and when it does
that, it passes wrong flags into the recursion. It is only valid to pass flags that are proved for
narrow type into a computation in wider type if we can prove that trunc instruction doesn't
actually change the value. If it did lose some meaningful bits, we may end up proving wrong
no-wrap flags for sum of arguments of trunc.
In the provided test we end up with `nuw` where it shouldn't be because of this bug.
The solution is to conservatively pass `SCEV::FlagAnyWrap` which is always a valid thing to do.
Reviewed By: sanjoy
Differential Revision: https://reviews.llvm.org/D49471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337435
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Peter Collingbourne [Wed, 18 Jul 2018 22:23:14 +0000 (22:23 +0000)]
Rename __asan_gen_* symbols to ___asan_gen_*.
This prevents gold from printing a warning when trying to export
these symbols via the asan dynamic list after ThinLTO promotes them
from private symbols to external symbols with hidden visibility.
Differential Revision: https://reviews.llvm.org/D49498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337428
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Heejin Ahn [Wed, 18 Jul 2018 21:42:22 +0000 (21:42 +0000)]
[WebAssembly] Add missing -mattr=+exception-handling guards
Summary:
The use of exception handling instructions should only be enabled with
`-mattr=+exception-handling` option.
Reviewers: jgravelle-google
Subscribers: dschuff, sbc100, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337425
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Tim Northover [Wed, 18 Jul 2018 21:32:49 +0000 (21:32 +0000)]
Revert "ARM: switch armv7em triple to hard-float defaults and libcalls."
This reverts commit r337385 until it can be targeted at MachO only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337424
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David Blaikie [Wed, 18 Jul 2018 20:37:01 +0000 (20:37 +0000)]
Fix some tests that had (implied) duplicate mtriple
I 'fixed' one of these to use %llc_dwarf unnecessarily, so switch them
both back to using llc directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337423
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Simon Pilgrim [Wed, 18 Jul 2018 19:55:19 +0000 (19:55 +0000)]
[X86][SSE] Canonicalize scalar fp arithmetic shuffle patterns
As discussed on PR38197, this canonicalizes MOVS*(N0, OP(N0, N1)) --> MOVS*(N0, SCALAR_TO_VECTOR(OP(N0[0], N1[0])))
This returns the scalar-fp codegen lost by rL336971.
Additionally it handles the OP(N1, N0)) case for commutable (FADD/FMUL) ops.
Differential Revision: https://reviews.llvm.org/D49474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337419
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Xin Tong [Wed, 18 Jul 2018 18:40:45 +0000 (18:40 +0000)]
Skip debuginfo intrinsic in markLiveBlocks.
Summary:
The optimizer is 10%+ slower with vs without debuginfo. I started checking where
the difference is coming from.
I compiled sqlite3.c with and without debug info from CTMark and compare the time difference.
I use Xcode Instrument to find where time is spent. This brings about 20ms, out of ~20s.
Reviewers: davide, hfinkel
Reviewed By: hfinkel
Subscribers: hfinkel, aprantl, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D49337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337416
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Roman Lebedev [Wed, 18 Jul 2018 18:35:27 +0000 (18:35 +0000)]
Add (very partial) Kate syntax highlighting definition for TableGen
This is very clearly not very good, and is very partial.
But this is better than nothing at all, and shouldn't
hurt those who don't need it.
If there are others interested in this functionality,
it will be great to further improve this.
{
F6253091}
Reviewed By: Bigcheese
Differential Revision: https://reviews.llvm.org/D47080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337415
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Nirav Dave [Wed, 18 Jul 2018 18:34:52 +0000 (18:34 +0000)]
[DAG] Add testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337414
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David Blaikie [Wed, 18 Jul 2018 18:04:42 +0000 (18:04 +0000)]
[DebugInfo] Dwarfv5: Avoid unnecessary base_address specifiers in rnglists
Since DWARFv5 rnglists are self descriptive and have distinct encodings
for base-relative (offset_pair) and absolute (start_length) entries,
there's no need to use a base address specifier when describing a lone
address range in a section.
Use that, and improve the test coverage a bit here to include cases like
this and others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337411
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Nirav Dave [Wed, 18 Jul 2018 18:01:03 +0000 (18:01 +0000)]
[ScheduleDAG] Fix unfolding of SUnits to already existent nodes.
Summary:
If unfolding an SUnit results in both load or the operation using it which
already exist in the DAG, abort the unfold if they are already scheduled.
If not, make sure we don't add duplicate dependencies.
This fixes PR37916.
Reviewers: davide, eli.friedman, fhahn, bogner
Subscribers: MatzeB, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D48666
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337409
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Paul Semel [Wed, 18 Jul 2018 18:00:41 +0000 (18:00 +0000)]
[llvm-readobj] Generic -string-dump option
Differential Revision: https://reviews.llvm.org/D49470
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337408
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Teresa Johnson [Wed, 18 Jul 2018 17:10:17 +0000 (17:10 +0000)]
[docs] Update GoldPlugin documentation
Summary:
Updated and reorganized. Made the following additions:
1) How to see if ld.gold is installed, and whether it is the current
default.
2) How to install ld.gold as the default or alternatively use
-fuse-ld=gold.
3) Move the part about installing the newly built ld-new as the default
to the prior section and how to use --enable-gold=default to do it
automatically on install.
4) Add a note about ld.bfd supporting plugins but indicate that it is
not tested by the LLVM project and gold is the recommended linker for
use with the gold plugin.
Fixes PR32760.
Reviewers: davide
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337404
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Wei Mi [Wed, 18 Jul 2018 16:56:33 +0000 (16:56 +0000)]
[RegAlloc][NFC] Fix the help string of the option "huge-size-for-split".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337402
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Paul Semel [Wed, 18 Jul 2018 16:39:21 +0000 (16:39 +0000)]
[llvm-objdump] Add -demangle (-C) option
Differential Revision: https://reviews.llvm.org/D49043
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337401
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Roman Lebedev [Wed, 18 Jul 2018 16:19:06 +0000 (16:19 +0000)]
[NFC][X86][AArch64][DAGCombine] More tests for optimizeSetCCOfSignedTruncationCheck()
At least one of these cases is more canonical,
so we really do have to handle it.
https://godbolt.org/g/pkzP3X
https://rise4fun.com/Alive/pQyh
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337400
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Benjamin Kramer [Wed, 18 Jul 2018 16:17:53 +0000 (16:17 +0000)]
[llvm-objcopy] %python wants to be in quotes, because it might contain spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337399
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Nirav Dave [Wed, 18 Jul 2018 16:17:03 +0000 (16:17 +0000)]
[MC] Fix nested macro body parsing
Add missing .rep case in nestlevel checking for macro body parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337398
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Simon Atanasyan [Wed, 18 Jul 2018 14:11:22 +0000 (14:11 +0000)]
[mips] Fix predicate for the MipsTruncIntFP pattern
This is a follow-up to the rL337171. This patch fixes regression
introduced by the r337171 and enables MipsTruncIntFP pattern.
Differential revision: https://reviews.llvm.org/D49469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337392
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Chandler Carruth [Wed, 18 Jul 2018 14:05:14 +0000 (14:05 +0000)]
[x86/SLH] Add the design document for Speculative Load Hardening,
a Spectre v1 mitigation.
This was initially posted w/ the patch implementing this, got some basic
review there. Also, it is generated from a the Google doc that I shared
as part of the Speculative Load Hardening RFC and which has seen pretty
widespread review at this point.
However, as the patches are landing in LLVM, I wanted to land the docs
as well. But it seemed like a bad idea to have them in the same commit
in case of reverts or other things. So the docs are split out here.
Thanks for all the review so far, and further review and improvements to
the documentation here welcome. Please feel free to keep hammering on
the code review or Google document.
Note that this is a markdown document which Sphinx doesn't yet process.
But we can add support for that after and this should get picked up
(and I'm preparing patches for that). Also, this gets the document
itself into a nice shared place where we can iterate on it.
Differential Revision: https://reviews.llvm.org/D49433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337391
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Simon Pilgrim [Wed, 18 Jul 2018 13:53:55 +0000 (13:53 +0000)]
[SLPVectorizer] Avoid duplicate scalar cost calculations in BoUpSLP::getEntryCost. NFCI.
Pulled out from D49225, we have a lot of repeated scalar cost calculations, often with arguments that don't look the same but turn out to be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337390
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Tim Northover [Wed, 18 Jul 2018 13:42:18 +0000 (13:42 +0000)]
[Support] Build fix for Haiku when checking for a local filesystem
Haiku does not expose information about local versus remote mounts, so just
return false, like Cygwin.
Patch by Niels Sascha Reedijk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337389
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Simon Pilgrim [Wed, 18 Jul 2018 13:01:20 +0000 (13:01 +0000)]
[X86][SSE] Remove BLENDPD canonicalization from combineTargetShuffle
When rL336971 removed the scalar-fp isel patterns, we lost the need for this canonicalization - commutation/folding can handle everything else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337387
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Tim Northover [Wed, 18 Jul 2018 12:37:43 +0000 (12:37 +0000)]
ARM: stop explicitly marking armv7k libcalls as hard-float. NFC.
Since the triple's default is hard float, the libcalls will already use VFP
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337386
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Tim Northover [Wed, 18 Jul 2018 12:37:04 +0000 (12:37 +0000)]
ARM: switch armv7em triple to hard-float defaults and libcalls.
We were emitting incorrect calls to libm functions that LLVM had decided it
knew about because the default is soft-float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337385
91177308-0d34-0410-b5e6-
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Tim Northover [Wed, 18 Jul 2018 12:36:25 +0000 (12:36 +0000)]
ARM: deduplicate hard-float detection code. NFC.
ARMSubtarget had a copy/pasted block to determine whether the target was
hard-float, but it just delegated to triple features anyway so it's better at
the TargetMachine level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337384
91177308-0d34-0410-b5e6-
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Sander de Smalen [Wed, 18 Jul 2018 11:59:12 +0000 (11:59 +0000)]
[AArch64][SVE] Asm: Support for unpredicated FP operations.
This patch adds support for the following unpredicated
floating-point instructions:
FADD Floating point add
FSUB Floating point subtract
FMUL Floating point multiplication
FTSMUL Floating point trigonometric starting value
FRECPS Floating point reciprocal step
FRSQRTS Floating point reciprocal square root step
The instructions have the following assembly format:
fadd z0.h, z1.h, z2.h
and have variants for 16, 32 and 64-bit FP elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337383
91177308-0d34-0410-b5e6-
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Andrea Di Biagio [Wed, 18 Jul 2018 11:16:31 +0000 (11:16 +0000)]
[TargetInstPredicate] Add definition of CheckInvalidRegisterOperand.
This should have been part of r337378. I forgot to svn add it before committing
the change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337380
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Max Kazantsev [Wed, 18 Jul 2018 11:03:40 +0000 (11:03 +0000)]
[NFC] Make a test more neat
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337379
91177308-0d34-0410-b5e6-
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Andrea Di Biagio [Wed, 18 Jul 2018 11:03:22 +0000 (11:03 +0000)]
[Tablegen][PredicateExpander] Add the ability to define checks for invalid registers.
This was discussed in review D49436.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337378
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Roman Lebedev [Wed, 18 Jul 2018 10:55:17 +0000 (10:55 +0000)]
[InstCombine] Re-commit: Fold 'check for [no] signed truncation' pattern
Summary:
[[ https://bugs.llvm.org/show_bug.cgi?id=38149 | PR38149 ]]
As discussed in https://reviews.llvm.org/D49179#
1158957 and later,
the IR for 'check for [no] signed truncation' pattern can be improved:
https://rise4fun.com/Alive/gBf
^ that pattern will be produced by Implicit Integer Truncation sanitizer,
https://reviews.llvm.org/D48958 https://bugs.llvm.org/show_bug.cgi?id=21530
in signed case, therefore it is probably a good idea to improve it.
The DAGCombine will reverse this transform, see
https://reviews.llvm.org/D49266
This transform is surprisingly frustrating.
This does not deal with non-splat shift amounts, or with undef shift amounts.
I've outlined what i think the solution should be:
```
// Potential handling of non-splats: for each element:
// * if both are undef, replace with constant 0.
// Because (1<<0) is OK and is 1, and ((1<<0)>>1) is also OK and is 0.
// * if both are not undef, and are different, bailout.
// * else, only one is undef, then pick the non-undef one.
```
This is a re-commit, as the original patch, committed in rL337190
was reverted in rL337344 as it broke chromium build:
https://bugs.llvm.org/show_bug.cgi?id=38204 and
https://crbug.com/864832
Proofs that the fixed folds are ok: https://rise4fun.com/Alive/VYM
Differential Revision: https://reviews.llvm.org/D49320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337376
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Simon Pilgrim [Wed, 18 Jul 2018 10:54:13 +0000 (10:54 +0000)]
[X86][SSE] Add extra scalar fop + blend tests for commuted inputs
While working on PR38197, I noticed that we don't make use of FADD/FMUL being able to commute the inputs to support the addps+movss -> addss style combine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337375
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Daniel Cederman [Wed, 18 Jul 2018 10:05:30 +0000 (10:05 +0000)]
Revert "[Sparc] Use the IntPair reg class for r constraints with value type f64"
This reverts commit
55222c9183c6e07f53a54c4061677734f54feac1.
I missed that this patch has a dependency on https://reviews.llvm.org/D49219
that has not been approved yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337373
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Sander de Smalen [Wed, 18 Jul 2018 09:37:51 +0000 (09:37 +0000)]
[AArch64][SVE] Asm: Support for UDOT/SDOT instructions.
The signed/unsigned DOT instructions perform a dot-product on
quadtuplets from two source vectors and accumulate the result in
the destination register. The instructions come in two forms:
Vector form, e.g.
sdot z0.s, z1.b, z2.b - signed dot product on four 8-bit quad-tuplets,
accumulating results in 32-bit elements.
udot z0.d, z1.h, z2.h - unsigned dot product on four 16-bit quad-tuplets,
accumulating results in 64-bit elements.
Indexed form, e.g.
sdot z0.s, z1.b, z2.b[3] - signed dot product on four 8-bit quad-tuplets
with specified quadtuplet from second
source vector, accumulating results in 32-bit
elements.
udot z0.d, z1.h, z2.h[1] - dot product on four 16-bit quad-tuplets
with specified quadtuplet from second
source vector, accumulating results in 64-bit
elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337372
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George Rimar [Wed, 18 Jul 2018 09:25:36 +0000 (09:25 +0000)]
[llvm-objdump] - An attempt to fix BB after r337361.
Seems r337361 is the reason of the following ARM BB failures:
http://lab.llvm.org:8011/builders/clang-cmake-armv8-quick
http://lab.llvm.org:8011/builders/clang-cmake-armv8-full/builds/4633
Reason is unclear to me, other bots are OK.
If this will not help, I'll revert r337361.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337371
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Daniel Cederman [Wed, 18 Jul 2018 09:25:33 +0000 (09:25 +0000)]
[Sparc] Use the IntPair reg class for r constraints with value type f64
Summary: This is how it appears to be handled in GCC and it prevents a
"Unknown mismatch" error in the SelectionDAGBuilder.
Reviewers: venkatra, jyknight, jrtc27
Reviewed By: jyknight, jrtc27
Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D49218
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337370
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Sander de Smalen [Wed, 18 Jul 2018 09:17:29 +0000 (09:17 +0000)]
[AArch64][SVE] Asm: Integer divide instructions.
This patch adds the following predicated instructions:
UDIV Unsigned divide active elements
UDIVR Unsigned divide active elements, reverse form.
SDIV Signed divide active elements
SDIVR Signed divide active elements, reverse form.
e.g.
udiv z0.s, p0/m, z0.s, z1.s
(unsigned divide active elements in z0 by z1, store result in z0)
sdivr z0.s, p0/m, z0.s, z1.s
(signed divide active elements in z1 by z0, store result in z0)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337369
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Simon Pilgrim [Wed, 18 Jul 2018 09:10:18 +0000 (09:10 +0000)]
Fix -Wdocumentation warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337368
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 18 Jul 2018 09:07:54 +0000 (09:07 +0000)]
Fix -Wdocumentation warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337367
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Philip Pfaffe [Wed, 18 Jul 2018 08:53:31 +0000 (08:53 +0000)]
[CMake] Export the LLVM_LINK_LLVM_DYLIB setting
Summary:
When building out-of-tree tools, there are several macros available to
automate linking against llvm. An examples is `add_llvm_executable`, or
the clang variant of this.
These macros use the LLVM_LINK_LLVM_DYLIB option to decide whether to
link against libraries defined by setting LLVM_LINK_COMPONENTS or to
link against libLLVM instead. Currently this is problematic in
out-of-tree targets, because they cannot identify whether this option is
required or even available. If the option was enabled in LLVM's own
build, the clang libraries are built against libLLVM, so a client
linking against those must link against it too. On the other hand the
client can't just always link against it, because it might not be
available.
This is related to D44391, but that change assumed the client knew
whether they wanted the dylib or not.
Reviewers: mgorny, beanz, labath
Reviewed By: mgorny
Subscribers: bollu, llvm-commits
Differential Revision: https://reviews.llvm.org/D49193
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337366
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Roman Lebedev [Wed, 18 Jul 2018 08:49:51 +0000 (08:49 +0000)]
[NFC][InstCombine] i65 tests for 'check for [no] signed truncation' pattern
Those initially broke chromium build:
https://bugs.llvm.org/show_bug.cgi?id=38204 and
https://crbug.com/864832
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337364
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George Rimar [Wed, 18 Jul 2018 08:34:35 +0000 (08:34 +0000)]
[llvm-objdump] - Stop reporting bogus section IDs.
Imagine we have a file with few sections, and one of them is .foo
with index N != 0.
Problem is that when llvm-objdump is given a -section=.foo parameter
it lists .foo as a section at index 0. That makes impossible to write
test cases which needs to find the index of the particular section,
while ignoring dumping of others.
The patch fixes that.
Differential revision: https://reviews.llvm.org/D49372
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337361
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George Rimar [Wed, 18 Jul 2018 08:19:58 +0000 (08:19 +0000)]
[llvm-readobj] - Teach tool to dump objects with >= SHN_LORESERVE of sections.
http://www.sco.com/developers/gabi/2003-12-17/ch4.eheader.html
says that e_shnum and/or e_shstrndx may have special values if
"the number of sections is greater than or equal to SHN_LORESERVE" or
"the section name string table section index is greater than or equal to SHN_LORESERVE (0xff00)"
Previously llvm-readobj was unable to dump such files, patch changes that.
I had to add a precompiled test case because it does not seem possible to
prepare a test using yaml2obj or llvm-mc (not clear how to make .shstrtab
to have index >= SHN_LORESERVE).
Differential revision: https://reviews.llvm.org/D49369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337360
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Roman Lebedev [Wed, 18 Jul 2018 08:15:13 +0000 (08:15 +0000)]
Revert test changes part of "Revert "[InstCombine] Fold 'check for [no] signed truncation' pattern""
We want the test to remain good anyway.
I think the fix is incoming.
This reverts part of commit rL337344.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337359
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Sander de Smalen [Wed, 18 Jul 2018 08:10:03 +0000 (08:10 +0000)]
[AArch64][SVE] Asm: Support for integer MUL instructions.
This patch adds the following instructions:
MUL - multiply vectors, e.g.
mul z0.h, p0/m, z0.h, z1.h
- multiply with immediate, e.g.
mul z0.h, z0.h, #127
SMULH - signed multiply returning high half, e.g.
smulh z0.h, p0/m, z0.h, z1.h
UMULH - unsigned multiply returning high half, e.g.
umulh z0.h, p0/m, z0.h, z1.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337358
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Craig Topper [Wed, 18 Jul 2018 07:31:32 +0000 (07:31 +0000)]
[X86] Enable commuting of VUNPCKHPD to VMOVLHPS to enable load folding by using VMOVLPS with a modified address.
This required an annoying amount of tablegen multiclass changes to make only VUNPCKHPDZ128rr commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337357
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Craig Topper [Wed, 18 Jul 2018 07:31:30 +0000 (07:31 +0000)]
[X86] Add test case for missed opportunity to commute vunpckhpd to enable use of vmovlps to fold a load.
We do this transform for SSE, but not AVX or AVX512VL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337356
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Craig Topper [Wed, 18 Jul 2018 07:08:28 +0000 (07:08 +0000)]
[X86] Regenerate fma.ll checks using current version of the script which produces different regular expressions on spills and reloads. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337354
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Hiroshi Inoue [Wed, 18 Jul 2018 06:04:43 +0000 (06:04 +0000)]
[NFC] fix trivial typos in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337351
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Justin Hibbits [Wed, 18 Jul 2018 05:19:25 +0000 (05:19 +0000)]
Fix build failures from r337347, found by clang
* Delete a no-longer-used override, and mark the other
getRegisterTypeForCallingConv() as override.
* SPE only supports i32, not i64, as the internal type, so simply remove
the type check, so that DestReg and Opc are provably always set.
GCC 6.4 did not warn about either of the above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337350
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Craig Topper [Wed, 18 Jul 2018 05:10:53 +0000 (05:10 +0000)]
[X86] Remove patterns that mix X86ISD::MOVLHPS/MOVHLPS with v2i64/v2f64 types.
The X86ISD::MOVLHPS/MOVHLPS should now only be emitted in SSE1 only. This means that the v2i64/v2f64 types would be illegal thus we don't need these patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337349
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 18 Jul 2018 05:10:51 +0000 (05:10 +0000)]
[X86] Generate v2f64 X86ISD::UNPCKL/UNPCKH instead of X86ISD::MOVLHPS/MOVHLPS for unary v2f64 {0,0} and {1,1} shuffles with SSE2.
I'm trying to restrict the MOVLHPS/MOVHLPS ISD nodes to SSE1 only. With SSE2 we can use unpcks. I believe this will allow some patterns to be cleaned up to require fewer bitcasts.
I've put in an odd isel hack to still select MOVHLPS instruction from the unpckh node to avoid changing tests and because movhlps is a shorter encoding. Ideally we'd do execution domain switching on this, but the operands are in the wrong order and are tied. We might be able to try a commute in the domain switching using custom code.
We already support domain switching for UNPCKLPD and MOVLHPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337348
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Justin Hibbits [Wed, 18 Jul 2018 04:25:10 +0000 (04:25 +0000)]
Introduce codegen for the Signal Processing Engine
Summary:
The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1,
e500v2, and several e200 cores. This adds support targeting the e500v2,
as this is more common than the e500v1, and is in SoCs still on the
market.
This patch is very intrusive because the SPE is binary incompatible with
the traditional FPU. After discussing with others, the cleanest
solution was to make both SPE and FPU features on top of a base PowerPC
subset, so all FPU instructions are now wrapped with HasFPU predicates.
Supported by this are:
* Code generation following the SPE ABI at the LLVM IR level (calling
conventions)
* Single- and Double-precision math at the level supported by the APU.
Still to do:
* Vector operations
* SPE intrinsics
As this changes the Callee-saved register list order, one test, which
tests the precise generated code, was updated to account for the new
register order.
Reviewed by: nemanjai
Differential Revision: https://reviews.llvm.org/D44830
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337347
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Justin Hibbits [Wed, 18 Jul 2018 04:24:57 +0000 (04:24 +0000)]
Complete the SPE instruction set patterns
This is the lead-up to having SPE codegen. Add the rest of the
instructions, along with MC tests.
Differential Revision: https://reviews.llvm.org/D44829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337346
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Justin Hibbits [Wed, 18 Jul 2018 04:24:49 +0000 (04:24 +0000)]
Add PowerPC e500(v2) core scheduler and directives.
Differential Revision: https://reviews.llvm.org/D44828
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337345
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Bob Haarman [Wed, 18 Jul 2018 02:18:28 +0000 (02:18 +0000)]
Revert "[InstCombine] Fold 'check for [no] signed truncation' pattern"
This reverts r337190 (and a few follow-up commits), which caused the
Chromium build to fail. See
https://bugs.llvm.org/show_bug.cgi?id=38204 and
https://crbug.com/864832
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337344
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Wed, 18 Jul 2018 00:21:40 +0000 (00:21 +0000)]
CodeGen: Don't create address significance table entries for thread-local variables.
The presence of these symbols in the symbol table can cause symbol type
mismatch errors (or undefined symbol errors on emulated TLS targets)
and they can't be ICF'd anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337338
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Puyan Lotfi [Wed, 18 Jul 2018 00:10:51 +0000 (00:10 +0000)]
[NFC][llvm-objcopy] Cleanup namespace usage in llvm-objcopy.
Nest any classes not used outside of a file into anon. Nest any classes used
across files in llvm-objcopy into namespace llvm::objcopy.
Differential Revision: https://reviews.llvm.org/D49449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337337
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Craig Topper [Tue, 17 Jul 2018 23:26:20 +0000 (23:26 +0000)]
[X86] Remove the vector alignment requirement from the patterns added in r337320.
The resulting instruction will only load 64 bits so alignment isn't required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337334
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Peter Collingbourne [Tue, 17 Jul 2018 22:40:08 +0000 (22:40 +0000)]
CodeGen: Add a target option for emitting .addrsig directives for all address-significant symbols.
Differential Revision: https://reviews.llvm.org/D48143
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337331
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Peter Collingbourne [Tue, 17 Jul 2018 22:17:18 +0000 (22:17 +0000)]
MC: Implement support for new .addrsig and .addrsig_sym directives.
Part of the address-significance tables proposal:
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123514.html
Differential Revision: https://reviews.llvm.org/D47744
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337328
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Eli Friedman [Tue, 17 Jul 2018 20:38:11 +0000 (20:38 +0000)]
[LangRef] Clarify semantics of load metadata.
We need to explicitly state what happens when an invariant promised by
load metadata is violated at runtime, since it's come up repeatedly.
It's possible we want to specify that the result of the load is poison
in some cases, rather than undefined behavior, if the constraint is
violated. That would allow preserving the metadata when the load is
hoisted, but doesn't allow propagating metadata based on control flow.
We currently do transforms based on control flow for nonnull metadata
(in PromoteMemToReg).
Differential Revision: https://reviews.llvm.org/D47854
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337325
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Eli Friedman [Tue, 17 Jul 2018 20:31:42 +0000 (20:31 +0000)]
[LangRef] nnan and ninf produce poison.
Clarify that violating nnan and ninf can lead to undefined behavior.
This allows more aggressive optimizations based on those assumptions.
Differential Revision: https://reviews.llvm.org/D47963
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337323
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Eli Friedman [Tue, 17 Jul 2018 20:28:31 +0000 (20:28 +0000)]
[LangRef] Clarify which fast-math flags affect fcmp.
nsz has no effect due to the way fcmp is defined; +0 and -0 compare
equal anyway. reassoc could have the obvious effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337322
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Craig Topper [Tue, 17 Jul 2018 20:16:18 +0000 (20:16 +0000)]
[X86] Add patterns for folding full vector load into MOVHPS and MOVLPS with SSE1 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337320
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 17 Jul 2018 20:16:15 +0000 (20:16 +0000)]
[X86] Add test case for missed opportunity to use MOVLPS on the SSE1 only targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337319
91177308-0d34-0410-b5e6-
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Fangrui Song [Tue, 17 Jul 2018 19:50:41 +0000 (19:50 +0000)]
[Demangle] Add missing header files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337318
91177308-0d34-0410-b5e6-
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Zachary Turner [Tue, 17 Jul 2018 19:48:46 +0000 (19:48 +0000)]
Add missing include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337317
91177308-0d34-0410-b5e6-
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Zachary Turner [Tue, 17 Jul 2018 19:42:29 +0000 (19:42 +0000)]
Add some helper functions to the demangle utility classes.
These are all methods that, while not currently used in the
Itanium demangler, are generally useful enough that it's
likely the itanium demangler could find a use for them. More
importantly, they are all necessary for the Microsoft demangler
which is up and coming in a subsequent patch. Rather than
combine these into a single monolithic patch, I think it makes
sense to commit this utility code first since it is very simple,
this way it won't detract from the substance of the MS demangler
patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337316
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Vedant Kumar [Tue, 17 Jul 2018 18:08:36 +0000 (18:08 +0000)]
[InstCombine] Preserve debug value when simplifying cast-of-select
InstCombine has a cast transform that matches a cast-of-select:
Orig = cast (Src = select Cond TV FV)
And tries to replace it with a select which has the cast folded in:
NewSel = select Cond (cast TV) (cast FV)
The combiner does RAUW(Orig, NewSel), so any debug values for Orig would
survive the transform. But debug values for Src would be lost.
This patch teaches InstCombine to replace all debug uses of Src with
NewSel (taking care of doing any necessary DIExpression rewriting).
Differential Revision: https://reviews.llvm.org/D49270
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337310
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Vedant Kumar [Tue, 17 Jul 2018 18:08:34 +0000 (18:08 +0000)]
Remove an errant piece of !dbg metadata from a test, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337309
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Chandler Carruth [Tue, 17 Jul 2018 18:07:59 +0000 (18:07 +0000)]
[x86/SLH] Flesh out the data-invariant instruction table a bit based on feedback from Craig.
Summary:
The only thing he suggested that I've skipped here is the double-wide
multiply instructions. Multiply is an area I'm nervous about there being
some hidden data-dependent behavior, and it doesn't seem important for
any benchmarks I have, so skipping it and sticking with the minimal
multiply support that matches what I know is widely used in existing
crypto libraries. We can always add double-wide multiply when we have
clarity from vendors about its behavior and guarantees.
I've tried to at least cover the fundamentals here with tests, although
I've not tried to cover every width or permutation. I can add more tests
where folks think it would be helpful.
Reviewers: craig.topper
Subscribers: sanjoy, mcrosier, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D49413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337308
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Simon Pilgrim [Tue, 17 Jul 2018 17:47:35 +0000 (17:47 +0000)]
[llvm-mca][x86] Add extend, carry-flag and CMP instructions to general x86_64 resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337306
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Simon Pilgrim [Tue, 17 Jul 2018 17:41:45 +0000 (17:41 +0000)]
[llvm-mca][x86] Add MOVBE resource tests to all supporting targets
SNB doesn't support MOVBE but the numbers in Generic (which use the SNB model) look sane.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337305
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Florian Hahn [Tue, 17 Jul 2018 17:12:50 +0000 (17:12 +0000)]
Revert rL337292 due to another MSVC STL problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337303
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Simon Pilgrim [Tue, 17 Jul 2018 17:10:47 +0000 (17:10 +0000)]
[llvm-mca][x86] Add BSWAP resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337302
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Sam Clegg [Tue, 17 Jul 2018 16:40:03 +0000 (16:40 +0000)]
[WebAssembly] Update WebAssemblyLowerEmscriptenEHSjLj to handle separate compilation
Previously we were assuming whole program compilation. Now that
separate compilation is a thing we need to update this pass.
Firstly, it can no longer assert on the existence of malloc and free.
This functions might not be in the current translation unit. If we
need them then we will generate not imports for them.
Secondly the global helper function we create should be marked as
weak since we will be generating a separate copy in each translation
unit.
Finally the names of the symbols used must be unique and fixed since
they need to agree across translation units.
Differential Revision: https://reviews.llvm.org/D49263
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337301
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Craig Topper [Tue, 17 Jul 2018 16:24:33 +0000 (16:24 +0000)]
[X86] Remove some standalone patterns in favor of the patterns in the MOVLPD instruction definitions.
Previously we passed 'null_frag' into the instruction definition. The multiclass is shared with MOVHPD which doesn't use null_frag. It turns out by passing X86Movsd it produces patterns equivalent to some standalone patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337299
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Simon Pilgrim [Tue, 17 Jul 2018 16:17:33 +0000 (16:17 +0000)]
[llvm-mca][x86] Add displacement-only and additional scale=1 LEA tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337298
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Simon Pilgrim [Tue, 17 Jul 2018 16:13:29 +0000 (16:13 +0000)]
[llvm-mca][x86] Add LEA resource tests (PR32326)
Add llvm-mca tests demonstrating how LEA instructions are currently modelled. Once this is working on btver2 I'll copy the test file to the other target directories.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337297
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Matt Davis [Tue, 17 Jul 2018 16:11:54 +0000 (16:11 +0000)]
[llvm-mca][docs] Revert mca internals docs.
We're going to work on this in a separate review focusing more on documenting
the View and probably removing some of the less-interesting/less-useful pieces.
This reverts r337219,337225
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337295
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