OSDN Git Service
Momchil Velikov [Tue, 14 Nov 2017 10:36:52 +0000 (10:36 +0000)]
[ARM] Fix incorrect conversion of a tail call to an ordinary call
When we emit a tail call for Armv8-M, but then discover that the caller needs to
save/restore `LR`, we convert the tail call to an ordinary one, since restoring
`LR` takes extra instructions, which may negate the benefits of the tail
call. If the callee, however, takes stack arguments, this conversion is
incorrect, since nothing has been done to pass the stack arguments.
Thus the patch reverts https://reviews.llvm.org/rL294000
Also, we improve the instruction sequence for popping `LR` in the case when we
couldn't immediately find a scratch low register, but we can use as a temporary
one of the callee-saved low registers and restore `LR` before popping other
callee-saves.
Differential Revision: https://reviews.llvm.org/D39599
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318143
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Matt Arsenault [Tue, 14 Nov 2017 06:40:00 +0000 (06:40 +0000)]
AMDGPU: Fix test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318138
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Adam Nemet [Tue, 14 Nov 2017 04:48:18 +0000 (04:48 +0000)]
[opt-viewer] Truncate long remark text in source view
The table is changed to fixed layout[1] and the lines use ellipses if they
would overflow their cell.
[1] https://css-tricks.com/fixing-tables-long-strings/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318136
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Adam Nemet [Tue, 14 Nov 2017 04:37:32 +0000 (04:37 +0000)]
[opt-viewer] With hotness only show max 1000 entries on the index page
Adjustable with an option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318135
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Dylan McKay [Tue, 14 Nov 2017 04:32:49 +0000 (04:32 +0000)]
[AVR] Remove the select-mbb-placement-bug.ll test
This test was originally added when an old bug was fixed that caused
broken iterator code to break basic block placement.
The issue has an extremely low chance of every being a problem again.
This specific test is very flaky and fails often due to upstream
changes.
I have removed this test because it negates more value than it returns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318134
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Matt Arsenault [Tue, 14 Nov 2017 02:16:54 +0000 (02:16 +0000)]
AMDGPU: Fix producing saveexec when the copy is spilled
If the register from the copy from exec was spilled,
the copy before the spill was deleted leaving a spill
of undefined register verifier error and miscompiling.
Check for other use instructions of the copy register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318132
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Chandler Carruth [Tue, 14 Nov 2017 01:30:04 +0000 (01:30 +0000)]
[PM] Port BoundsChecking to the new PM.
Registers it and everything, updates all the references, etc.
Next patch will add support to Clang's `-fexperimental-new-pass-manager`
path to actually enable BoundsChecking correctly.
Differential Revision: https://reviews.llvm.org/D39084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318128
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Rafael Espindola [Tue, 14 Nov 2017 01:21:15 +0000 (01:21 +0000)]
Use TempFile in llvm-ar. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318127
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Chandler Carruth [Tue, 14 Nov 2017 01:13:59 +0000 (01:13 +0000)]
[PM] Refactor BoundsChecking further to prepare it to be exposed both as
a legacy and new PM pass.
This essentially moves the class state to parameters and re-shuffles the
code to make that reasonable. It also does some minor cleanups along the
way and leaves some comments.
Differential Revision: https://reviews.llvm.org/D39081
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318124
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Sam Clegg [Tue, 14 Nov 2017 00:49:16 +0000 (00:49 +0000)]
[WebAssembly] Explicily disable comdat support for wasm output
For now at least. We clearly need some kind of comdat or
linkonce_odr support for wasm but currently COMDAT is not
supported.
Disable COMDAT support in the same way we do the Mach-O. This
also causes clang not to generated COMDATs.
Differential Revision: https://reviews.llvm.org/D39873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318123
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Rafael Espindola [Tue, 14 Nov 2017 00:31:28 +0000 (00:31 +0000)]
Add a move assignment operator to TempFile. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318122
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Hans Wennborg [Mon, 13 Nov 2017 23:47:58 +0000 (23:47 +0000)]
Update some code.google.com links
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318115
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Zachary Turner [Mon, 13 Nov 2017 23:33:29 +0000 (23:33 +0000)]
Revert "Update test_debuginfo.pl script to point to new tree location."
This reverts the aforementioned patch and 2 subsequent follow-ups,
as some buildbots are still failing 2 tests because of it.
Investigation is ongoing into the cause of the failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318112
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Rafael Espindola [Mon, 13 Nov 2017 23:32:19 +0000 (23:32 +0000)]
Simplify and rename variable.
std::error_code can represent success, so we don't need a
Optional<std::error_code>.
Rename the variable to avoid confusion with the type Error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318111
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Matt Arsenault [Mon, 13 Nov 2017 23:24:26 +0000 (23:24 +0000)]
AMDGPU: Fix not converting d16 load/stores to offset
Fixes missed optimization with new MUBUF instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318106
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Rafael Espindola [Mon, 13 Nov 2017 23:06:54 +0000 (23:06 +0000)]
Simplify. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318104
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Daniel Sanders [Mon, 13 Nov 2017 23:03:47 +0000 (23:03 +0000)]
[tablegen] Handle atomic predicates for ordering inside tablegen. NFC.
Similar to r315841, GlobalISel and SelectionDAG require different code for the
common atomic predicates due to differences in the representation.
Even without that, differences in the IR (SDNode vs MachineInstr) require
differences in the C++ predicate.
This patch moves the implementation of the common atomic predicates related to
ordering into tablegen so that it can handle these differences.
It's NFC for SelectionDAG since it emits equivalent code and it's NFC for
GlobalISel since the rules involving the relevant predicates are still
rejected by the importer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318102
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Matt Arsenault [Mon, 13 Nov 2017 22:55:05 +0000 (22:55 +0000)]
AMDGPU: Implement computeKnownBitsForTargetNode for mbcnt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318100
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Daniel Sanders [Mon, 13 Nov 2017 22:26:13 +0000 (22:26 +0000)]
[tablegen] Handle atomic predicates for memory type inside tablegen. NFC.
Similar to r315841, GlobalISel and SelectionDAG require different code for the
common atomic predicates due to differences in the representation.
Even without that, differences in the IR (SDNode vs MachineInstr) require
differences in the C++ predicate.
This patch moves the implementation of the common atomic predicates related to
memory type into tablegen so that it can handle these differences.
It's NFC for SelectionDAG since it emits equivalent code and it's NFC for
GlobalISel since the rules involving the relevant predicates are still
rejected by the importer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318095
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Jake Ehrlich [Mon, 13 Nov 2017 22:13:08 +0000 (22:13 +0000)]
[llvm-objcopy] Add --strip-debug
Many projects use this option. There are two ways to use it. You can
either a) Just use --strip-debug and keep the old file with debug
content or b) you can use --strip-debug, --only-keep-debug, and
--add-gnu-debuglink all in conjunction to create two separate files, the
stripped file and the debug file. --only-keep-debug is more complicated
than --strip-debug because it keeps the section headers without keeping
section contents. That's not really supported by llvm-objcopy at the
moment but I plan on adding it. So this change just supports a) and
options to support b) will come soon.
Differential Revision: https://reviews.llvm.org/D39919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318094
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Jake Ehrlich [Mon, 13 Nov 2017 22:02:07 +0000 (22:02 +0000)]
[llvm-objcopy] Add --strip-all option to llvm-objcopy
This change adds a slightly less extreme form of stripping. It should
remove any section that starts with ".debug" and should remove any
symbol table or relocations. In general this strips out most of the
stuff you don't need to execute but leaves a number of things around.
This behavior has been designed to be compatible with GNU strip/objcopy
--strip-all so that anywhere you currently use --strip-all you should be
able to use llvm-objcopy as a drop in replacement.
Differential Revision: https://reviews.llvm.org/D39769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318092
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Serge Guelton [Mon, 13 Nov 2017 21:55:01 +0000 (21:55 +0000)]
Fix -Werror when compiling rL318083 (ter)
Statically assert the result and remove a runtime comparison, a direct consequence of the optimization introduced in rL318083.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318091
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Serge Guelton [Mon, 13 Nov 2017 21:40:57 +0000 (21:40 +0000)]
Fix -Werror when compiling rL318083 (bis)
Statically assert the result and remove a runtime comparison, a direct consequence of the optimization introduced in rL318083.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318090
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Serge Guelton [Mon, 13 Nov 2017 21:25:35 +0000 (21:25 +0000)]
Fix -Werror when compiling rL318083
Statically assert the result and remove a runtime comparison, a direct consequence of the optimization introduced in rL318083.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318087
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Adrian Prantl [Mon, 13 Nov 2017 21:24:54 +0000 (21:24 +0000)]
Fix an assertion in SelectionDAG::transferDbgValues()
when transferring debug info describing the lower bits of an extended SDNode.
rdar://problem/
35504722
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318086
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Serge Guelton [Mon, 13 Nov 2017 20:57:40 +0000 (20:57 +0000)]
Reorder Value.def to optimize code size
If the first values in Value.def is the range of constant, then the code
generated by `isa<Constant>` is smaller by one operation (basically, an add is
removed). It turns out this small optimization reduces the size of the
statically linked clang binary by 400ko on my laptop. The theoritical
performance gain is non visible from my benchmarks, but the size dropdown is.
Differential Revision: https://reviews.llvm.org/D39373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318083
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Evgeniy Stepanov [Mon, 13 Nov 2017 20:45:38 +0000 (20:45 +0000)]
[arm] Fix Unnecessary reloads from GOT.
Summary:
This fixes PR35221.
Use pseudo-instructions to let MachineCSE hoist global address computation.
Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D39871
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318081
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Sanjay Patel [Mon, 13 Nov 2017 19:46:28 +0000 (19:46 +0000)]
[Reassociation] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318076
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Reid Kleckner [Mon, 13 Nov 2017 18:43:11 +0000 (18:43 +0000)]
Fix clang -Wsometimes-uninitialized warning in SCEV code
I don't believe this was a problem in practice, as it's likely that the
boolean wasn't checked unless the backend condition was non-null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318073
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Dinar Temirbulatov [Mon, 13 Nov 2017 18:35:43 +0000 (18:35 +0000)]
NFC, Allow SystemZ SLP tests only when SystemZ is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318070
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Rafael Espindola [Mon, 13 Nov 2017 18:33:44 +0000 (18:33 +0000)]
Create a TempFile class.
This just adds a TempFile class and replaces the use in
FileOutputBuffer with it.
The only difference for now is better error handling. Followup work includes:
- Convert other user of temporary files to it.
- Add support for automatically deleting on windows.
- Add a createUnnamed method that returns a potentially unnamed
file. It would be actually unnamed on modern linux and have a
unknown name on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318069
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Daniel Sanders [Mon, 13 Nov 2017 18:30:23 +0000 (18:30 +0000)]
[globalisel][tablegen] Add support for extload.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318068
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Petar Jovanovic [Mon, 13 Nov 2017 18:00:24 +0000 (18:00 +0000)]
fix printing of alias instructions by removing redundant spacing
Some alias instructions are printed with an extra space after the tab
character. Fix this by skipping that space when the tab character is printed
so that the instructions are aligned with the rest of the code.
Patch by Milos Stojanovic.
Differential Revision: https://reviews.llvm.org/D35946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318059
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Sanjay Patel [Mon, 13 Nov 2017 17:56:23 +0000 (17:56 +0000)]
[ValueTracking] use 'auto' with 'dyn_cast'; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318058
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Craig Topper [Mon, 13 Nov 2017 17:53:59 +0000 (17:53 +0000)]
[X86] Allow X86ISD::Wrapper to be folded into the base of gather/scatter address
If the base of our gather corresponds to something contained in X86ISD::Wrapper we should be able to fold it into the address.
This patch refactors some of the address matching to more fully use the X86ISelAddressMode struct and the getAddressOperands helper. A new helper function matchVectorAddress is added to call matchWrapper or fall back to matchAddressBase.
We should also be able to support constant offsets from a wrapper, but I'll look into that in a future patch. We may even be able to completely reuse matchAddress here, but I wanted to start simple and work up to it.
Differential Revision: https://reviews.llvm.org/D39927
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318057
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Sanjay Patel [Mon, 13 Nov 2017 17:40:47 +0000 (17:40 +0000)]
[ValueTracking] simplify code in CannotBeNegativeZero() with match(); NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318055
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Sanjay Patel [Mon, 13 Nov 2017 17:29:11 +0000 (17:29 +0000)]
[Reassociate] add tests with 'reassoc' FMF; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318053
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Jan Vesely [Mon, 13 Nov 2017 16:46:07 +0000 (16:46 +0000)]
AMDGPU: Drop duplicate setOperationAction
These are set with other scalar int ops few lines up
Differential Revision: https://reviews.llvm.org/D39928
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318051
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Jatin Bhateja [Mon, 13 Nov 2017 16:43:24 +0000 (16:43 +0000)]
[SCEV] Handling for ICmp occuring in the evolution chain.
Summary:
If a compare instruction is same or inverse of the compare in the
branch of the loop latch, then return a constant evolution node.
This shall facilitate computations of loop exit counts in cases
where compare appears in the evolution chain of induction variables.
Will fix PR 34538
Reviewers: sanjoy, hfinkel, junryoungju
Reviewed By: sanjoy, junryoungju
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D38494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318050
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Simon Dardis [Mon, 13 Nov 2017 16:41:17 +0000 (16:41 +0000)]
Revert "[CodeGenPrepare] Check that erased sunken address are not reused"
This reverts commit r318032. The test broke some sanitizer bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318049
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Diana Picus [Mon, 13 Nov 2017 16:02:42 +0000 (16:02 +0000)]
[ARM GlobalISel] Update legalizer test
Make one of the legalizer tests a bit more robust by making sure all
values we're interested in are used (either in a store or a return) and
by using loads instead of constants for obtaining values on fewer than
32 bits. This should make the test less fragile to changes in the
legalize combiner, since those loads are legal (as opposed to the
constants, which were being widened and thus produced opportunities for
the legalize combiner).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318047
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Bill Seurer [Mon, 13 Nov 2017 15:43:19 +0000 (15:43 +0000)]
[PowerPC][msan] Update msan to handle changed memory layouts in newer kernels
In more recent Linux kernels (including those with 47 bit VMAs) the layout of
virtual memory for powerpc64 changed causing the memory sanitizer to not
work properly. This patch adjusts a bit mask in the memory sanitizer to work
on the newer kernels while continuing to work on the older ones as well.
This is the non-runtime part of the patch and finishes it. ref: r317802
Tested on several 4.x and 3.x kernel releases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318045
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Omer Paparo Bivas [Mon, 13 Nov 2017 15:02:39 +0000 (15:02 +0000)]
Inserting a base test for X86 performance nops
Change-Id: I69da08b617d7fae8024c5aee04720eb465f39b81
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318041
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Uriel Korach [Mon, 13 Nov 2017 12:51:18 +0000 (12:51 +0000)]
[X86] test/testn intrinsics lowering to IR. llvm part.
Remove builtins from llvm and add AutoUpgrade support.
Also add fast-isel tests for the TEST and TESTN instructions.
Differential Revision: https://reviews.llvm.org/D38736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318036
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Greg Bedwell [Mon, 13 Nov 2017 12:40:05 +0000 (12:40 +0000)]
Move the setting of LLVM_BUILD_MODE to a macro so that we can re-use it in compiler-rt
Differential Revision: https://reviews.llvm.org/D38470
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318034
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Momchil Velikov [Mon, 13 Nov 2017 11:56:48 +0000 (11:56 +0000)]
[ARM] Place jump table as the first operand in additions
When generating table jump code for switch statements, place the jump
table label as the first operand in the various addition instructions
in order to enable addressing mode selectors to better match index
computation and possibly fold them into the addressing mode of the
table entry load instruction.
Differential revision: https://reviews.llvm.org/D39752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318033
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Simon Dardis [Mon, 13 Nov 2017 11:47:21 +0000 (11:47 +0000)]
[CodeGenPrepare] Check that erased sunken address are not reused
CodeGenPrepare sinks address computations from one basic block to another
and attempts to reuse address computations that have already been sunk. If
the same address computation appears twice with the first instance as an
operand of a load whose result is an operand to a simplifable select,
CodeGenPrepare simplifies the select and recursively erases the now dead
instructions. CodeGenPrepare then attempts to use the erased address
computation for the second load.
Fix this by erasing the cached address value if it has zero uses before
looking for the address value in the sunken address map.
This partially resolves PR35209.
Thanks to Alexander Richardson for reporting the issue!
Reviewers: john.brawn
Differential Revision: https://reviews.llvm.org/D39841
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318032
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Florian Hahn [Mon, 13 Nov 2017 11:08:47 +0000 (11:08 +0000)]
[CodeExtractor] Add missing AllowVarArgs initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318029
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Florian Hahn [Mon, 13 Nov 2017 10:35:52 +0000 (10:35 +0000)]
[PartialInliner] Inline vararg functions that forward varargs.
Summary:
This patch extends the partial inliner to support inlining parts of
vararg functions, if the vararg handling is done in the outlined part.
It adds a `ForwardVarArgsTo` argument to InlineFunction. If it is
non-null, all varargs passed to the inlined function will be added to
all calls to `ForwardVarArgsTo`.
The partial inliner takes care to only pass `ForwardVarArgsTo` if the
varargs handing is done in the outlined function. It checks that vastart
is not part of the function to be inlined.
`test/Transforms/CodeExtractor/PartialInlineNoInline.ll` (already part
of the repo) checks we do not do partial inlining if vastart is used in
a basic block that will be inlined.
Reviewers: davide, davidxl, grosser
Reviewed By: davide, davidxl, grosser
Subscribers: gyiu, grosser, eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D39607
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318028
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Sander de Smalen [Mon, 13 Nov 2017 09:57:20 +0000 (09:57 +0000)]
Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318027
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Jina Nahias [Mon, 13 Nov 2017 09:16:39 +0000 (09:16 +0000)]
[x86][AVX512] Lowering shuffle i/f intrinsics to LLVM IR
This patch, together with a matching clang patch (https://reviews.llvm.org/D38672), implements the lowering of X86 shuffle i/f intrinsics to IR.
Differential Revision: https://reviews.llvm.org/D38671
Change-Id: I1e7d359a74743e995ec356237a85214ce55d3661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318026
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Gadi Haber [Mon, 13 Nov 2017 08:42:07 +0000 (08:42 +0000)]
[X86][SKX] Adding scheduling info of non-intrinsic + commutable SKX opcodes.
Updated the scheduling information of the SKX subtarget in the file X86SchedSkylakeServer.td under lib/Target/X86 to:
1. add regular opcodes in addition to the suffixed "_Int" opcodes
2. add the (V)MAXCPD/MAXCPS/MAXCSD/MAXCSS/MINCPD/MINCPS/MINCSD/MINCSS
instructions that are equivalent to their counterparts without the 'C' as they are part of a hack to
make floating point min/max commutable under fast math.
Reviewers: zvi, RKSimon, craig.topper
Differential Revision: https://reviews.llvm.org/D39833
Change-Id: Ie13702a5ce1b1a08af91ca637a52b6962881e7d6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318024
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Craig Topper [Mon, 13 Nov 2017 08:17:30 +0000 (08:17 +0000)]
[X86] Limit NOPs to 7 bytes when 'slm' is spelled 'silvermont'.
We support 2 spelling for silvermont and we should accept both here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318023
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Craig Topper [Mon, 13 Nov 2017 08:07:33 +0000 (08:07 +0000)]
[X86] Use sse_load_f32/f64 to improve load folding of scalar vfscalefss/sd, vrcp14ss/sd, rsqrt14ss/sd instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318022
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Craig Topper [Mon, 13 Nov 2017 08:07:31 +0000 (08:07 +0000)]
[X86] Regenerate test. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318021
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Matt Arsenault [Mon, 13 Nov 2017 07:09:20 +0000 (07:09 +0000)]
MI: Print ranges on MMO
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318020
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Craig Topper [Mon, 13 Nov 2017 06:46:48 +0000 (06:46 +0000)]
[X86] Use sse_load_f32/f64 to improve load folding for scalar VFPCLASS intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318019
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Craig Topper [Mon, 13 Nov 2017 06:46:46 +0000 (06:46 +0000)]
[X86] Add tests for missed opportunities to fold a 128-bit vector load into vfpclassss and vpfpclasssd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318018
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Matt Arsenault [Mon, 13 Nov 2017 05:33:35 +0000 (05:33 +0000)]
AMDGPU: Preserve nuw in shl add ptr combine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318017
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Craig Topper [Mon, 13 Nov 2017 05:25:24 +0000 (05:25 +0000)]
[X86] Fix SQRTSS/SQRTSD/RCPSS/RCPSD intrinsics to use sse_load_f32/sse_load_f64 to increase load folding opportunities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318016
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Craig Topper [Mon, 13 Nov 2017 05:25:23 +0000 (05:25 +0000)]
[X86] Add tests for full vector loads to fold-load-unops.ll.
We should be able to fold a full vector load into a scalar intrinsic. Since it's legal to narrow a load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318015
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Craig Topper [Mon, 13 Nov 2017 05:25:21 +0000 (05:25 +0000)]
[X86] Regenerate fold-load-unops.ll and add and avx512f command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318014
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Matt Arsenault [Mon, 13 Nov 2017 05:11:54 +0000 (05:11 +0000)]
AMDGPU: Fix multi-use shl/add combine
This was using a custom function that didn't handle the
addressing modes properly for private. Use
isLegalAddressingMode to avoid duplicating this.
Additionally, skip the combine if there is only one use
since the standard combine will handle it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318013
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Craig Topper [Mon, 13 Nov 2017 02:19:13 +0000 (02:19 +0000)]
[X86] Attempt to fix signed and unsigned comparison warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318010
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Craig Topper [Mon, 13 Nov 2017 02:03:01 +0000 (02:03 +0000)]
[X86] Use sse_load_f32/f64 in patterns for the memory forms of VRNDSCALESS/SD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318009
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Craig Topper [Mon, 13 Nov 2017 02:03:00 +0000 (02:03 +0000)]
[X86] Use EVEX encoded VRNDSCALE instructions to implement the legacy round intrinsics.
The VRNDSCALE instructions implement a superset of the (V)ROUND instructions. They are equivalent if the upper 4-bits of the immediate are 0.
This patch lowers the legacy intrinsics to the VRNDSCALE ISD node and masks the upper bits of the immediate to 0. This allows us to take advantage of the larger register encoding space.
We should maybe consider converting VRNDSCALE back to VROUND in the EVEX to VEX pass if the extended registers are not being used.
I notice some load folding opportunities being missed for the VRNDSCALESS/SD instructions that I'll try to fix in future patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318008
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Craig Topper [Mon, 13 Nov 2017 02:02:58 +0000 (02:02 +0000)]
[X86] Split VRNDSCALE/VREDUCE/VGETMANT/VRANGE ISD nodes into versions with and without the rounding operand. NFCI
I want to reuse the VRNDSCALE node for the legacy SSE rounding intrinsics so that those intrinsics can use EVEX instructions. All of these nodes share tablegen multiclasses so I split them all so that they all remain similar in their implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318007
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Matt Arsenault [Mon, 13 Nov 2017 01:47:52 +0000 (01:47 +0000)]
Fix some misc. -enable-var-scope violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318006
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Matt Arsenault [Mon, 13 Nov 2017 00:22:09 +0000 (00:22 +0000)]
AMDGPU: Select d16 loads into low component of register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318005
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Matt Arsenault [Sun, 12 Nov 2017 23:53:44 +0000 (23:53 +0000)]
AMDGPU: Fix -enable-var-scope violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318004
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Matt Arsenault [Sun, 12 Nov 2017 23:40:12 +0000 (23:40 +0000)]
AMDGPU: Fix missing gfx9 atomic inc/dec tests
The global instructions weren't tested. Plus there
were also some -enable-var-scope violations and
broken check prefixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318003
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Craig Topper [Sun, 12 Nov 2017 18:51:09 +0000 (18:51 +0000)]
[X86] Add an X86ISD::RANGES opcode to use for the scalar intrinsics.
This fixes a bug where we selected packed instructions for scalar intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317999
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Craig Topper [Sun, 12 Nov 2017 18:51:08 +0000 (18:51 +0000)]
[X86] Add test cases and command lines demonstrating how we accidentally select vrangeps/vrangepd from vrangess/vrangesd instrinsics when the rounding mode is CUR_DIRECTION
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317998
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Craig Topper [Sun, 12 Nov 2017 18:51:06 +0000 (18:51 +0000)]
[X86] Remove some no longer needed intrinsic lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317997
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Mandeep Singh Grang [Sun, 12 Nov 2017 03:47:50 +0000 (03:47 +0000)]
[llvm] Remove redundant return [NFC]
Reviewers: davidxl, olista01, Eugene.Zelenko
Reviewed By: Eugene.Zelenko
Subscribers: sdardis, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D39917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317995
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Craig Topper [Sun, 12 Nov 2017 02:28:21 +0000 (02:28 +0000)]
[InstCombine] Teach visitICmpInst to not break integer absolute value idioms
Summary:
This patch adds an early out to visitICmpInst if we are looking at a compare as part of an integer absolute value idiom. Similar is already done for min/max.
In the particular case I observed in a benchmark we had an absolute value of a load from an indexed global. We simplified the compare using foldCmpLoadFromIndexedGlobal into a magic bit vector, a shift, and an and. But the load result was still used for the select and the negate part of the absolute valute idiom. So we overcomplicated the code and lost the ability to recognize it as an absolute value.
I've chosen a simpler case for the test here.
Reviewers: spatel, davide, majnemer
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39766
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317994
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Craig Topper [Sat, 11 Nov 2017 21:44:51 +0000 (21:44 +0000)]
[X86] Use vrndscaleps/pd for 128/256 ffloor/ftrunc/fceil/fnearbyint/frint when avx512vl is enabled.
This matches what we do for scalar and 512-bit types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317991
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Craig Topper [Sat, 11 Nov 2017 21:44:50 +0000 (21:44 +0000)]
[X86] Remove avx512-round.ll. The 512-bit rounding tests are now in vec_floor.ll with 128/256 sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317990
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Craig Topper [Sat, 11 Nov 2017 21:44:49 +0000 (21:44 +0000)]
[X86] Add avx512vl command line to vec_floor.ll. Add 512-bit test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317989
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Craig Topper [Sat, 11 Nov 2017 21:44:48 +0000 (21:44 +0000)]
[X86] Add avx512f command line to rounding-ops.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317988
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Craig Topper [Sat, 11 Nov 2017 21:44:47 +0000 (21:44 +0000)]
[X86] Regenerate rounding-ops.ll with update_llc_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317987
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Simon Pilgrim [Sat, 11 Nov 2017 18:16:55 +0000 (18:16 +0000)]
[X86] Attempt to match multiple binary reduction ops at once. NFCI
matchBinOpReduction currently matches against a single opcode, but we already have a case where we repeat calls to try to match against AND/OR and I'll be shortly adding another case for SMAX/SMIN/UMAX/UMIN (D39729).
This NFCI patch alters matchBinOpReduction to try and pattern match against any of the provided list of candidate bin ops at once to save time.
Differential Revision: https://reviews.llvm.org/D39726
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317985
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Craig Topper [Sat, 11 Nov 2017 08:24:15 +0000 (08:24 +0000)]
[X86] Add scalar register class versions of VRNDSCALE instructions and rename the existing versions to _Int.
This is consistent with out normal implementation of scalar instructions.
While there disable load folding for the patterns with IMPLICIT_DEF unless optimizing for size which is also our standard practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317977
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Craig Topper [Sat, 11 Nov 2017 08:24:13 +0000 (08:24 +0000)]
[X86] Regenerate avx512-round.ll test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317976
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Craig Topper [Sat, 11 Nov 2017 08:24:12 +0000 (08:24 +0000)]
[X86] Inline some SDNode operand multiclass operands that don't vary. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317975
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Craig Topper [Sat, 11 Nov 2017 06:57:44 +0000 (06:57 +0000)]
[X86] Set the execution domain for VFPCLASS to SSEPackedSingle/Double.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317974
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Craig Topper [Sat, 11 Nov 2017 06:19:12 +0000 (06:19 +0000)]
[X86] Set the execution domain for vptest instruction to the integer domain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317973
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Daniel Sanders [Sat, 11 Nov 2017 03:23:44 +0000 (03:23 +0000)]
[globalisel][tablegen] Import signextload and zeroextload.
Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to
correct situations where SelectionDAG and GlobalISel disagree on
representation. For example, it would rewrite:
(sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16>
to:
(sext:i32 (load:i16 $ptr)<<unindexedload>>)
I'd have preferred to replace the fragments and have the expansion happen
naturally as part of PatFrag expansion but the type inferencing system can't
cope with loads of types narrower than those mentioned in register classes.
This is because the SDTCisInt's on the sext constrain both the result and
operand to the 'legal' integer types (where legal is defined as 'a register
class can contain the type') which immediately rules the narrower types out.
Several targets (those with only one legal integer type) would then go on to
crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types
for the result of the extend.
Also, improve isObviouslySafeToFold() slightly to automatically return true for
neighbouring instructions. There can't be any re-ordering problems if
re-ordering isn't happenning. We'll need to improve it further to handle
sign/zero-extending loads when the extend and load aren't immediate neighbours
though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317971
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Craig Topper [Sat, 11 Nov 2017 02:26:05 +0000 (02:26 +0000)]
[X86] Correct the execution domain on ROUND/VROUND instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317968
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Craig Topper [Sat, 11 Nov 2017 02:26:02 +0000 (02:26 +0000)]
[X86] Remove the default for one of the arguments to some tablegen multiclasses. NFC
No one ever uses this default and probably shouldn't since it sets the execution domain to generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317967
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NAKAMURA Takumi [Sat, 11 Nov 2017 02:05:47 +0000 (02:05 +0000)]
llvm/Support/TargetParser.h: Fix -fmodules build in rL317900.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317966
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Tony Tye [Sat, 11 Nov 2017 00:50:32 +0000 (00:50 +0000)]
[AMDGPU] Correct targets that support XNACK
Differential Revision: https://reviews.llvm.org/D39887
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317955
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Craig Topper [Fri, 10 Nov 2017 23:36:56 +0000 (23:36 +0000)]
[SelectionDAG] Make getUniformBase in SelectionDAGBuilder fail if any of the middle GEP indices are non-constant.
This is a fix for a bug in r317947. We were supposed to check that all the indices are are constant 0, but instead we're only make sure that indices that are constant are 0. Non-constant indices are being ignored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317950
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Zachary Turner [Fri, 10 Nov 2017 23:13:14 +0000 (23:13 +0000)]
Update test_debuginfo.pl script to point to new tree location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317949
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Craig Topper [Fri, 10 Nov 2017 22:50:50 +0000 (22:50 +0000)]
[SelectionDAG] Teach SelectionDAGBuilder's getUniformBase for gather/scatter handling to accept GEPs with more than 2 operands if the middle operands are all 0s
Currently we can only get a uniform base from a simple GEP with 2 operands. This causes us to miss address folding opportunities for simple global array accesses as the test case shows.
This patch adds support for larger GEPs if the other indices are 0 since those don't require any additional computations to be inserted.
We may also want to handle constant splats of zero here, but I'm leaving that for future work when I have a real world example.
Differential Revision: https://reviews.llvm.org/D39911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317947
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Evgeniy Stepanov [Fri, 10 Nov 2017 22:27:48 +0000 (22:27 +0000)]
[asan] Use dynamic shadow on 32-bit Android.
Summary:
The following kernel change has moved ET_DYN base to 0x4000000 on arm32:
https://marc.info/?l=linux-kernel&m=
149825162606848&w=2
Switch to dynamic shadow base to avoid such conflicts in the future.
Reserve shadow memory in an ifunc resolver, but don't use it in the instrumentation
until PR35221 is fixed. This will eventually let use save one load per function.
Reviewers: kcc
Subscribers: aemerson, srhines, kubamracek, kristof.beyls, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D39393
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317943
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Martin Storsjo [Fri, 10 Nov 2017 22:27:41 +0000 (22:27 +0000)]
[llvm-cvtres] Add support for ARM64
Also change some default cases into llvm_unreachable in
WindowsResourceCOFFWriter, to make it easier to find if they
are triggerd from within e.g. lld, which supported ARM64 earlier
than llvm-cvtres did.
Differential Revision: https://reviews.llvm.org/D39892
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317942
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Mitch Phillips [Fri, 10 Nov 2017 21:00:22 +0000 (21:00 +0000)]
[cfi-verify] Made FileAnalysis operate on a GraphResult rather than build one and validate it.
Refactors the behaviour of building graphs out of FileAnalysis, allowing for analysis of the GraphResult by the callee without having to rebuild the graph. Means when we want to analyse the constructed graph (planned for later revisions), we don't do repeated work.
Also makes CFI verification in FileAnalysis now return an enum that allows us to differentiate why something failed, not just that it did/didn't fail.
Reviewers: vlad.tsyrklevich
Subscribers: kcc, pcc, llvm-commits
Differential Revision: https://reviews.llvm.org/D39764
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317927
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Amaury Sechet [Fri, 10 Nov 2017 20:59:53 +0000 (20:59 +0000)]
[DAGcombine] Do not replace truncate node by itself when doing constant folding, this trigger needless extra rounds of combine for nothing. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317926
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Zachary Turner [Fri, 10 Nov 2017 20:57:57 +0000 (20:57 +0000)]
[debuginfo-tests] Make debuginfo-tests work in a standard configuration.
Previously, debuginfo-tests was expected to be checked out into
clang/test and then the tests would automatically run as part of
check-clang. This is not a standard workflow for handling
external projects, and it brings with it some serious drawbacks
such as the inability to depend on things other than clang, which
we will need going forward.
The goal of this patch is to migrate towards a more standard
workflow. To ease the transition for build bot maintainers,
this patch tries not to break the existing workflow, but instead
simply deprecate it to give maintainers a chance to update
the build infrastructure.
Differential Revision: https://reviews.llvm.org/D39605
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317925
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