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Craig Topper [Tue, 25 Jun 2019 01:32:42 +0000 (01:32 +0000)]
Revert r363802, r363850, and r363856 "[TargetLowering] SimplifyDemandedBits..."
This reverts the following patches.
"[TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_INREG -> ANY/ZERO_EXTEND_VECTOR_INREG"
"[TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_VECTOR_INREG"
"[TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG support"
We can end up with an any_extend_vector_inreg with a 256 bit result type
and a 128 bit result type. This is allowed by the ISD opcode, but the
generic operation legalizer is only able to expand cases where the
total vector width is the same.
The X86 backend creates these mismatched cases for zext_vec_inreg/sext_vec_inreg.
The SimplifyDemandedBits changes are allowing those nodes to become
aext_vec_inreg. For the zext/sext cases, the X86 backend has Custom
handling and never lets them get to the generic legalizer. We need to do the same
for aext_vec_inreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364264
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Seiya Nuta [Tue, 25 Jun 2019 01:08:21 +0000 (01:08 +0000)]
[llvm-objcopy][NFCI] Fix build failure with GCC
Here is unreachable since the switch statement above is exhaustive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364263
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Matt Arsenault [Tue, 25 Jun 2019 01:07:22 +0000 (01:07 +0000)]
AMDGPU/GlobalISel: Fix regbankselect for amdgcn.class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364262
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Huihui Zhang [Tue, 25 Jun 2019 00:14:02 +0000 (00:14 +0000)]
[InstCombine][NFC] Add test to show missing fold for icmp ult/uge (shl %x, C2), C1.
Summary:
'shl' inequality test
```
icmp ult/uge (shl %x, C2), C1 iff C1 is power of two
```
can be simplified as 'and' equality test
```
icmp eq/ne (and %x, (lshr -C1, C2)), 0.
```
Reviewers: lebedev.ri, efriedma
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63670
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364256
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Huihui Zhang [Tue, 25 Jun 2019 00:09:10 +0000 (00:09 +0000)]
[InstCombine] Fold icmp eq/ne (and %x, C), 0 iff (-C) is power of two -> %x u</u>= (-C) earlier.
Summary:
To generate simplified IR, make sure fold
(X & ~C) ==/!= 0 --> X u</u>= C+1
is scheduled before fold
((X << Y) & C) == 0 -> (X & (C >> Y)) == 0.
https://rise4fun.com/Alive/7ZN
Reviewers: lebedev.ri, efriedma, spatel, craig.topper
Reviewed By: lebedev.ri
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364255
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Seiya Nuta [Tue, 25 Jun 2019 00:02:04 +0000 (00:02 +0000)]
[llvm-objcopy][NFC] Refactor output target parsing
Summary:
Use an enum instead of string to hold the output file format in Config.InputFormat and Config.OutputFormat. It's essential to support other output file formats other than ELF.
Reviewers: espindola, alexshap, rupprecht, jhenderson
Reviewed By: rupprecht, jhenderson
Subscribers: jyknight, compnerd, emaste, arichardson, fedor.sergeev, jakehehrlich, MaskRay, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63239
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364254
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David Blaikie [Mon, 24 Jun 2019 23:45:18 +0000 (23:45 +0000)]
DataExtractor: use decodeSLEB128 to implement getSLEB128
Should've been NFC, but turns out DataExtractor had better test coverage
for decoding SLEB128 than the decodeSLEB128 did - revealing a couple of
bugs (one in the error handling, another in sign extension). So fixed
those to get the DataExtractor tests passing again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364253
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Seiya Nuta [Mon, 24 Jun 2019 23:39:01 +0000 (23:39 +0000)]
[llvm-objcopy][MachO] Fix strict-aliasing warning. NFCI
Summary:
Use MachOObjectFile::isRelocationScattered instead of reinterpret_cast.
Fixes https://bugs.llvm.org/show_bug.cgi?id=42360
Reviewers: alexshap, rupprecht, jhenderson
Reviewed By: alexshap
Subscribers: dendibakh, bjope, uabelho, jakehehrlich, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364252
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Tim Shen [Mon, 24 Jun 2019 23:29:20 +0000 (23:29 +0000)]
Revert "[NVPTX][NFC] Fix documentation for shfl instructions." The
original documentation is correct as it matches the C++ builtins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364250
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Douglas Yung [Mon, 24 Jun 2019 23:16:32 +0000 (23:16 +0000)]
[NFC] Fix tests added in r364225 which failed on Windows due to incorrect path separators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364249
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Tim Shen [Mon, 24 Jun 2019 23:16:32 +0000 (23:16 +0000)]
[NVPTX][NFC] Fix documentation for shfl instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364248
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Vitaly Buka [Mon, 24 Jun 2019 22:42:53 +0000 (22:42 +0000)]
[NFC] Add missing consts into memoryaccess_def_iterator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364247
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Sanjay Patel [Mon, 24 Jun 2019 22:35:26 +0000 (22:35 +0000)]
[InstCombine] squash is-not-power-of-2 using ctpop
This is the Demorgan'd 'not' of the pattern handled in:
D63660 / rL364153
This is another intermediate IR step towards solving PR42314:
https://bugs.llvm.org/show_bug.cgi?id=42314
We can test if a value is not a power-of-2 using ctpop(X) > 1,
so combining that with an is-zero check of the input is the
same as testing if not exactly 1 bit is set:
(X == 0) || (ctpop(X) u> 1) --> ctpop(X) != 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364246
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Matt Arsenault [Mon, 24 Jun 2019 22:21:02 +0000 (22:21 +0000)]
AMDGPU/GlobalISel: Add tests for regbankselect of v2s16 and/or/xor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364244
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Vasileios Porpodas [Mon, 24 Jun 2019 21:40:48 +0000 (21:40 +0000)]
[SLP] NFC: Fixed typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364237
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Matt Arsenault [Mon, 24 Jun 2019 21:37:03 +0000 (21:37 +0000)]
InstCombine: Preserve nuw when reassociating nuw ops [3/3]
Alive says this is OK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364235
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Matt Arsenault [Mon, 24 Jun 2019 21:37:02 +0000 (21:37 +0000)]
InstCombine: Preserve nuw when reassociating nuw ops [2/3]
Alive says this is OK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364234
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Matt Arsenault [Mon, 24 Jun 2019 21:36:59 +0000 (21:36 +0000)]
InstCombine: Preserve nuw when reassociating nuw ops [1/3]
Alive says this is OK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364233
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Cameron McInally [Mon, 24 Jun 2019 21:36:09 +0000 (21:36 +0000)]
[NFC][Reassociate] Add unary FNeg tests to fast-ReassociateVector.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364232
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David Blaikie [Mon, 24 Jun 2019 20:43:36 +0000 (20:43 +0000)]
NFC: DataExtractor: use decodeULEB128 to implement getULEB128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364230
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Nikita Popov [Mon, 24 Jun 2019 20:13:13 +0000 (20:13 +0000)]
[CVP] Reenable nowrap flag inference
Inference of nowrap flags in CVP has been disabled, because it
triggered a bug in LFTR (https://bugs.llvm.org/show_bug.cgi?id=31181).
This issue has been fixed in D60935, so we should be able to reenable
nowrap flag inference now.
Differential Revision: https://reviews.llvm.org/D62776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364228
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Sanjay Patel [Mon, 24 Jun 2019 20:11:40 +0000 (20:11 +0000)]
[InstCombine] add tests for more variants of isPowerOf2; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364227
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Peter Collingbourne [Mon, 24 Jun 2019 20:03:23 +0000 (20:03 +0000)]
llvm-symbolizer: Add a FRAME command.
This command prints a description of the referenced function's stack frame.
For each formal parameter and local variable, the tool prints:
- function name
- variable name
- file/line of declaration
- FP-relative variable location (if available)
- size in bytes
- HWASAN tag offset
This information will be used by the HWASAN runtime to identify local
variables in UAR reports.
Differential Revision: https://reviews.llvm.org/D63468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364225
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Huihui Zhang [Mon, 24 Jun 2019 19:49:42 +0000 (19:49 +0000)]
[InstCombine] Regenerate test pr17827. NFCI.
Prep work for upcoming patch D63505.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364224
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Roland Froese [Mon, 24 Jun 2019 19:27:07 +0000 (19:27 +0000)]
[CodeGen] Add missing vector type legalization for ctlz_zero_undef
Widen vector result type for ctlz_zero_undef and cttz_zero_undef the same as
ctlz and cttz.
Differential Revision: https://reviews.llvm.org/D63463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364221
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Philip Reames [Mon, 24 Jun 2019 19:26:17 +0000 (19:26 +0000)]
[Tests] Add cases where we're failing to discharge provably loop exits (tests for D63733)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364220
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Cameron McInally [Mon, 24 Jun 2019 19:24:23 +0000 (19:24 +0000)]
[SLP] Support unary FNeg vectorization
Differential Revision: https://reviews.llvm.org/D63609
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364219
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Nico Weber [Mon, 24 Jun 2019 18:47:53 +0000 (18:47 +0000)]
Remove flag for no longer supported MSVC version
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364218
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Matt Arsenault [Mon, 24 Jun 2019 18:02:18 +0000 (18:02 +0000)]
AMDGPU/GlobalISel: Select G_TRUNC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364215
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Matt Arsenault [Mon, 24 Jun 2019 18:00:47 +0000 (18:00 +0000)]
AMDGPU/GlobalISel: RegBankSelect for amdgcn.class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364214
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Jinsong Ji [Mon, 24 Jun 2019 18:00:34 +0000 (18:00 +0000)]
[PowerPC][UpdateTestChecks] powerpc- triple support
There are quite some old testcases with powerpc- triple,
we should add this triple support so that we can update them with script.
Differential Revision: https://reviews.llvm.org/D63723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364213
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Matt Arsenault [Mon, 24 Jun 2019 17:54:12 +0000 (17:54 +0000)]
AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect
Scalar extends to s64 can use S_BFE_{I64|U64}, but vector extends need
to extend to the 32-bit half, and then to 64.
I'm not sure what the line should be between what RegBankSelect
handles, and what instruction select does, but for now I'm erring on
the side of RegBankSelect for future post-RBS combines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364212
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Yuanfang Chen [Mon, 24 Jun 2019 17:47:56 +0000 (17:47 +0000)]
[llvm-objdump] Match GNU objdump on symbol types shown in disassembly
output.
STT_OBJECT and STT_COMMON are dumped as data, not disassembled.
https://bugs.llvm.org/show_bug.cgi?id=41947
Differential Revision: https://reviews.llvm.org/D62964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364211
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Tim Renouf [Mon, 24 Jun 2019 17:35:20 +0000 (17:35 +0000)]
[AMDGPU] Allow any value in unused src0 field in v_nop
Summary:
The LLVM disassembler assumes that the unused src0 operand of v_nop is
zero. Other tools can put another value in that field, which is still
valid. This commit fixes the LLVM disassembler to recognize such an
encoding as v_nop, in the same way as we already do for s_getpc.
Differential Revision: https://reviews.llvm.org/D63724
Change-Id: Iaf0363eae26ff92fc4ebc716216476adbff37a6f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364208
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Craig Topper [Mon, 24 Jun 2019 17:28:41 +0000 (17:28 +0000)]
[X86] Don't a vzext_movl in LowerBuildVectorv16i8/LowerBuildVectorv8i16 if there are no zeroes in the vector we're building.
In LowerBuildVectorv16i8 we took care to use an any_extend if the first pair is in the lower 16-bits of the vector and no elements are 0. So bits [31:16] will be undefined. But we still emitted a vzext_movl to ensure that bits [127:32] are 0. If we don't need any zeroes we should be consistent and make all of 127:16 undefined.
In LowerBuildVectorv8i16 we can just delete the vzext_movl code because we only use the scalar_to_vector when there are no zeroes. So the vzext_movl is always unnecessary.
Found while investigating whether (vzext_movl (scalar_to_vector (loadi32)) patterns are necessary. At least one of the cases where they were necessary was where the loadi32 matched 32-bit aligned 16-bit extload. Seemed weird that we required vzext_movl for that case.
Differential Revision: https://reviews.llvm.org/D63700
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364207
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Craig Topper [Mon, 24 Jun 2019 17:28:26 +0000 (17:28 +0000)]
[X86] Cleanups and safety checks around the isFNEG
This patch does a few things to start cleaning up the isFNEG function.
-Remove the Op0/Op1 peekThroughBitcast calls that seem unnecessary. getTargetConstantBitsFromNode has its own peekThroughBitcast inside. And we have a separate peekThroughBitcast on the return value.
-Add a check of the scalar size after the first peekThroughBitcast to ensure we haven't changed the element size and just did something like f32->i32 or f64->i64.
-Remove an unnecessary check that Op1's type is floating point after the peekThroughBitcast. We're just going to look for a bit pattern from a constant. We don't care about its type.
-Add VT checks on several places that consume the return value of isFNEG. Due to the peekThroughBitcasts inside, the type of the return value isn't guaranteed. So its not safe to use it to build other nodes without ensuring the type matches the type being used to build the node. We might be able to replace these checks with bitcasts instead, but I don't have a test case so a bail out check seemed better for now.
Differential Revision: https://reviews.llvm.org/D63683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364206
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Simon Pilgrim [Mon, 24 Jun 2019 17:18:20 +0000 (17:18 +0000)]
[AArch64] Regenerate vcvt tests. NFCI.
Prep work for an upcoming patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364205
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Simon Pilgrim [Mon, 24 Jun 2019 16:58:19 +0000 (16:58 +0000)]
[AArch64] Regenerate 2velem tests. NFCI.
Prep work for an upcoming patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364204
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Simon Pilgrim [Mon, 24 Jun 2019 16:57:12 +0000 (16:57 +0000)]
[AArch64] Regenerate merge-store tests. NFCI.
Prep work for an upcoming patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364203
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Simon Pilgrim [Mon, 24 Jun 2019 16:25:30 +0000 (16:25 +0000)]
[X86] Regenerate fast fadd reduction tests. NFCI
Fix whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364200
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Matt Arsenault [Mon, 24 Jun 2019 16:24:03 +0000 (16:24 +0000)]
AMDGPU/GlobalISel: Fix selecting G_IMPLICIT_DEF for s1
Try to fail for scc, since I don't think that should ever be produced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364199
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Ayke van Laethem [Mon, 24 Jun 2019 16:23:17 +0000 (16:23 +0000)]
[bindings/go] Add debug information accessors
Add debug information accessors, as provided in the following patches:
https://reviews.llvm.org/D46627 (DILocation)
https://reviews.llvm.org/D52693 metadata kind
https://reviews.llvm.org/D60481 get/set debug location on a Value
https://reviews.llvm.org/D60489 (DIScope)
The API as proposed in this patch is similar to the current Value API,
with a single root type and methods that are only valid for certain
subclasses. I have considered just implementing generic Line() calls
(that are valid on all DINodes that have a line) but the implementation
of that got a bit awkward without support from the C API. I've also
considered creating generic getters like a Metadata.DebugLoc() that
returns a DebugLoc, but there is a mismatch between the Go DI nodes in
the LLVM API and the actual DINode class hierarchy, so that's also hard
to get right (without being confusing or breaking the API).
Differential Revision: https://reviews.llvm.org/D63056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364198
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Matt Arsenault [Mon, 24 Jun 2019 16:16:19 +0000 (16:16 +0000)]
Hexagon: Rename another copy of Register class
For some reason clang is happy with the conflict, but MSVC is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364196
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Matt Arsenault [Mon, 24 Jun 2019 16:16:16 +0000 (16:16 +0000)]
ARC: Fix -Wimplicit-fallthrough
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364195
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Matt Arsenault [Mon, 24 Jun 2019 16:16:12 +0000 (16:16 +0000)]
GlobalISel: Remove unsigned variant of SrcOp
Force using Register.
One downside is the generated register enums require explicit
conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364194
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Matt Arsenault [Mon, 24 Jun 2019 15:50:29 +0000 (15:50 +0000)]
CodeGen: Introduce a class for registers
Avoids using a plain unsigned for registers throughoug codegen.
Doesn't attempt to change every register use, just something a little
more than the set needed to build after changing the return type of
MachineOperand::getReg().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364191
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Bjorn Pettersson [Mon, 24 Jun 2019 15:50:18 +0000 (15:50 +0000)]
[AMDGPU] Remove unused variable AllSGPRSpilledToVGPRs. NFC
Summary:
Removing the unused variable AllSGPRSpilledToVGPRs in
SIFrameLowering::processFunctionBeforeFrameFinalized
to avoid
error: variable 'AllSGPRSpilledToVGPRs' set but not used
[-Werror=unused-but-set-variable]
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63721
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364190
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Matt Arsenault [Mon, 24 Jun 2019 15:27:29 +0000 (15:27 +0000)]
Hexagon: Rename Register class
This avoids a naming conflict in a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364188
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Sanjay Patel [Mon, 24 Jun 2019 15:20:49 +0000 (15:20 +0000)]
[InstCombine] reduce funnel-shift i16 X, X, 8 to bswap X
Prefer the more exact intrinsic to remove a use of the input value
and possibly make further transforms easier (we will still need
to match patterns with funnel-shift of wider types as pieces of
bswap, especially if we want to canonicalize to funnel-shift with
constant shift amount). Discussed in D46760.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364187
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Matt Arsenault [Mon, 24 Jun 2019 14:53:58 +0000 (14:53 +0000)]
AMDGPU/GlobalISel: Fix RegBankSelect for s1 sext/zext/anyext
This needs different handling if the source is known to be a valid
condition or not. Handle turning it into shifts or a select during
regbankselect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364186
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Matt Arsenault [Mon, 24 Jun 2019 14:53:56 +0000 (14:53 +0000)]
AMDGPU: Fold frame index into MUBUF
This matters for byval uses outside of the entry block, which appear
as copies.
Previously, the only folding done was during selection, which could
not see the underlying frame index. For any uses outside the entry
block, the frame index was materialized in the entry block relative to
the global scratch wave offset.
This may produce worse code in cases where the offset ends up not
fitting in the MUBUF offset field. A better heuristic would be helpfu
for extreme frames.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364185
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Sanjay Patel [Mon, 24 Jun 2019 14:47:02 +0000 (14:47 +0000)]
[InstCombine] add tests for funnel-shift to bswap; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364184
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Matt Arsenault [Mon, 24 Jun 2019 14:34:40 +0000 (14:34 +0000)]
AMDGPU: Cleanup checking when spills need emergency slots
Address fixme, which should no longer be a problem since r363757.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364182
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Simon Pilgrim [Mon, 24 Jun 2019 13:13:36 +0000 (13:13 +0000)]
[InstCombine] SliceUpIllegalIntegerPHI - bail on out of range shifts
trunc(lshr) handling - if the shift is out of range (undefined) then bail like we do for non-constant shifts.
Fixes OSS Fuzz #15217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364181
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Simon Pilgrim [Mon, 24 Jun 2019 12:47:17 +0000 (12:47 +0000)]
[DAGCombine] visitMUL - allow shift by zero in MulByConstant.
This can occur under certain circumstances when undefs are created later on in the constant multipliers (e.g. in this case due to SimplifyDemandedVectorElts). Its better to let the shift by zero to occur and perform any cleanup afterward.
Fixes OSS Fuzz #15429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364179
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Bjorn Pettersson [Mon, 24 Jun 2019 12:07:17 +0000 (12:07 +0000)]
[ConstantFolding] Use hasVectorInstrinsicScalarOpd. NFC
Summary:
Use the hasVectorInstrinsicScalarOpd helper function
in ConstantFoldVectorCall.
Reviewers: rengolin, RKSimon, dblaikie
Reviewed By: rengolin, RKSimon
Subscribers: tschuett, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364178
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Bjorn Pettersson [Mon, 24 Jun 2019 12:07:11 +0000 (12:07 +0000)]
[Scalarizer] Add scalarizer support for smul.fix.sat
Summary:
Handle smul.fix.sat in the scalarizer. This is done by
adding smul.fix.sat to the set of "isTriviallyVectorizable"
intrinsics.
The addition of smul.fix.sat in isTriviallyVectorizable and
hasVectorInstrinsicScalarOpd can also be seen as a preparation
to be able to use hasVectorInstrinsicScalarOpd in ConstantFolding.
Reviewers: rengolin, RKSimon, dblaikie
Reviewed By: rengolin
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364177
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James Henderson [Mon, 24 Jun 2019 10:50:49 +0000 (10:50 +0000)]
[docs][llvm-nm] Add missing options to documentation
There were several options missing from the documentation. This patch
adds them as well as improving some wording and separating the Mach-O
only options into a separate section.
Fixes https://bugs.llvm.org/show_bug.cgi?id=42234.
Reviewed by: MaskRay
Differential Revision: https://reviews.llvm.org/D63655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364176
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Fangrui Song [Mon, 24 Jun 2019 10:23:47 +0000 (10:23 +0000)]
[sancov] Avoid unnecessary unique_ptr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364175
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Simon Tatham [Mon, 24 Jun 2019 10:00:39 +0000 (10:00 +0000)]
[ARM] Add MVE interleaving load/store family.
This adds the family of loads and stores with names like VLD20.8 and
VST42.32, which load and store parts of multiple q-registers in such a
way that executing both VLD20 and VLD21, or all four of VLD40..VLD43,
will distribute 2 or 4 vectors' worth of memory data across the lanes
of the same number of registers but in a transposed order.
In addition to the Tablegen descriptions of the instructions
themselves, this patch also adds encode and decode support for the
QQPR and QQQQPR register classes (representing the range of loaded or
stored vector registers), and tweaks to the parsing system for lists
of vector registers to make it return the right format in this case
(since, unlike NEON, MVE regards q-registers as primitive, and not
just an alias for two d-registers).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364172
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James Henderson [Mon, 24 Jun 2019 09:53:02 +0000 (09:53 +0000)]
[docs][llvm-nm] Improve symbol code documentation
The existing symbol code documentation was very incomplete. This patch
adds the missing codes, and defines them based on the current code
behaviour.
Fixes https://bugs.llvm.org/show_bug.cgi?id=42231.
Reviewed by: rupprecht, mtrent, MaskRay
Differential Revision: https://reviews.llvm.org/D63327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364171
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Pavel Labath [Mon, 24 Jun 2019 09:11:24 +0000 (09:11 +0000)]
[Support] Fix error handling in DataExtractor::get[US]LEB128
Summary:
These functions are documented as not modifying the offset argument if
the extraction fails (just like other DataExtractor functions). However,
while reviewing D63591 we discovered that this is not the case -- if the
function reaches the end of the data buffer, it will just return the
value parsed until that point and set offset to point to the end of the
buffer.
This fixes the functions to act as advertised, and adds a regression
test.
Reviewers: dblaikie, probinson, bkramer
Subscribers: kristina, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63645
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364169
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Sjoerd Meijer [Mon, 24 Jun 2019 08:44:29 +0000 (08:44 +0000)]
Follow up of rL363913. NFC.
Minor reshuffle in AArch64 targetparser unittest, solving a potential problem
with querying iterators too early.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364168
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George Rimar [Mon, 24 Jun 2019 08:29:54 +0000 (08:29 +0000)]
[llvm-readobj/llvm-readelf] - Eliminate the elf-groups.x86_64 precompiled binary from the inputs.
We do not need the elf-groups.x86_64. In one of the tests, it was
used for no solid reason, and for the second test case we can use
YAML input with SHT_GROUP sections.
The patch performs a cleanup of one of the test cases, removes another
one completely (since during the review was found out it actually
duplicates one of the existent tests) and removes the precompiled binary.
Differential revision: https://reviews.llvm.org/D63647
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364167
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Craig Topper [Sun, 23 Jun 2019 23:51:21 +0000 (23:51 +0000)]
[X86] Turn v16i16->v16i8 truncate+store into a any_extend+truncstore if we avx512f, but not avx512bw.
Ideally we'd be able to represent this truncate as a any_extend to
v16i32 and a truncate, but SelectionDAG doens't know how to not
fold those together.
We have isel patterns to use a vpmovzxwd+vpdmovdb for the truncate,
but we aren't able to simultaneously fold the load and the store
from the isel pattern. By pulling the truncate into the store we
can successfully hide it from the DAG combiner. Then we can isel
pattern match the truncstore and load+any_extend separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364163
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Petr Hosek [Sun, 23 Jun 2019 23:12:10 +0000 (23:12 +0000)]
[GN] Generation failure caused by trailing space in file name
When I executed gn.py gen out/gn I got the following error:
ERROR at //compiler-rt/lib/builtins/BUILD.gn:162:7: Only source, header, and object files belong in the sources of a static_library. //compiler-rt/lib/builtins/emutls.c is not one of the valid types.
"emutls.c ",
^----------
See //compiler-rt/lib/BUILD.gn:3:5: which caused the file to be included.
"//compiler-rt/lib/builtins",
^---------------------------
It turns out to be that the latest gn doesn't accept ill-format file name. And the emutls.c above has a trailing space.
Remove the trailing space should work.
Patch By: myhsu
Differential Revision: https://reviews.llvm.org/D63449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364162
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Sanjoy Das [Sun, 23 Jun 2019 19:22:13 +0000 (19:22 +0000)]
Fix typo in comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364159
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Craig Topper [Sun, 23 Jun 2019 19:17:50 +0000 (19:17 +0000)]
[X86] Fix isel pattern that was looking for a bitcasted load. Remove what appears to be a copy/paste mistake.
DAG combine should ensure bitcasts of loads don't exist.
Also remove 3 patterns that are identical to the block above them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364158
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Philip Reames [Sun, 23 Jun 2019 17:13:53 +0000 (17:13 +0000)]
[Tests] Autogen and improve test readability
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364156
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Philip Reames [Sun, 23 Jun 2019 17:06:57 +0000 (17:06 +0000)]
[IndVars] Remove dead instructions after folding trivial loop exit
In rL364135, I taught IndVars to fold exiting branches in loops with a zero backedge taken count (i.e. loops that only run one iteration). This extends that to eliminate the dead comparison left around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364155
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Fangrui Song [Sun, 23 Jun 2019 16:05:29 +0000 (16:05 +0000)]
SlotIndexes: delete unused functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364154
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Sanjay Patel [Sun, 23 Jun 2019 14:22:37 +0000 (14:22 +0000)]
[InstCombine] squash is-power-of-2 that uses ctpop
This is another intermediate IR step towards solving PR42314:
https://bugs.llvm.org/show_bug.cgi?id=42314
We can test if a value is power-of-2-or-0 using ctpop(X) < 2,
so combining that with a non-zero check of the input is the
same as testing if exactly 1 bit is set:
(X != 0) && (ctpop(X) u< 2) --> ctpop(X) == 1
Differential Revision: https://reviews.llvm.org/D63660
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364153
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Fangrui Song [Sun, 23 Jun 2019 13:16:03 +0000 (13:16 +0000)]
SlotIndexes: simplify IdxMBBPair operators
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364152
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Craig Topper [Sun, 23 Jun 2019 07:00:46 +0000 (07:00 +0000)]
[SelectionDAG] Remove the code that attempts to calculate the alignment for the second half of a split masked load/store.
The code divides the alignment by 2 if the original alignment is
equal to the original VT size. But this wouldn't be correct
if the alignment was larger than the VT size.
The memory operand object already takes care of calling MinAlign
on the base alignment and the memory pointer offset. So we don't
need any special code at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364151
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Craig Topper [Sun, 23 Jun 2019 06:06:04 +0000 (06:06 +0000)]
[X86][SelectionDAG] Cleanup and simplify masked_load/masked_store in tablegen. Use more precise PatFrags for scalar masked load/store.
Rename masked_load/masked_store to masked_ld/masked_st to discourage
their direct use. We need to check truncating/extending and
compressing/expanding before using them. This revealed that
our scalar masked load/store patterns were misusing these.
With those out of the way, renamed masked_load_unaligned and
masked_store_unaligned to remove the "_unaligned". We didn't
check the alignment anyway so the name was somewhat misleading.
Make the aligned versions inherit from masked_load/store instead
from a separate identical version. Merge the 3 different alignments
PatFrags into a single version that uses the VT from the SDNode to
determine the size that the alignment needs to match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364150
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Keno Fischer [Sun, 23 Jun 2019 00:29:59 +0000 (00:29 +0000)]
[Support] Fix build under Emscripten
Summary:
Emscripten's libc doesn't define MNT_LOCAL, thus causing a build
failure in the fallback path. However, to the best of my knowledge,
it also doesn't support remote file system mounts, so we may simply
return `true` here (as we do for e.g. Fuchsia). With this fix, the
core LLVM libraries build correctly under emscripten (though some
of the tools and utils do not).
Reviewers: kripken
Differential Revision: https://reviews.llvm.org/D63688
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364143
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Don Hinton [Sat, 22 Jun 2019 23:32:36 +0000 (23:32 +0000)]
Revert [CommandLine] Remove OptionCategory and SubCommand caches from the Option class.
This reverts r364134 (git commit
a5b83bc9e3b8e8945b55068c762bd6c73621a4b0)
Caused errors in the asan bot, so the GeneralCategory global needs to
be changed to ManagedStatic.
Differential Revision: https://reviews.llvm.org/D62105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364141
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Simon Pilgrim [Sat, 22 Jun 2019 17:57:01 +0000 (17:57 +0000)]
[X86][SSE] Fold extract_subvector(vselect(x,y,z),0) -> vselect(extract_subvector(x,0),extract_subvector(y,0),extract_subvector(z,0))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364136
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Philip Reames [Sat, 22 Jun 2019 17:54:25 +0000 (17:54 +0000)]
Exploit a zero LoopExit count to eliminate loop exits
This turned out to be surprisingly effective. I was originally doing this just for completeness sake, but it seems like there are a lot of cases where SCEV's exit count reasoning is stronger than it's isKnownPredicate reasoning.
Once this is in, I'm thinking about trying to build on the same infrastructure to eliminate provably untaken checks. There may be something generally interesting here.
Differential Revision: https://reviews.llvm.org/D63618
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364135
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Don Hinton [Sat, 22 Jun 2019 17:22:50 +0000 (17:22 +0000)]
[CommandLine] Remove OptionCategory and SubCommand caches from the Option class.
Summary:
This change processes `OptionCategory`s and `SubCommand`s as they
are seen instead of caching them in the Option class and processing
them later. Doing so simplifies the work needed to be done by the Global
parser and significantly reduces the size of the Option class to a mere 64
bytes.
Removing the `OptionCategory` cache saved 24 bytes, and removing
the `SubCommand` cache saved an additional 48 bytes, for a total of a
72 byte reduction.
Reviewers: beanz, zturner, MaskRay, serge-sans-paille
Reviewed By: serge-sans-paille
Subscribers: serge-sans-paille, tstellar, zturner, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364134
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Hubert Tong [Sat, 22 Jun 2019 16:03:29 +0000 (16:03 +0000)]
[NFC] Fix indentation in PPCAsmPrinter.cpp
After r248261, the indentation switches, inside a namespace definition,
between indenting and not indenting one level in for that namespace; the
abomination occurs in the middle of a class definition. Fix that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364133
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Hubert Tong [Sat, 22 Jun 2019 16:02:02 +0000 (16:02 +0000)]
[PowerPC][NFC] Move comment to the relevant function
A comment that applies to a virtual destructor was placed on a class
constructor. Move the comment to where it belongs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364132
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Nico Weber [Sat, 22 Jun 2019 11:23:01 +0000 (11:23 +0000)]
PDB docs: Delete trailing whitespace, wrap to 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364131
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Nikita Popov [Sat, 22 Jun 2019 10:20:13 +0000 (10:20 +0000)]
[NewGVN] Fix copy/paste mistake in cast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364130
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Nikita Popov [Sat, 22 Jun 2019 10:20:07 +0000 (10:20 +0000)]
[NewGVN] Remove dead SwitchEdges variable; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364129
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Nikita Popov [Sat, 22 Jun 2019 09:57:59 +0000 (09:57 +0000)]
[LFTR] Add tests for PR41998; NFC
The limit for the pointer case is incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364128
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Peter Collingbourne [Sat, 22 Jun 2019 03:03:25 +0000 (03:03 +0000)]
AArch64: Add support for reading pc using llvm.read_register.
This is useful for allowing code to efficiently take an address
that can be later mapped onto debug info. Currently the hwasan
pass achieves this by taking the address of the current function:
http://llvm-cs.pcc.me.uk/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp#921
but this costs two instructions (plus a GOT entry in PIC code) per function
with stack variables. This will allow the cost to be reduced to a single
instruction.
Differential Revision: https://reviews.llvm.org/D63471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364126
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Fangrui Song [Sat, 22 Jun 2019 01:50:21 +0000 (01:50 +0000)]
[CMake] Delete redundant DEPENDS/LINK_LIBS from LineEditor/XRay
The link dependencies are already specified in LLVMBuild.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364125
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Fangrui Song [Sat, 22 Jun 2019 01:30:17 +0000 (01:30 +0000)]
Make GlobalISel depend on SelectionDAG after D63169
GlobalISel/IRTranslator.cpp now references SelectionDAG/FunctionLoweringInfo.cpp.
This fixes a link error in -DBUILD_SHARED_LIBS=on builds:
ld.lld: error: undefined symbol: llvm::FunctionLoweringInfo::clear()
>>> referenced by IRTranslator.cpp:2198 (../lib/CodeGen/GlobalISel/IRTranslator.cpp:2198)
>>> lib/CodeGen/GlobalISel/CMakeFiles/LLVMGlobalISel.dir/IRTranslator.cpp.o:(llvm::IRTranslator::finalizeFunction())
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364124
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Douglas Yung [Sat, 22 Jun 2019 01:14:29 +0000 (01:14 +0000)]
Fix UNSUPPORTED attribute from windows to system-windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364122
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Yuanfang Chen [Sat, 22 Jun 2019 01:13:04 +0000 (01:13 +0000)]
[llvm-objdump] Allow --disassemble-functions to take demangled names
The --disassemble-functions switch takes demangled names when
--demangle is specified, otherwise the switch takes mangled names.
https://bugs.llvm.org/show_bug.cgi?id=41908
Reviewers: jhenderson, grimar, MaskRay, rupprecht
Differential Revision: https://reviews.llvm.org/D63524
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364121
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Yuanfang Chen [Sat, 22 Jun 2019 00:22:57 +0000 (00:22 +0000)]
[llvm-objdump] Move --start-address >= --stop-address check out of the
-d code.
Summary:
Move it into `main` function so the checking is effective for all actions
user may do with llvm-objdump; notably, -r and -s in addition to existing -d.
Match GNU behavior.
Reviewers: jhenderson, grimar, MaskRay, rupprecht
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63631
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364118
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Peter Collingbourne [Sat, 22 Jun 2019 00:06:51 +0000 (00:06 +0000)]
AArch64: Prefer FP-relative debug locations in HWASANified functions.
To help produce better diagnostics for stack use-after-return, we'd like
to be able to determine the addresses of each HWASANified function's local
variables given a small amount of information recorded on entry to the
function. Currently we require all HWASANified functions to use frame pointers
and record (PC, FP) on function entry. This works better than recording SP
because FP cannot change during the function, unlike SP which can change
e.g. due to dynamic alloca.
However, most variables currently end up using SP-relative locations in their
debug info. This prevents us from recomputing the address of most variables
because the distance between SP and FP isn't recorded in the debug info. To
address this, make the AArch64 backend prefer FP-relative debug locations
when producing debug info for HWASANified functions.
Differential Revision: https://reviews.llvm.org/D63300
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364117
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Peter Collingbourne [Sat, 22 Jun 2019 00:03:53 +0000 (00:03 +0000)]
gn build: Merge r364046.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364116
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Tom Tan [Fri, 21 Jun 2019 23:38:05 +0000 (23:38 +0000)]
[COFF, ARM64] Fix encoding of debugtrap for Windows
On Windows ARM64, intrinsic __debugbreak is compiled into brk #0xF000 which is
mapped to llvm.debugtrap in Clang. Instruction brk #F000 is the defined break
point instruction on ARM64 which is recognized by Windows debugger and
exception handling code, so llvm.debugtrap should map to it instead of
redirecting to llvm.trap (brk #1) as the default implementation.
Differential Revision: https://reviews.llvm.org/D63635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364115
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Reid Kleckner [Fri, 21 Jun 2019 23:10:25 +0000 (23:10 +0000)]
Revert [SLP] Look-ahead operand reordering heuristic.
This reverts r364084 (git commit
5698921be2d567f6abf925479ac9f5a376d6d74f)
It caused crashes while compiling a file in Chrome. Reduction
forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364111
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Shoaib Meenai [Fri, 21 Jun 2019 21:59:01 +0000 (21:59 +0000)]
[llvm-lipo] Implement -thin
Creates thin output file of specified arch_type from the fat input file.
Patch by Anusha Basana <anushabasana@fb.com>
Differential Revision: https://reviews.llvm.org/D63341
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364107
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Julian Lettner [Fri, 21 Jun 2019 21:01:39 +0000 (21:01 +0000)]
[ASan] Use dynamic shadow on 32-bit iOS and simulators
The VM layout on iOS is not stable between releases. On 64-bit iOS and
its derivatives we use a dynamic shadow offset that enables ASan to
search for a valid location for the shadow heap on process launch rather
than hardcode it.
This commit extends that approach for 32-bit iOS plus derivatives and
their simulators.
rdar://
50645192
rdar://
51200372
rdar://
51767702
Reviewed By: delcypher
Differential Revision: https://reviews.llvm.org/D63586
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364105
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Craig Topper [Fri, 21 Jun 2019 20:16:26 +0000 (20:16 +0000)]
[X86] Add test cases for incorrect shrinking of volatile vector loads from 128-bits to 32 or 64 bits. NFC
This is caused by isel patterns that look for vzmovl+load and
treat it the same as vzload.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364101
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Matt Arsenault [Fri, 21 Jun 2019 20:04:02 +0000 (20:04 +0000)]
AMDGPU: Fix not using s33 for scratch wave offset in kernels
Fixes missing piece from r363990.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364099
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