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Rex Zhu [Sat, 24 Feb 2018 11:53:41 +0000 (19:53 +0800)]
drm/amd/pp: Revert gfx/compute profile switch sysfs
The gfx/compute profiling mode switch is only for internally
test. Not a complete solution and unexpectly upstream.
so revert it.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 23 Feb 2018 09:41:07 +0000 (17:41 +0800)]
drm/amd/pp: Fix sclk in highest two levels when compute on smu7
Compute workload tends to be "bursty", Only tune the behavior of
nature dpm don't work well for most of such workloads. From test
results, Fix sclk in highest two levels can get better performance.
so add min sclk setting into the default cumpute workload policy on
smu7.
user still can change sclk range through sysfs pp_dpm_sclk
for better perf/watt.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 31 Jan 2018 06:48:14 +0000 (14:48 +0800)]
drm/amd/pp: Implement get/set_power_profile_mode on smu7
It show what parameters can be configured to tune
the behavior of natural dpm for perf/watt on smu7.
user can select the mode per workload, but even the default per
workload settings are not bulletproof.
user can configure custom settings per different use case
for better perf or better perf/watt.
cat pp_power_profile_mode
NUM MODE_NAME SCLK_UP_HYST SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL MCLK_UP_HYST MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL
0 3D_FULL_SCREEN: 0 100 30 0 100 10
1 POWER_SAVING: 10 0 30 - - -
2 VIDEO: - - - 10 16 31
3 VR: 0 11 50 0 100 10
4 COMPUTE: 0 5 30 - - -
5 CUSTOM: 0 0 0 0 0 0
* CURRENT: 0 100 30 0 100 10
Under manual dpm level,
user can echo "0/1/2/3/4">pp_power_profile_mode
to select 3D_FULL_SCREEN/POWER_SAVING/VIDEO/VR/COMPUTE
mode.
echo "5 * * * * * * * *">pp_power_profile_mode
to set custom settings.
"5 * * * * * * * *" mean "CUSTOM enable_sclk SCLK_UP_HYST
SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL enable_mclk MCLK_UP_HYST
MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL"
if the parameter enable_sclk/enable_mclk is true,
driver will update the following parameters to dpm table.
if false, ignore the following parameters.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 23 Feb 2018 08:52:41 +0000 (16:52 +0800)]
drm/amd/pp: Implement update_dpm_settings on CI
use SW method to update DPM settings by updating SRAM
directly on CI.
Reviewed-by: Alex Deucher <alexdeucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 23 Feb 2018 08:41:20 +0000 (16:41 +0800)]
drm/amd/pp: Implement update_dpm_settings on Tonga
use SW method to update DPM settings by updating SRAM
directly on Tonga.
Reviewed-by: Alex Deucher <alexdeucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 23 Feb 2018 08:39:59 +0000 (16:39 +0800)]
drm/amd/pp: Implement update_dpm_settings on Fiji
use SW method to update DPM settings by updating SRAM
directly on Fiji.
Reviewed-by: Alex Deucher <alexdeucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 1 Mar 2018 16:05:31 +0000 (11:05 -0500)]
drm/amdgpu: fix KV harvesting
Always set the graphics values to the max for the
asic type. E.g., some 1 RB chips are actually 1 RB chips,
others are actually harvested 2 RB chips.
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=99353
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Thu, 1 Mar 2018 16:03:27 +0000 (11:03 -0500)]
drm/radeon: fix KV harvesting
Always set the graphics values to the max for the
asic type. E.g., some 1 RB chips are actually 1 RB chips,
others are actually harvested 2 RB chips.
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=99353
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Rex Zhu [Wed, 24 Jan 2018 09:15:37 +0000 (17:15 +0800)]
drm/amd/pp: Implement update_dpm_settings on Polaris
v2: lock dpm level when update pptable by SW method
use SW method to update DPM settings by updating SRAM
directly on Polaris.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 23 Feb 2018 08:32:55 +0000 (16:32 +0800)]
drm/amd/pp: Add a helper to set field in u32
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 24 Jan 2018 06:48:17 +0000 (14:48 +0800)]
drm/amd/pp: Add common interface in smu for update dpm setting
it is used for adjust part of dpm settigs per workloads
to change the natural dpm behavior for better perf or perf/watt.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 2 Mar 2018 05:50:59 +0000 (13:50 +0800)]
drm/amd/pp: Add PCC feature support on Vega
This features controls vega peak current protection to allow
for a wider compatibility with power supplies.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 2 Mar 2018 02:52:25 +0000 (10:52 +0800)]
drm/amd/pp: Export new smu message for PCC feature on Vega10
used to set PccThrottleLevel and PccResidencyThreshold
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 27 Feb 2018 11:15:08 +0000 (19:15 +0800)]
drm/amd/pp: Remove cgs_query_system_info
Get gpu info through adev directly in powerplay
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 27 Feb 2018 10:28:54 +0000 (18:28 +0800)]
drm/amd/pp: Remove the wrap functions for acpi in powerplay
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 27 Feb 2018 10:27:54 +0000 (18:27 +0800)]
drm/amd/pp: Use amdgpu acpi helper functions in powerplay
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 27 Feb 2018 10:20:53 +0000 (18:20 +0800)]
drm/amdgpu: Notify sbios device ready before send request
it is required if a platform supports PCIe root complex
core voltage reduction. After receiving this notification,
SBIOS can apply default PCIe root complex power policy.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Rex Zhu [Tue, 27 Feb 2018 06:09:40 +0000 (14:09 +0800)]
drm/amd/pp: Refine powerplay instance
Include adev in powerplay instance.
so can visit adev directly instand of through cgs interface.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 26 Feb 2018 11:58:49 +0000 (19:58 +0800)]
drm/amd/pp: Simplify the create of powerplay instance
use adev as input parameter to create powerplay instance
directly. delete cgs wrap layer for power play create.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 26 Feb 2018 11:47:54 +0000 (19:47 +0800)]
drm/amd/dc: Use forward declaration instand of include header file
avoid build error:
drivers/gpu/drm/amd/amdgpu/../powerplay/inc/smu9_driver_if.h:342:3: error: redeclaration of enumerator ‘WM_COUNT’
WM_COUNT,
^
In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:32:0,
from drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services.h:35,
from drivers/gpu/drm/amd/amdgpu/../display/modules/inc/mod_freesync.h:57,
from drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:48,
from drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:55,
from drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amd_powerplay.h:33,
from drivers/gpu/drm/amd/amdgpu/../powerplay/inc/smumgr.h:26,
from drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vega10_smumgr.c:24:
drivers/gpu/drm/amd/amdgpu/../display/dc/dm_pp_smu.h:43:2: note: previous definition of ‘WM_COUNT’ was here
WM_COUNT,
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Wed, 28 Feb 2018 06:44:58 +0000 (12:14 +0530)]
drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)
The below commit
"drm/atomic: Try to preserve the crtc enabled state in drm_atomic_remove_fb, v2"
introduces a slight behavioral change to rmfb. Instead of disabling a crtc
when the primary plane is disabled, it now preserves it.
This change leads to BUG hit while performing atomic commit on amd driver.
As a fix this patch ensures that we disable the CRTC's with NULL FB by returning
-EINVAL and hence triggering fall back to the old behavior and turning off the
crtc in atomic_remove_fb().
V2: Added error check for plane_state and removed sanity check for crtc.
Signed-off-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 2 Mar 2018 10:41:41 +0000 (18:41 +0800)]
drm/amd/pp: Fix incorrect return value in smu7_check_clk_voltage_valid
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Fri, 23 Feb 2018 11:29:04 +0000 (12:29 +0100)]
drm/amdgpu/dce6: Use DRM_DEBUG instead of DRM_INFO for HPD IRQ info
For consistency with other DCE generations.
HPD IRQs appear to be working fine.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 1 Mar 2018 10:09:15 +0000 (11:09 +0100)]
drm/amdgpu: use separate status for buffer funcs availability v2
The ring status can change during GPU reset, but we still need to be
able to schedule TTM buffer moves in the meantime.
Otherwise we can ran into problems because of aborted move/fill
operations during GPU resets.
v2: still check if ring is available during direct submit.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 1 Mar 2018 10:03:27 +0000 (11:03 +0100)]
drm/amdgpu: ignore changes of buffer function status because of GPU resets
When we reset the GPU we also disable/enable the SDMA, but we don't want
to change TTM idea of the VRAM size in the middle of that.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 1 Mar 2018 10:01:52 +0000 (11:01 +0100)]
drm/amdgpu: change amdgpu_ttm_set_active_vram_size
Instead of setting the active VRAM size directly provide a the info if
we can use the buffer functions or not.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 1 Mar 2018 09:41:46 +0000 (10:41 +0100)]
drm/amdgpu: move some functions into amdgpu_ttm.h
Those belong to the TTM handling.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Tue, 20 Feb 2018 18:36:23 +0000 (13:36 -0500)]
drm/amd/display: Default HDMI6G support to true. Log VBIOS table error.
There have been many reports of Ellesmere and Baffin systems not being
able to drive HDMI 4k60 due to the fact that we check the HDMI_6GB_EN
bit from VBIOS table. Windows seems to not have this issue.
On some systems we fail to the encoder cap info from VBIOS. In that case
we should default to enabling HDMI6G support.
This was tested by dwagner on
https://bugs.freedesktop.org/show_bug.cgi?id=102820
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Shirish S [Tue, 13 Feb 2018 08:45:17 +0000 (14:15 +0530)]
drm/amd/display: update plane params before validation
This patch updates the dc's plane state with the parameters set by the
user side.
This is needed to validate the plane capabilities with the parameters
user space wants to set.
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Tue, 13 Feb 2018 16:07:43 +0000 (11:07 -0500)]
drm/amd/display: Don't blow up if TG is NULL in dce110_vblank_set
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Tue, 13 Feb 2018 08:41:37 +0000 (14:11 +0530)]
drm/amd/display: validate plane in dce110 for scaling
CZ & ST support uptil a limit 2:1 downscaling, this patch
adds validate_plane hook, that shall be used to validate
the plane attributes sent by the user space based
on dce110 capabilities.
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Fri, 16 Feb 2018 06:14:22 +0000 (11:44 +0530)]
drm/amd/display: defer modeset check in dm_update_planes_state
amdgpu_dm_atomic_check() is used to validate the entire configuration of
planes and crtc's that the user space wants to commit.
However amdgpu_dm_atomic_check() depends upon DRM_MODE_ATOMIC_ALLOW_MODESET
flag else its mostly dummy.
Its not mandatory for the user space to set DRM_MODE_ATOMIC_ALLOW_MODESET,
and in general its not set either along with DRM_MODE_ATOMIC_TEST_ONLY.
Considering its importantance, this patch defers the allow_modeset check
in dm_update_planes_state(), so that there shall be scope to validate
the configuration sent from user space, without impacting the population
of dc/dm related data structures.
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Tue, 13 Feb 2018 16:07:07 +0000 (11:07 -0500)]
drm/amd/display: Clean up formatting in irq_service_dce110.c
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Tue, 13 Feb 2018 16:03:01 +0000 (11:03 -0500)]
drm/amd/display: Return success when enabling interrupt
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Tue, 13 Feb 2018 15:54:26 +0000 (10:54 -0500)]
drm/amd/display: Use crtc enable/disable_vblank hooks
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Wed, 21 Feb 2018 21:40:50 +0000 (16:40 -0500)]
drm/amd/display: dal 3.1.37
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Fri, 9 Feb 2018 21:52:15 +0000 (16:52 -0500)]
drm/amd/display: Remove duplicate dm_pp_power_level enum
This is really just a copy of dm_pp_clocks_state, so just use that one.
Thanks to Matthias Kaehlke for spotting this.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Wed, 21 Feb 2018 21:37:16 +0000 (16:37 -0500)]
drm/amd/display: update infoframe after dig fe is turned on
Before dig fe is enabled, infoframe can't be programmed. So in
suspend resume case our infoframe programmming was not going through.
This change changes the sequence so that infoframe is programmed
after.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Wed, 21 Feb 2018 20:10:02 +0000 (15:10 -0500)]
drm/amd/display: fix dcn1 dppclk when min dispclk patch applies
Applying min dispclk patch would result in incorrect dppclk divider
without this change
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Tue, 20 Feb 2018 22:42:50 +0000 (17:42 -0500)]
drm/amd/display: define DC_LOGGER for logger
Created a DC_LOGGER define. This is used to
pass the logger into the macros.
Anywhere we need to use the logger we need to define
DC_LOGGER
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Fri, 16 Feb 2018 18:57:42 +0000 (13:57 -0500)]
drm/amd/display: Use MACROS instead of dm_logger
Created MACROS for all log levels. Also Replaced
usage of dm_logger_write to the defined MACROS
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Vitaly Prosyak [Tue, 13 Feb 2018 19:18:43 +0000 (13:18 -0600)]
drm/amd/display: Handle HDR use cases.
Implementation of de-gamma, blnd-gamma, shaper and
3d lut's.
Removed memory allocations in transfer functions.
Refactor color module.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Bernstein [Fri, 16 Feb 2018 22:46:54 +0000 (17:46 -0500)]
drm/amd/display: Fix DAL surface change test
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Sat, 17 Feb 2018 06:34:42 +0000 (01:34 -0500)]
drm/amd/display: dal 3.1.36
Signed-off-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Tue, 13 Feb 2018 19:41:51 +0000 (14:41 -0500)]
drm/amd/display: add diags clock programming
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Mon, 12 Feb 2018 20:19:20 +0000 (15:19 -0500)]
drm/amd/display: add per pipe dppclk
v2: Fix commit title
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Wed, 17 Jan 2018 22:40:16 +0000 (17:40 -0500)]
drm/amd/display: Update DCN OPTC registers
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Tue, 20 Feb 2018 09:04:16 +0000 (14:34 +0530)]
drm/amd/display: allocate fbc buffer in AMDGPU_GEM_DOMAIN_GTT
Currently the FBC buffer is allocated in VRAM, since VRAM usage is
dedicatedly for scanouts, by allocating FBC back buffer in GTT
shall help in conserving VRAM for other purposes.
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo (Sunpeng) Li [Tue, 20 Feb 2018 18:30:47 +0000 (13:30 -0500)]
drm/amd/display: Add regamma lut write mask to SOC base
Mask and shift values for DCP0_REGAMMA_LUT_WRITE_EN_MASK were missing
from XFM_COMMON_MASK_SH_LIST_SOC_BASE. Add it.
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Fri, 16 Feb 2018 19:04:16 +0000 (14:04 -0500)]
drm/amd/display: Update Link Training Fallback logic
[Description]
When CR fails to minimum link rate,
we should reduce lane count to the number lowest cr_done lanes.
[Code Review]
Jun Lei
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xingyue Tao [Fri, 16 Feb 2018 21:29:13 +0000 (16:29 -0500)]
drm/amd/display: add psr_version to stream
Brightness could not be changed for some panels whose DPCD_version is below 1.2
Now psr_version is added into stream, and it copies from the displayTarget's psr_version.
It checks if the stream's psr_versio is non-zero and sets the vsc info packet revision now.
Signed-off-by: Xingyue Tao <xingyue.tao@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Wed, 14 Feb 2018 22:12:39 +0000 (17:12 -0500)]
drm/amd/display: Clear dmps off for eDP when resume.
This patch fixed secondary screen only S4 resume, eDP is unintentionally
light up due to incorrect dpms off flag.
When entering S4, dpms off flags are set to true via
set power state. During resume, eDP is light up by vbios, so the flags
should be changed to false to match the real state.
By change the flag properly, eDP is able to be turned off properly as per
OS request.
This change may affect S3/S4 Shut down resume IOIC, need to verify
those cases.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Thu, 15 Feb 2018 20:55:31 +0000 (15:55 -0500)]
drm/amd/display: fix missing az disable in reset backend
Optimization in reset backend skips disable stream if it is
already done in dc_stream_set_dpms. However that path does
not disable az in order to prevent audio from toggling
between internal and external displays. This still need to
be done.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Fri, 2 Feb 2018 06:17:34 +0000 (01:17 -0500)]
drm/amd/display: dal 3.1.35
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hersen Wu [Tue, 13 Feb 2018 21:23:12 +0000 (16:23 -0500)]
drm/amd/display: Check DCN PState ASSERT failure
[Description] ASIC change debug register definition
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yue Hin Lau [Mon, 12 Feb 2018 22:43:19 +0000 (17:43 -0500)]
drm/amd/display: update cur_clock correctly within set bandwidth
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo (Sunpeng) Li [Mon, 12 Feb 2018 18:20:56 +0000 (13:20 -0500)]
drm/amd/display: Use 4096 lut entries
Points in the DRM LUT are spaced linearly. Points in hardware are spaced
exponentially, with greater density towards 0. To maintain low-end
accuracy in hardware when sampling the DRM LUT, more points are needed.
However, X doesn't seem to play with legacy LUTs of such size.
Therefore, check for legacy lut when updating DC states, and update
accordingly.
v2: Use a macro for the maximum drm LUT value.
v3: Update commit to reflect that this does not map 1-1 to HW
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Barberiz [Fri, 9 Feb 2018 22:48:18 +0000 (17:48 -0500)]
drm/amd/display: Add passive dongle support for HPD Rearch
Add HPD delay timer support to
1. Single/dual link DVI.
2. DP to HDMI passive dongle
3. DP to DVI passive dongle.
Signed-off-by: John Barberiz <jbarberi@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Fri, 9 Feb 2018 21:57:38 +0000 (16:57 -0500)]
drm/amd/display: Fix active dongle hotplug
Clean fake sink flag after detecting link on downstream port.
Fixing display light-up after "hot-unplug&plug again" downstream
of an active dongle.
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hersen Wu [Fri, 9 Feb 2018 21:35:14 +0000 (16:35 -0500)]
drm/amd/display: move MST branch initialize to before link training
some MST capable scaler doesn't like recieving CLEAR_PAYLOAD_ID_TABLE after
link training. move branch initialize to before link training
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Matthias Kaehlcke [Wed, 28 Feb 2018 22:17:03 +0000 (14:17 -0800)]
drm/radeon/mkregtable: Delete unused list functions and macros
The util mkregtable includes a copy of the kernel API for linked lists,
only a small subset of it is used. Delete the unused functions and macros.
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 26 Feb 2018 16:05:10 +0000 (11:05 -0500)]
drm/amdgpu: used cached pcie gen info for SI (v2)
Rather than querying it every time we need it.
Also fixes a crash in VM pass through if there is no
root bridge because the cached value fetch already checks
this properly.
v2: fix includes
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105244
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Rex Zhu<rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Tom St Denis [Thu, 1 Mar 2018 14:39:57 +0000 (09:39 -0500)]
drm/amd/amdgpu: Mask rptr as well in ring debugfs
The read/write pointers on sdma4 devices increment
beyond the ring size and should be masked. Tested
on my Ryzen 2400G.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 25 Dec 2017 07:59:30 +0000 (15:59 +0800)]
drm/amdgpu: try again kiq access if not in IRQ(v4)
sometimes GPU is switched to other VFs and won't swich
back soon, so the kiq reg access will not signal within
a short period, instead of busy waiting a long time(MAX_KEQ_REG_WAIT)
and returning TMO we can istead sleep 5ms and try again
later (non irq context)
And since the waiting in kiq_r/weg is busy wait, so MAX_KIQ_REG_WAIT
shouldn't set to a long time, set it to 10ms is more appropriate.
if gpu already in reset state, don't retry the KIQ reg access
otherwise it would always hang because KIQ was already die usually.
v2:
replace schedule() with msleep() for the wait
v3:
use while loop for the wait repeating
use macros for the sleep period
more description for it
v4:
drop unused variable
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com
Reviewed-by: Pixel Ding <Pixel.Ding@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 25 Dec 2017 03:59:27 +0000 (11:59 +0800)]
drm/amdgpu: cleanups for vram lost handling
1)create a routine "handle_vram_lost" to do the vram
recovery, and put it into amdgpu_device_reset/reset_sriov,
this way no need of the extra paramter to hold the
VRAM LOST information and the related macros can be removed.
3)show vram_recover failure if time out, and set TMO equal to
lockup_timeout if vram_recover is under SRIOV runtime mode.
4)report error if any ip reset failed for SR-IOV
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 25 Dec 2017 07:14:58 +0000 (15:14 +0800)]
drm/amdgpu: stop all rings before doing gpu recover
found recover_vram_from_shadow sometimes get executed
in paralle with SDMA scheduler, should stop all
schedulers before doing gpu reset/recover
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 27 Feb 2018 16:44:31 +0000 (11:44 -0500)]
drm/amdgpu: fix module parameter descriptions
Some were missing the close parens around options.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Amber Lin [Tue, 27 Feb 2018 15:01:59 +0000 (10:01 -0500)]
drm/amdgpu: Map all visible VRAM at startup
When using CPU to update page table, we need to kmap all the PDs/PTs after
they are allocated and that requires a TLB shot down on each CPU, which is
quite heavy.
Instead, we map the whole visible VRAM to a kernel address at once. Pages
can be obtained from the offset.
v2: move the mapping base from gmc to amdgpu_mman structure, and the
implementation in amdgpu_ttm_* functions
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Wed, 21 Feb 2018 10:40:33 +0000 (16:10 +0530)]
drm/amd/display: check for ipp before calling cursor operations
Currently all cursor related functions are made to all
pipes that are attached to a particular stream.
This is not applicable to pipes that do not have cursor plane
initialised like underlay.
Hence this patch allows cursor related operations on a pipe
only if ipp in available on that particular pipe.
The check is added to set_cursor_position & set_cursor_attribute.
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Shirish S [Fri, 23 Feb 2018 10:40:13 +0000 (16:10 +0530)]
drm/amd/display: make dm_dp_aux_transfer return payload bytes instead of size
The drm layer expects aux->transfer() to return the payload bytes read.
Currently dm_dp_aux_transfer() returns the payload size which does not
gets updated during the read, hence not giving the right data for the
drm layer to pars edid. This leads to the drm layer to conclude as the
edid is BAD and hence some monitors/devices dont get detected properly.
This patch changes the return type of dm_dp_aux_transfer() to actual
bytes read during DP_AUX_NATIVE_READ & DP_AUX_I2C_READ.
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 29 Jan 2018 11:24:32 +0000 (19:24 +0800)]
drm/amdgpu: disable GFX ring and disable PQ wptr in hw_fini
otherwise there will be DMAR reading error comes out from CP since
GFX is still alive and CPC's WPTR_POLL is still enabled, which would
lead to DMAR read error.
fix:
we can hault CPG after hw_fini, but cannot halt CPC becaues KIQ
stil need to be alive to let RLCV invoke, but its WPTR_POLL could
be disabled.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Fri, 26 Jan 2018 08:57:25 +0000 (16:57 +0800)]
drm/amdgpu: cleanup SA inti and fini(v2)
should use bo_create_kernel instead of split to two
function that create and pin the SA bo
issue:
before this patch, there are DMAR read error in host
side when running SRIOV test, the DMAR address dropped
in the range of SA bo.
fix:
after this cleanups of SA init and fini, above DMAR
eror gone.
v2:
keep sa_bo's fini instead of suspend, to keep
reporting error
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Emily Deng [Wed, 7 Feb 2018 08:17:16 +0000 (16:17 +0800)]
drm/amdgpu: Correct sdma_v4 get_wptr(v2)
the original method will change the wptr value in wb.
v2:
furthur cleanup
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 23 Jan 2018 10:26:20 +0000 (18:26 +0800)]
drm/amdgpu: adjust timeout for ib_ring_tests(v2)
issue:
sometime GFX/MM ib test hit timeout under SRIOV env, root cause
is that engine doesn't come back soon enough so the current
IB test considered as timed out.
fix:
for SRIOV GFX IB test wait time need to be expanded a lot during
SRIOV runtimei mode since it couldn't really begin before GFX engine
come back.
for SRIOV MM IB test it always need more time since MM scheduling
is not go together with GFX engine, it is controled by h/w MM
scheduler so no matter runtime or exclusive mode MM IB test
always need more time.
v2:
use ring type instead of idx to judge
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Fri, 19 Jan 2018 12:29:17 +0000 (20:29 +0800)]
drm/amdgpu: don't use MM idle_work for SRIOV(v2)
SRIOV doesn't give VF cg/pg feature so the MM's idle_work
is skipped for SR-IOV
v2:
remove superfluous changes
since idle_work is not scheduled for SR-IOV so the condition
check for SR-IOV inside idle_work also can be dropped
v3:
drop the SRIOV check in amdgpu_vce/uvd_suspend
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 24 Feb 2018 06:29:12 +0000 (14:29 +0800)]
drm/amd/pp: Print more smu failed info on Vega10
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Huang [Mon, 26 Feb 2018 22:36:19 +0000 (17:36 -0500)]
drm/amd/powerplay: fix power over limit on Fiji
power containment disabled only on Fiji and compute
power profile. It violates PCIe spec and may cause power
supply failed. Enabling it will fix the issue, even the
fix will drop performance of some compute tests.
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
James Zhu [Tue, 27 Feb 2018 14:55:17 +0000 (09:55 -0500)]
drm/amdgpu:Fixed wrong emit frame size for enc
Emit frame size should match with corresponding function,
uvd_v6_0_enc_ring_emit_vm_flush has 5 amdgpu_ring_write
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 23 Jan 2018 11:17:56 +0000 (19:17 +0800)]
drm/amdgpu: increase gart size to 512MB
256MB is too small consider PTE/PDE shadow and TTM
eviction activity
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 24 Jan 2018 04:20:32 +0000 (12:20 +0800)]
drm/amdgpu: move WB_FREE to correct place
WB_FREE should be put after all engines's hw_fini
done, otherwise the invalid wptr/rptr_addr would still
be used by engines which trigger abnormal bugs.
This fixes couple DMAR reading error in host side for SRIOV
after guest kmd is unloaded.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 23 Jan 2018 10:29:22 +0000 (18:29 +0800)]
drm/amdgpu: change gfx9 ib test to use WB
two reasons to switch SCRATCH reg method to WB method:
1)Because when doing IB test we don't want to involve KIQ health
status affect, and since SCRATCH register access is go through
KIQ that way GFX IB test would failed due to KIQ fail.
2)acccessing SCRATCH register cost much more time than WB method
because SCRATCH register access runs through KIQ which at least could
begin after GPU world switch back to current Guest VF
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Fri, 19 Jan 2018 11:06:31 +0000 (19:06 +0800)]
drm/amdgpu: cond_exec only for schedule with a job
issue:
under SR-IOV sometimes the iB test will fail on
gfx ring
fix:
with cond_exec inserted in RB the gfx engine would
skip part packets if RLCV issue PREEMPT on gfx engine
if gfx engine is prior to COND_EXEC packet, this is
okay for regular command from UMD, but for the ib test
since the whole dma format doesn't support PREEMPT
so must remove the COND_EXEC from it.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Fri, 19 Jan 2018 11:02:16 +0000 (19:02 +0800)]
drm/amdgpu: only flush hotplug work without DC
since hotplug_work is initialized under the case of
no dc support
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Thu, 18 Jan 2018 08:58:04 +0000 (16:58 +0800)]
drm/amdgpu: skip ECC for SRIOV in gmc late_init
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Fri, 29 Dec 2017 09:06:41 +0000 (17:06 +0800)]
drm/amdgpu: fix&cleanups for wb_clear
fix:
should do right shift on wb before clearing
cleanups:
1,should memset all wb buffer
2,set max wb number to 128 (total 4KB) is big enough
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 26 Feb 2018 18:34:13 +0000 (13:34 -0500)]
drm/amdgpu/powerplay/smu7: use proper dep table for mclk
For mclk od, use the vdd dependency on mclk table. Looks
like a cut and paste typo.
Reviewed-by: Rex Zhu<rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Mon, 26 Feb 2018 14:09:26 +0000 (09:09 -0500)]
drm/amd/amdgpu: Correct VRAM width for APUs with GMC9
DDR4 has a 64-bit width not 128-bits. It was reporting
twice the width. Tested with my Ryzen 2400G.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 22 Feb 2018 07:54:57 +0000 (08:54 +0100)]
drm/ttm: cleanup ttm_tt_create
Cleanup ttm_tt_create a bit.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Roger He <Hongbo.He@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 22 Feb 2018 07:54:57 +0000 (08:54 +0100)]
drm/ttm: move ttm_tt_create into ttm_tt.c v2
Rename ttm_bo_add_ttm to ttm_tt_create and move it into ttm_tt.c.
v2: separate the cleanup.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Roger He <Hongbo.He@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roger He [Mon, 5 Feb 2018 09:57:07 +0000 (17:57 +0800)]
drm/ttm: check if free mem space is under the lower limit
the free mem space and the lower limit both include two parts:
system memory and swap space.
For the OOM triggered by TTM, that is the case as below:
first swap space is full of swapped out pages and soon
system memory also is filled up with ttm pages. and then
any memory allocation request will run into OOM.
to cover two cases:
a. if no swap disk at all or free swap space is under swap mem
limit but available system mem is bigger than sys mem limit,
allow TTM allocation;
b. if the available system mem is less than sys mem limit but
free swap space is bigger than swap mem limit, allow TTM
allocation.
v2: merge two memory limit(swap and system) into one
v3: keep original behavior except ttm_opt_ctx->flags with
TTM_OPT_FLAG_FORCE_ALLOC
v4: always set force_alloc as tx->flags & TTM_OPT_FLAG_FORCE_ALLOC
v5: add an attribute for lower_mem_limit
v6: set lower_mem_limit as 0 to keep original behavior
Signed-off-by: Roger He <Hongbo.He@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 22 Feb 2018 14:52:31 +0000 (15:52 +0100)]
drm/ttm: drop persistent_swap_storage from ttm_bo_init and co
Never used as parameter, the only driver actually using this is nouveau
and there it is initialized after the BO is initialized.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 21 Feb 2018 19:34:13 +0000 (20:34 +0100)]
drm/ttm: drop ttm->dummy_read_page
Only used by the AGP backend and there it can be easily accessed using
ttm->bdev->glob.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 21 Feb 2018 18:02:06 +0000 (19:02 +0100)]
drm/ttm: drop ttm->glob
The pointer is available as ttm->bdev->glob as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 21 Feb 2018 16:26:45 +0000 (17:26 +0100)]
drm/ttm: drop bo->glob
The pointer is available as bo->bdev->glob as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 22 Feb 2018 13:53:42 +0000 (14:53 +0100)]
staging: vboxvideo: remove ttm_pool_* wrappers
TTM calls the default implementation now.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 22 Feb 2018 11:12:41 +0000 (12:12 +0100)]
drm/bochs: remove the default ttm_tt_populate callbacks
TTM calls the default implementation now.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 22 Feb 2018 11:11:25 +0000 (12:11 +0100)]
drm/cirrus: remove ttm_pool_* wrappers
TTM calls the default implementation now.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 22 Feb 2018 11:06:59 +0000 (12:06 +0100)]
drm/qxl: remove ttm_pool_* wrappers
TTM calls the default implementation now.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 22 Feb 2018 11:05:09 +0000 (12:05 +0100)]
drm/ast: remove ttm_pool_* wrappers
TTM calls the default implementation now.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 22 Feb 2018 11:03:58 +0000 (12:03 +0100)]
drm/hisilicon: remove ttm_pool_* wrappers
TTM calls the default implementation now.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>