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Alexander Graf [Wed, 31 Aug 2011 13:13:41 +0000 (15:13 +0200)]
KVM: Update kernel headers
Another round of KVM features, another round of kernel header updates :)
Signed-off-by: Alexander Graf <agraf@suse.de>
Nishanth Aravamudan [Wed, 10 Aug 2011 16:36:27 +0000 (16:36 +0000)]
pseries: use macro for firmware filename
For some time we've had a nicely defined macro with the filename for our
firmware image. However we didn't actually use it in the place we're
supposed to. This patch fixes it.
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
David Gibson [Wed, 10 Aug 2011 14:44:20 +0000 (14:44 +0000)]
pseries: Add real mode debugging hcalls
PAPR systems support several hypercalls intended for use in real mode
debugging tools. These implement reads and writes to arbitrary guest
physical addresses. This is useful for real mode software because it
allows access to IO addresses and memory outside the RMA without going
through the somewhat involved process of setting up the hash page table
and enabling translation.
We want these so that when we add real IO devices, the SLOF firmware can
boot from them without having to enter virtual mode.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Elie Richa [Fri, 22 Jul 2011 05:58:39 +0000 (05:58 +0000)]
PPC: Fix sync instructions problem in SMP
In the current emulation of the load-and-reserve (lwarx) and
store-conditional (stwcx.) instructions, the internal reservation
mechanism is taken into account, however each CPU has its own
reservation information and this information is not synchronized between
CPUs to perform proper synchronization.
The following test case with 2 CPUs shows that the semantics of the
"lwarx" and "stwcx." instructions are not preserved by the emulation.
The test case does the following :
- CPU0: reserve a memory location
- CPU1: reserve the same memory location
- CPU0: perform stwcx. on the location
The last store-conditional operation succeeds while it is supposed to
fail since the reservation was supposed to be lost at the second reserve
operation.
This (one line) patch fixes this problem in a very simple manner by
removing the reservation of a CPU every time it is scheduled (in
cpu_exec()). While this is a harsh workaround, it does not affect the
guest code much because reservations are usually held for a very short
time, that is an lwarx is almost always followed by an stwcx. a few
instructions below. Therefore, in most cases, the reservation will be
taken and consumed before a CPU switch occurs. However in the rare case
where a CPU switch does occur between the lwarx and its corresponding
stwcx. this patch solves a potential erroneous behavior of the
synchronization instructions.
Signed-off-by: Elie Richa <richa@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
David Gibson [Wed, 3 Aug 2011 21:02:19 +0000 (21:02 +0000)]
pseries: More complete WIMG validation in H_ENTER code
Currently our implementation of the H_ENTER hypercall, which inserts a
mapping in the hash page table assumes that only ordinary memory is ever
mapped, and only permits mapping attribute bits accordingly (WIMG==0010).
However, we intend to start adding emulated IO to the pseries platform
(and real IO with PCI passthrough on kvm) which means this simple test
will no longer suffice.
This patch extends the h_enter validation code to check if the given
address is a RAM address. If it is it enforces WIMG==0010, otherwise
it assumes that it is an IO mapping and instead enforces WIMG=010x.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
David Gibson [Wed, 3 Aug 2011 21:02:18 +0000 (21:02 +0000)]
pseries: interrupt controller should not have a 'reg' property
The interrupt controller presented in the device tree for the pseries
machine is manipulated by the guest only through hypervisor calls. It
has no real or emulated registers for the guest to access.
However, it currently has a bogus 'reg' property advertising a register
window. Moreover, this property has an invalid format, being a 32-bit
zero, when the #address-cells property on the root bus indicates that it
needs a 64-bit address. Since the guest never attempts to manipulate
the node directly, it works, but it is ugly and can cause warnings when
manipulating the device tree in other tools (such as future firmware
versions).
This patch, therefore, corrects the problem by entirely removing the
interrupt-controller node's 'reg' property.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
David Gibson [Wed, 3 Aug 2011 21:02:17 +0000 (21:02 +0000)]
pseries: Add a phandle to the xicp interrupt controller device tree node
Future devices we will be adding to the pseries machine (e.g. PCI) will
need nodes in the device tree which explicitly reference the top-level
interrupt controller via interrupt-parent or interrupt-map properties.
In order to do this, the interrupt controller node needs an assigned
phandle. This patch adds the appropriate property, in preparation.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
David Gibson [Wed, 3 Aug 2011 21:02:14 +0000 (21:02 +0000)]
pseries: Bugfixes for interrupt numbering in XICS code
The implementation of the XICS interrupt controller contains several
(difficult to trigger) bugs due to the fact that we were not 100%
consistent with which irq numbering we used. In most places, global
numbers were used as handled by the presentation layer, however a few
functions took "local" numberings, that is the source number within
the interrupt source controller which is offset from the global
number. In most cases the function and its caller agreed on this, but
in a few cases it didn't.
This patch cleans this up by always using global numbering.
Translation to the local number is now always and only done when we
look up the individual interrupt source state structure. This should
remove the existing bugs and with luck reduce the chances of
re-introducing such bugs.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Tue, 9 Aug 2011 16:07:13 +0000 (18:07 +0200)]
PPC: SPAPR: Use KVM function for time info
One of the things we can't fake on PPC is the timer speed. So
we need to extract the frequency information from the host and
put it back into the guest device tree.
Luckily, we already have functions for that from the non-pseries
targets, so all we need to do is to connect the dots and the guest
suddenly gets to know its real timer speeds.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Tue, 9 Aug 2011 15:57:37 +0000 (17:57 +0200)]
PPC: Enable to use PAPR with PR style KVM
When running PR style KVM, we need to tell the kernel that we want
to run in PAPR mode now. This means that we need to pass some more
register information down and enable papr mode. We also need to align
the HTAB to htab_size boundary.
Using this patch, -M pseries works with kvm even on non-hv kvm
implementations, as long as the preceding kernel patches are in.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
v1 -> v2:
- match on CONFIG_PSERIES
v2 -> v3:
- remove HIOR pieces from PAPR patch (ABI breakage)
Alexander Graf [Tue, 9 Aug 2011 12:02:19 +0000 (14:02 +0200)]
KVM: update kernel headers
This patch updates the kvm kernel headers to the latest version.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 10 Aug 2011 12:21:41 +0000 (14:21 +0200)]
PPC: Add new target config for pseries
We only support -M pseries when certain prerequisites are met, such
as a PPC64 guest and libfdt. To only gather these requirements in
a single place, this patch introduces a new CONFIG_PSERIES variable
that gets set when all prerequisites are met.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jul 2011 23:45:37 +0000 (01:45 +0200)]
PPC: E500: Bump CPU count to 15
Now that we have everything in place, make the machine description
aware of the fact that we can now handle 15 virtual CPUs!
Signed-off-by: Alexander Graf <agraf@suse.de>
---
v1 -> v2:
- Max cpus is 15 because of MPIC
Alexander Graf [Sat, 23 Jul 2011 08:56:40 +0000 (10:56 +0200)]
MPC8544DS: Generate CPU nodes on init
With this patch, we generate CPU nodes in the machine initialization, giving
us the freedom to generate as many nodes as we want and as the machine supports,
but only those.
This is a first step towards a much cleaner device tree generation
infrastructure, where we would not require precompiled dtb blobs anymore.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sat, 23 Jul 2011 08:55:50 +0000 (10:55 +0200)]
MPC8544DS: Remove CPU nodes
We want to generate the CPU nodes in machine init code, so remove them from
the device tree definition that we precompile.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sat, 23 Jul 2011 08:54:11 +0000 (10:54 +0200)]
device tree: give dt more size
We currently load a device tree blob and then just take its size x2 to
account for modifications we do inside. While this is nice and great,
it fails when we have a small device tree as blob and lots of nodes added
in machine init code.
So for now, just make it 20k bigger than it was before. We maybe want to
be more clever about this later.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sat, 23 Jul 2011 08:52:00 +0000 (10:52 +0200)]
device tree: dont fail operations
When we screw up and issue an FDT command that doesn't work, we really need to
know immediately and usually can't continue to create the machine. To make sure
we don't need to add error checking in all device tree modification code users,
we can just add the fail checks to the qemu abstract functions.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Fri, 22 Jul 2011 11:55:37 +0000 (13:55 +0200)]
device tree: add add_subnode command
We want to be able to create subnodes in our device tree, so export it through
the qemu device tree abstraction framework.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 21 Jul 2011 01:06:12 +0000 (03:06 +0200)]
PPC: E500: Update cpu-release-addr property in cpu nodes
The guest OS wants to know where the guest spins, so let's tell him while
updating the CPU nodes with the frequencies anyways.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
v1 -> v2:
- use new spin table address
Alexander Graf [Fri, 22 Jul 2011 11:32:29 +0000 (13:32 +0200)]
PPC: E500: Add PV spinning code
CPUs that are not the boot CPU need to run in spinning code to check if they
should run off to execute and if so where to jump to. This usually happens
by leaving secondary CPUs looping and checking if some variable in memory
changed.
In an environment like Qemu however we can be more clever. We can just export
the spin table the primary CPU modifies as MMIO region that would event based
wake up the respective secondary CPUs. That saves us quite some cycles while
the secondary CPUs are not up yet.
So this patch adds a PV device that simply exports the spinning table into the
guest and thus allows the primary CPU to wake up secondary ones.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
v1 -> v2:
- change into MMIO scheme
- map the secondary NIP instead of 0 1:1
- only map 64MB for TLB, same as u-boot
- prepare code for 64-bit spinnings
v2 -> v3:
- remove r6
- set MAS2_M
- map EA 0
- use second TLB1 entry
v3 -> v4:
- change to memoryops
v4 -> v5:
- fix endianness bugs
v5 -> v6:
- add header
Alexander Graf [Thu, 21 Jul 2011 01:02:31 +0000 (03:02 +0200)]
PPC: E500: Remove unneeded CPU nodes
We should only keep CPU nodes in the device tree around that we really have
virtual CPUs for. So remove all superfluous entries that we just keep there
in case someone wants to create a lot of vCPUs.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 21 Jul 2011 01:01:11 +0000 (03:01 +0200)]
PPC: E500: Update freqs for all CPUs
Now that we can so nicely find out the host's frequencies, we should also
make sure that we get them into all virtual CPUs' device tree nodes.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 21 Jul 2011 00:54:51 +0000 (02:54 +0200)]
PPC: KVM: Add stubs for kvm helper functions
We have a bunch of helper functions that don't have any stubs for them in case
we don't have CONFIG_KVM enabled. That didn't bite us so far, because gcc can
optimize them out pretty well, but we should really provide them.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
v1 -> v2:
- use uint64_t for clockfreq
Alexander Graf [Thu, 21 Jul 2011 00:46:11 +0000 (02:46 +0200)]
PPC: KVM: Remove kvmppc_read_host_property
We just got rid of the last user of kvmppc_read_host_property, so we
can now safely remove it.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 21 Jul 2011 00:44:53 +0000 (02:44 +0200)]
PPC: bamboo: Use kvm api for freq and clock frequencies
Now that we have nice and shiny APIs to read out the host's clock and timebase
frequencies, let's use them in the bamboo code as well!
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 21 Jul 2011 00:35:28 +0000 (02:35 +0200)]
PPC: E500: Remove mpc8544_copy_soc_cell
We don't need mpc8544_copy_soc_cell anymore, since we're explicitly reading
host values and writing guest values respectively.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 21 Jul 2011 00:34:11 +0000 (02:34 +0200)]
PPC: E500: Use generic kvm function for freq
Now that we have generic KVM functions to read out the host tb and clock
frequencies, let's use them in the e500 code!
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 21 Jul 2011 00:29:15 +0000 (02:29 +0200)]
PPC: KVM: Add generic function to read host clockfreq
We need to find out the host's clock-frequency when running on KVM, so
let's export a respective function.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
v1 -> v2:
- enable 64bit values
Alexander Graf [Thu, 21 Jul 2011 00:08:10 +0000 (02:08 +0200)]
PPC: bamboo: Move host fdt copy to target
We have some code in generic kvm_ppc.c that is only used by 440. Move to
the 440 specific device code.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jul 2011 23:52:57 +0000 (01:52 +0200)]
device tree: add nop_node
We have a qemu internal abstraction layer on FDT. While I'm not fully convinced
we need it at all, it's missing the nop_node functionality that we now need
on e500. So let's add it and think about the general future of that API later.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jul 2011 23:42:58 +0000 (01:42 +0200)]
PPC: E500: Generate IRQ lines for many CPUs
Now that we can generate multiple envs for all our virtual CPUs, we
also need to tell the MPIC that we have multiple CPUs connected and
connect them all to the respective virtual interrupt lines.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jul 2011 23:41:16 +0000 (01:41 +0200)]
PPC: E500: create multiple envs
When creating a VM, we should go through smp_cpus and create a virtual CPU for
every CPU the user requested. This patch adds support for that and moves some
code around to make that more convenient.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jul 2011 23:39:46 +0000 (01:39 +0200)]
PPC: Bump MPIC up to 32 supported CPUs
The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that in
the code exporting the numbers out and fix an integer overflow while at it.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
v1 -> v2:
- Max cpus is 15 due to cINT routing
- Report nb_cpus not MAX_CPUS in MPIC capabilities
Alexander Graf [Sat, 23 Jul 2011 09:27:53 +0000 (11:27 +0200)]
PPC: MPIC: Fix CI bit definitions
The bit definitions for critical interrupt routing are in PowerPC order
(most significant bit is 0), while we end up shifting it with normal bit
order. Turn the numbers around so we actually end up fetching the
right ones.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sat, 23 Jul 2011 09:09:23 +0000 (11:09 +0200)]
PPC: MPIC: Remove read functionality for WO registers
The IPI dispatch registers are write only according to every MPIC
spec I have found. So instead of pretending you could read back something
from them, better not handle them at all.
Reported-by: Elie Richa <richa@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sat, 23 Jul 2011 09:05:35 +0000 (11:05 +0200)]
PPC: Set MPIC IDE for IPI to 0
We use the IDE register with IPIs as a mask to keep track which processors
have already acknowledged the respective interrupt. So we need to initialize
it to 0 to make sure that it doesn't accidently fire an IPI on CPU0 when the
first IPI is triggered.
Reported-by: Elie Richa <richa@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
v2 -> v3:
- fix IDE IPI reset
Alexander Graf [Wed, 20 Jul 2011 23:36:44 +0000 (01:36 +0200)]
PPC: Fix IPI support in MPIC
The current IPI support in the MPIC code is incomplete and doesn't work. This
code adds proper support for IPIs in MPIC by using the IDE register to remember
which CPUs IPIs are still outstanding to. New triggers through the IPI trigger
register only add to the list of CPUs we want to IPI.
Signed-off-by: Alexander Graf <agraf@suse.de>
---
v1 -> v2:
- Use MAX_IPI instead of hardcoded 4
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jul 2011 23:35:15 +0000 (01:35 +0200)]
PPC: Extend MPIC MMIO range
The MPIC exports a page for each CPU that it controls. To support more than
one CPU, we need to also reserve the MMIO space according to the amount of
CPUs we want to support.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jul 2011 23:33:29 +0000 (01:33 +0200)]
PPC: Add CPU local MMIO regions to MPIC
The MPIC exports a register set for each CPU connected to it. They can all
be accessed through specific registers or using a shadow page that is mapped
differently depending on which CPU accesses it.
This patch implements the shadow map, making it possible for guests to access
the CPU local registers using the same address on each CPU.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jul 2011 22:49:45 +0000 (00:49 +0200)]
PPC: Move openpic to target specific code compilation
The MPIC has some funny feature where it maps different registers to an MMIO
region depending which CPU accesses them.
To be able to reflect that, we need to make OpenPIC be compiled in the target
code, so it can access cpu_single_env.
Signed-off-by: Alexander Graf <agraf@suse.de>
Paolo Bonzini [Thu, 26 May 2011 09:52:46 +0000 (11:52 +0200)]
spapr: make irq customizable via qdev
This also lets the user see the irq in "info qtree".
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
Paolo Bonzini [Thu, 26 May 2011 09:52:45 +0000 (11:52 +0200)]
spapr: prepare for qdevification of irq
Restructure common properties for sPAPR devices so that IRQ definitions
can be added in one place.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
Paolo Bonzini [Thu, 26 May 2011 09:52:44 +0000 (11:52 +0200)]
spapr: proper qdevification
Right now the spapr devices cannot be instantiated with -device,
because the IRQs need to be passed to the spapr_*_create functions.
Do this instead in the bus's init wrapper.
This is particularly important with the conversion from scsi-disk
to scsi-{cd,hd} that Markus made. After his patches, if you
specify a scsi-cd device attached to an if=none drive, the default
VSCSI controller will not be created and, without qdevification,
you will not be able to add yours.
NOTE from agraf: added small compile fix
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
Stefan Hajnoczi [Fri, 30 Sep 2011 10:39:11 +0000 (11:39 +0100)]
qed: fix use-after-free during l2 cache commit
QED's metadata caching strategy allows two parallel requests to race for
metadata lookup. The first one to complete will populate the metadata
cache and the second one will drop the data it just read in favor of the
cached data.
There is a use-after-free in qed_read_l2_table_cb() and
qed_commit_l2_update() where l2_table->offset was used after the
l2_table may have been freed due to a metadata lookup race. Fix this by
keeping the l2_offset in a local variable and not reaching into the
possibly freed l2_table.
Reported-by: Amit Shah <amit.shah@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Edgar E. Iglesias [Mon, 3 Oct 2011 08:20:13 +0000 (10:20 +0200)]
etrax-dma: Remove bogus if statement
Reported-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Jan Kiszka [Tue, 27 Sep 2011 13:00:41 +0000 (15:00 +0200)]
memory: Print regions in ascending order
Makes reading the output more user friendly.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Jan Kiszka [Tue, 27 Sep 2011 13:00:38 +0000 (15:00 +0200)]
memory: Do not print empty PIO root
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Jan Kiszka [Tue, 27 Sep 2011 13:00:31 +0000 (15:00 +0200)]
memory: Print region priority
Useful to discover eclipses.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Blue Swirl [Sun, 11 Sep 2011 20:22:05 +0000 (20:22 +0000)]
memory: simple memory tree printer
Add a monitor command 'info mtree' to show the memory hierarchy
much like /proc/iomem in Linux.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Blue Swirl [Wed, 21 Sep 2011 18:13:16 +0000 (18:13 +0000)]
Move GETPC from dyngen-exec.h to exec-all.h
GETPC() can be used even from outside of helper code. Move the macro to
a more accessible location. Avoid a compile warning from redefining it in exec.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Blue Swirl [Mon, 4 Jul 2011 20:57:05 +0000 (20:57 +0000)]
softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture local
cpu_single_env hacks.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Blue Swirl [Wed, 21 Sep 2011 20:00:18 +0000 (20:00 +0000)]
Document softmmu templates
Add some comments to describe each file.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Blue Swirl [Sun, 11 Sep 2011 15:54:18 +0000 (15:54 +0000)]
ESP: convert to trace framework
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Alexander Graf [Fri, 30 Sep 2011 13:29:12 +0000 (15:29 +0200)]
PPC: Drop initial ESCC mapping
We are mapping ESCC to a static (incorrect) address on machine init. This
overlaps with our vram, rendering the screen barely usable.
Since openBIOS is clever enough to map ESCC to where it needs to be, we can
just drop that invalid map and everyone's happy.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Jan Kiszka [Thu, 29 Sep 2011 16:52:11 +0000 (18:52 +0200)]
tcg-i386: Introduce limited deposit support
x86 cannot provide an optimized generic deposit implementation. But at
least for a few special cases, namely for writing bits 0..7, 8..15, and
0..15, versions using only a single instruction are feasible.
Introducing such limited support improves emulating 16-bit x86 code on
x86, but also rarer cases where 32-bit or 64-bit code accesses bytes or
words.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Jan Kiszka [Wed, 28 Sep 2011 09:19:02 +0000 (11:19 +0200)]
mips_fulong2e: Reorder ISA bus and i8259 creation
Missed during memory region conversion: The i8259 now depends on the ISA
bus being created first. Reorder the initialization.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Jan Kiszka [Mon, 26 Sep 2011 17:20:00 +0000 (19:20 +0200)]
target-i386: Remove redundant word mask in port out instructions
T0 was already masked to 16 bits when loading it.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Peter Maydell [Mon, 26 Sep 2011 15:56:55 +0000 (16:56 +0100)]
softfloat: Reinstate accidentally disabled target-specific NaN handling
Include config.h in softfloat.c, so that the target specific ifdefs in
softfloat-specialize.h are evaluated correctly. This was accidentally
broken in commit
789ec7ce2 when config-target.h was removed from
softfloat.h, and means that most targets will have been returning the
wrong results for calculations involving NaNs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Peter Maydell [Mon, 12 Sep 2011 10:03:45 +0000 (11:03 +0100)]
tcg/arm: Remove unused tcg_out_addi()
Remove the unused function tcg_out_addi() from the ARM TCG backend;
this fixes a compilation failure on ARM hosts with newer gcc.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Brad [Thu, 8 Sep 2011 01:24:56 +0000 (21:24 -0400)]
configure: Detect predefined compiler symbols for ARM and HPPA
To be able to detect some ARM / HPPA based architectures such as with
OpenBSD/(armish / zaurus) or OpenBSD/hppa.
Signed-off-by: Brad Smith <brad@comstyle.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Stefan Weil [Sat, 17 Sep 2011 20:00:30 +0000 (22:00 +0200)]
tcg: Add some assertions
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Stefan Weil [Sat, 17 Sep 2011 20:00:29 +0000 (22:00 +0200)]
tcg: Add forward declarations for local functions
These functions are defined in the tcg target specific file
tcg-target.c.
The forward declarations assert that every tcg target uses
the same function prototype.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Stefan Weil [Sat, 17 Sep 2011 20:00:28 +0000 (22:00 +0200)]
tcg: Don't declare TCG_TARGET_REG_BITS in tcg-target.h
It is now declared for all tcg targets in tcg.h,
so the tcg target specific declarations are redundant.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Stefan Weil [Sat, 17 Sep 2011 20:00:27 +0000 (22:00 +0200)]
tcg: Declare TCG_TARGET_REG_BITS in tcg.h
TCG_TARGET_REG_BITS can be determined by the compiler,
so there is no need to declare it for each individual tcg target.
This is especially important for new tcg targets
which will be supported by the tcg interpreter.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Anthony Liguori [Thu, 29 Sep 2011 18:33:47 +0000 (13:33 -0500)]
Merge remote-tracking branch 'kiszka/queues/slirp' into staging
Anthony Liguori [Thu, 29 Sep 2011 18:32:05 +0000 (13:32 -0500)]
Merge remote-tracking branch 'aneesh/for-upstream-5' into staging
Blue Swirl [Mon, 29 Aug 2011 21:13:29 +0000 (21:13 +0000)]
Add OpenBIOS as a submodule
Update OpenBIOS images to r1047 built from submodule.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Thomas Huth [Tue, 27 Sep 2011 09:20:38 +0000 (11:20 +0200)]
slirp: Fix packet expiration
The two new variables "arp_requested" and "expiration_date" in the mbuf
structure have been added after the variable-sized "m_dat_" array. The
variables have to be added before the m_dat_ array instead.
Without this patch, the expiration_date gets clobbered by code that
accesses the m_dat_ array.
I experienced this problem with the code in slirp/tftp.c: The
tftp_send_data() function created a new packet with the m_get()
function (which fills-in a default expiration_date value). Then the
TFTP code cleared the data section of the packet, which accidentially
also cleared the expiration_date. This zeroed expiration_date then
finally causes the packet to be discarded during if_start(), so that
TFTP packets were not transmitted anymore.
[Jan: added comment as suggested by Fabien ]
CC: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Mon, 26 Sep 2011 19:29:56 +0000 (21:29 +0200)]
slirp: Fix use after release on tcp_input
ti points into the m buffer. But the latter may already be released
right after the dodata: label. Move the test before the potential
release.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Blue Swirl [Sat, 17 Sep 2011 20:30:50 +0000 (20:30 +0000)]
PPC: use memory API to construct the PCI hole
Avoid vga.chain4 mapping by constructing a PCI hole for upper
2G of the PCI space.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Anthony Liguori [Mon, 26 Sep 2011 13:00:47 +0000 (08:00 -0500)]
Merge remote-tracking branch 'qemu-kvm-tmp/memory/urgent' into staging
Anthony Liguori [Mon, 26 Sep 2011 13:00:40 +0000 (08:00 -0500)]
Merge remote-tracking branch 'qemu-kvm-tmp/memory/batch' into staging
Anthony Liguori [Mon, 26 Sep 2011 13:00:29 +0000 (08:00 -0500)]
Merge remote-tracking branch 'qemu-kvm-tmp/memory/core' into staging
Anthony Liguori [Mon, 26 Sep 2011 13:00:00 +0000 (08:00 -0500)]
Merge remote-tracking branch 'pmaydell/omap-for-upstream' into staging
Anthony Liguori [Mon, 26 Sep 2011 12:59:13 +0000 (07:59 -0500)]
Merge remote-tracking branch 'riku/linux-user-for-upstream' into staging
Avi Kivity [Sun, 25 Sep 2011 14:15:43 +0000 (17:15 +0300)]
ppc_prep: fix pci config space initialization
Use data_mem for the data mmio region, not conf_mem.
Signed-off-by: Avi Kivity <avi@redhat.com>
Richard Henderson [Wed, 10 Aug 2011 22:28:20 +0000 (15:28 -0700)]
fdc: Convert isabus_fdc_init1 to MemoryRegion
This requires some amount of hoop-jumping, so that we don't
inadvertently claim port 0x3f6, which is used by ISA IDE.
The sysbus initialization path is as yet unconverted.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Richard Henderson [Wed, 10 Aug 2011 22:28:18 +0000 (15:28 -0700)]
serial: Convert serial_isa_initfn to MemoryRegion
The serial_mm_init path is as yet unconverted.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Richard Henderson [Wed, 10 Aug 2011 22:28:17 +0000 (15:28 -0700)]
pckbd: Convert to MemoryRegion
Slightly non-obvious with mips_jazz passing in the region
structure to populate.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Richard Henderson [Wed, 10 Aug 2011 22:28:16 +0000 (15:28 -0700)]
i8259: Convert to MemoryRegion
The only non-obvious part is pic_poll_read which used
"addr1 >> 7" to detect whether one referred to either
the master or slave PIC. Instead, test this directly.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Avi Kivity [Sun, 18 Sep 2011 13:13:38 +0000 (16:13 +0300)]
ppc_prep: initialize i8259 after the ISA bus
Succeeding i8259 conversion to ISA requires this.
Signed-off-by: Avi Kivity <avi@redhat.com>
Avi Kivity [Sun, 18 Sep 2011 13:13:38 +0000 (16:13 +0300)]
mips_r4k: initialize i8259 after the ISA bus
Succeeding i8259 conversion to ISA requires this.
Signed-off-by: Avi Kivity <avi@redhat.com>
Avi Kivity [Sun, 18 Sep 2011 13:13:38 +0000 (16:13 +0300)]
mips_jazz: initialize i8259 after the ISA bus
Succeeding i8259 conversion to ISA requires this.
Signed-off-by: Avi Kivity <avi@redhat.com>
Avi Kivity [Mon, 12 Sep 2011 10:00:05 +0000 (13:00 +0300)]
mips_malta: move i8259 initialization after piix4 initialization
i8259 is an ISA device (or at least, depends on the ISA infrastructure to
register its ioport); and the ISA bus is supplied by piix4. Later patches
make this dependency explicit.
Use qemu_irq_proxy() to stop the cycle by adding an extra layer of
indirection.
Signed-off-by: Avi Kivity <avi@redhat.com>
Richard Henderson [Wed, 10 Aug 2011 22:28:15 +0000 (15:28 -0700)]
i8254: Convert to MemoryRegion
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Richard Henderson [Wed, 10 Aug 2011 22:28:14 +0000 (15:28 -0700)]
cs4231a: Convert to MemoryRegion
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Richard Henderson [Wed, 10 Aug 2011 22:28:13 +0000 (15:28 -0700)]
pc: Re-order pc_init1 to initialize the ISA bus before ISA devices
In particular, the i8259 was being initialized before the ISA bus,
leading to a crash.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Richard Henderson [Wed, 10 Aug 2011 22:28:12 +0000 (15:28 -0700)]
isa: add isa_register_ioport()
To replace isa_init_ioport and isa_init_ioport_range
as the ISA devices are converted to the memory api.
[avi: use memory_region_size()]
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Richard Henderson [Wed, 10 Aug 2011 22:28:11 +0000 (15:28 -0700)]
isa: Pass i/o address space to isa_bus_new
Not used yet, but at least we're provided with the correct region.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Richard Henderson [Wed, 10 Aug 2011 22:28:10 +0000 (15:28 -0700)]
pci: add pci_address_space_io()
Returns the I/O address space. Useful for implementing
PCI-ISA bridge devices.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Avi Kivity [Sun, 25 Sep 2011 11:48:47 +0000 (14:48 +0300)]
memory: implement memory_region_set_readonly()
The property is inheritable, but only if set to true. This is so
that memory routers can mark sections of RAM as read-only via aliases.
Signed-off-by: Avi Kivity <avi@redhat.com>
Peter Maydell [Tue, 20 Sep 2011 15:18:46 +0000 (16:18 +0100)]
MAINTAINERS: update maintainer for target-arm and ARM devboards
Add myself as co-maintainer alongside Paul Brook for the TCG ARM
guest implementation (target-arm) and the ARM dev boards (integratorcp,
realview, stellaris, versatilepb).
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Peter Maydell [Fri, 16 Sep 2011 14:40:16 +0000 (15:40 +0100)]
Makefile: Remove 'tarbin' target
Remove the 'tarbin' target -- it isn't used as part of the official
QEMU release process, and it's out of date (various new bios files
were never added to its list of files). It's better not to provide
it at all than to have a broken makefile target we never use or test.
(Creating a tarball by just pulling in binaries that have been installed
directly to the system you're running the build on is a bad idea anyway:
the better way to create a binary tarball would be just to install to
a temporary DESTDIR and then tar up that.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Marcelo Tosatti [Fri, 16 Sep 2011 21:19:55 +0000 (18:19 -0300)]
qemu-char: use qemu_set_fd_handler/2 consistently
Now that qemu_set_fd_handler and qemu_set_fd_handler2 have different
implementations, one using qemu iohandlers and the other glib, it is not
safe to mix the two when inserting/deleting handlers.
Fixes kvm-autotest.
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Hervé Poussineau [Sun, 18 Sep 2011 14:27:23 +0000 (16:27 +0200)]
adlib: remove write-only variable
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Avi Kivity [Sun, 18 Sep 2011 12:58:26 +0000 (15:58 +0300)]
irq: introduce qemu_irq_proxy()
In some cases we have a circular dependency involving irqs - the irq
controller depends on a bus, which in turn depends on the irq controller.
Add qemu_irq_proxy() which acts as a passthrough, except that the target
irq may be set later on.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
David Gibson [Tue, 20 Sep 2011 02:05:21 +0000 (12:05 +1000)]
Barriers in qemu-barrier.h should not be x86 specific
qemu-barrier.h contains a few macros implementing memory barrier
primitives used in several places throughout qemu. However, apart
from the compiler-only barrier, the defined wmb() is correct only for
x86, or platforms which are similarly strongly ordered.
This patch addresses the FIXME about this by making the wmb() macro
arch dependent. On x86, it remains a compiler barrier only, but with
a comment explaining in more detail the conditions under which this is
correct. On weakly-ordered powerpc, an "eieio" instruction is used,
again with explanation of the conditions under which it is sufficient.
On other platforms, we use the __sync_synchronize() primitive,
available in sufficiently recent gcc (4.2 and after?). This should
implement a full barrier which will be sufficient on all platforms,
although it may be overkill in some cases. Other platforms can add
optimized versions in future if it's worth it for them.
Without proper memory barriers, it is easy to reproduce ordering
problems with virtio on powerpc; specifically, the QEMU puts new
element into the "used" ring and then updates the ring free-running
counter. Without a barrier between these under the right
circumstances, the guest linux driver can receive an interrupt, read
the counter change but find the ring element to be handled still has
an old value, leading to an "id %u is not a head!\n" error message.
Similar problems are likely to be possible with kvm on other weakly
ordered platforms.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
David Gibson [Tue, 20 Sep 2011 02:05:20 +0000 (12:05 +1000)]
virtio: Use global memory barrier macros
The virtio code uses wmb() macros in several places, as required by the
SMP-aware virtio protocol. However the wmb() macro is locally defined
to be a compiler barrier only. This is probably sufficient on x86
due to its strong storage ordering model, but it certainly isn't on other
platforms, such as ppc.
In any case, qemu already has some globally defined memory barrier macros
in qemu-barrier.h. This patch, therefore converts virtio.c to use those
barrier macros. The macros in qemu-barrier.h are also wrong (or at least,
safe for x86 only) but this way at least there's only one place to fix
them.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Stefan Weil [Fri, 16 Sep 2011 20:03:08 +0000 (22:03 +0200)]
Fix and clean code which tests the gcc version
The code which tests whether gcc supports warn_unused_result was wrong.
Remove the wrong test from configure and replace it by code using
macro QEMU_GNUC_PREREQ in compiler.h.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Stefan Weil [Fri, 16 Sep 2011 20:03:07 +0000 (22:03 +0200)]
Move macro QEMU_GNUC_PREREQ to compiler.h
The macro is compiler specific and does not depend on the operating system.
Move macro QEMU_GNUC_PREREQ from osdep.h to compiler.h
and use it to simplify existing code.
host-utils.h uses this macro, so it now needs compiler.h
instead of osdep.h.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>