OSDN Git Service
Alina Sbirlea [Thu, 8 Mar 2018 18:03:14 +0000 (18:03 +0000)]
Expose must/may alias info in MemorySSA.
Summary:
Building MemorySSA gathers alias information for Defs/Uses.
Store and expose this information when optimizing uses (when building MemorySSA),
and when optimizing defs or updating uses (getClobberingMemoryAccess).
Current patch does not propagate alias information through MemoryPhis.
Reviewers: gbiv, dberlin
Subscribers: Prazek, sanjoy, llvm-commits
Differential Revision: https://reviews.llvm.org/D38569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327035
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Sanjay Patel [Thu, 8 Mar 2018 17:34:25 +0000 (17:34 +0000)]
[AMDGPU] fix test to survive the most basic undef constant folding
This will likely need to be changed again for anything more than:
fmul undef, undef -> undef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327034
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Kuba Mracek [Thu, 8 Mar 2018 17:32:00 +0000 (17:32 +0000)]
Revert r327029
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327033
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Sanjay Patel [Thu, 8 Mar 2018 17:24:30 +0000 (17:24 +0000)]
[x86] fix test to be independent of FP undef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327030
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Kuba Mracek [Thu, 8 Mar 2018 17:24:06 +0000 (17:24 +0000)]
[asan] Fix a false positive ODR violation due to LTO ConstantMerge pass [llvm part]
This fixes a false positive ODR violation that is reported by ASan when using LTO. In cases, where two constant globals have the same value, LTO will merge them, which breaks ASan's ODR detection.
Differential Revision: https://reviews.llvm.org/D43959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327029
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Sanjay Patel [Thu, 8 Mar 2018 17:13:57 +0000 (17:13 +0000)]
[StructurizeCFG] fix test to be independent of FP undef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327028
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Andrea Di Biagio [Thu, 8 Mar 2018 17:02:28 +0000 (17:02 +0000)]
[llvm-mca] add override keyword to method ResourcePressureView::printView().
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327027
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Sanjay Patel [Thu, 8 Mar 2018 16:56:49 +0000 (16:56 +0000)]
[x86] regenerate checks; NFC
This test will fail if we fix FP undef constant folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327026
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Andrea Di Biagio [Thu, 8 Mar 2018 16:34:19 +0000 (16:34 +0000)]
[llvm-mca] HWEventListener is a class, not struct.
This should appease the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327025
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Tom Stellard [Thu, 8 Mar 2018 16:29:08 +0000 (16:29 +0000)]
merge-request.sh: Update 6.0 metabug for 6.0.1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327024
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Sanjay Patel [Thu, 8 Mar 2018 16:25:37 +0000 (16:25 +0000)]
[StructurizeCFG] auto-generate full checks; NFC
Not sure what the intent of this test is, but this will change when we fix FP undef constant folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327022
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Stefan Pintilie [Thu, 8 Mar 2018 16:24:33 +0000 (16:24 +0000)]
[Power9] Add more missing instructions to the Power 9 scheduler
With this patch we should be able to mark the Power 9 model as complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327021
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Matt Arsenault [Thu, 8 Mar 2018 16:24:16 +0000 (16:24 +0000)]
AMDGPU/GlobalISel: Pass subtarget + TM to LegalizerInfo
These are the parameters x86 already uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327020
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Andrea Di Biagio [Thu, 8 Mar 2018 16:08:43 +0000 (16:08 +0000)]
[llvm-mca] Unify the API for the various views. NFCI
This allows the customization of the performance report.
Users can specify their own custom sequence of views.
Each view contributes a portion of the performance report generated by the
BackendPrinter.
Internally, class BackendPrinter keeps a sequence of views; views are printed
out in sequence when method 'printReport()' is called.
This patch addresses one of the two review comments from Clement in D43951.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327018
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Daniel Sanders [Thu, 8 Mar 2018 15:52:45 +0000 (15:52 +0000)]
Fix unused function warning in StatisticTest.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327015
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Sanjay Patel [Thu, 8 Mar 2018 15:46:38 +0000 (15:46 +0000)]
[InstCombine] regenerate checks; NFC
We may not need any of these tests after rL327012, but leaving
them here for now until that's confirmed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327014
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Sanjay Patel [Thu, 8 Mar 2018 15:39:39 +0000 (15:39 +0000)]
[InstSimplify] add more tests for FP undef; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327012
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Pavel Labath [Thu, 8 Mar 2018 15:34:42 +0000 (15:34 +0000)]
DWARFVerifier: Basic verification of .debug_names
Summary:
This patch adds basic .debug_names verification capabilities to the
DWARF verifier. Right now, it checks that the headers and abbreviation
tables of the individual name indexes can be parsed correctly, it
verifies the buckets table and the cross-checks the CU lists for
consistency. I intend to add further checks in follow-up patches.
Reviewers: JDevlieghere, aprantl, probinson, dblaikie
Subscribers: vleschuk, echristo, clayborg, llvm-commits
Differential Revision: https://reviews.llvm.org/D44211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327011
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Andrea Di Biagio [Thu, 8 Mar 2018 15:34:38 +0000 (15:34 +0000)]
[llvm-mca] Emit the 'Instruction Info' table before the resource pressure view.
In future, both the summary information and the 'instruction info' table should
be moved into a separate "Summary" view.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327010
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Michal Gorny [Thu, 8 Mar 2018 15:09:38 +0000 (15:09 +0000)]
[cmake] Append -Wl,-rpath-link conditionally to GNULD
Append -Wl,-rpath-link conditionally to whether GNU ld.bfd is used
rather than the Linux+!gold conditionals. Also move it out of 'else'
branch of *BSD handling. This fixes build failures with ld.bfd
on Gentoo/FreeBSD, and should cause no harm on other systems using
ld.bfd.
This patch improves the original logic by reusing results of linker
detection introduced in r307852.
Differential Revision: https://reviews.llvm.org/D43751
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327007
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Sanjay Patel [Thu, 8 Mar 2018 14:57:08 +0000 (14:57 +0000)]
[InstCombine, NewGVN] remove FP undef from tests
I'm trying to preserve the intent of these tests by using
non-undef operands; if we fix FP undef folding these tests
will not pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327004
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David Zarzycki [Thu, 8 Mar 2018 14:43:24 +0000 (14:43 +0000)]
[CMake] Add missing test dependency
This makes 'ninja clean ; ninja check-all' work again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327002
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Ed Maste [Thu, 8 Mar 2018 13:52:04 +0000 (13:52 +0000)]
Use ellipsis ... to indicate omitted commands
In an example like "clang -fxray-instrument .." the .. could be confused
with a literal .. (parent directory), which is used in commands like
"cmake -GNinja .."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327000
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Andrea Di Biagio [Thu, 8 Mar 2018 13:43:11 +0000 (13:43 +0000)]
Add llvm-mca.rst to the table of contents in docs/CommandGuide.
This should fix the documentation error reported by builder llvm-sphinx-docs
(build #16407) after r326998.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326999
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Andrea Di Biagio [Thu, 8 Mar 2018 13:05:02 +0000 (13:05 +0000)]
[llvm-mca] LLVM Machine Code Analyzer.
llvm-mca is an LLVM based performance analysis tool that can be used to
statically measure the performance of code, and to help triage potential
problems with target scheduling models.
llvm-mca uses information which is already available in LLVM (e.g. scheduling
models) to statically measure the performance of machine code in a specific cpu.
Performance is measured in terms of throughput as well as processor resource
consumption. The tool currently works for processors with an out-of-order
backend, for which there is a scheduling model available in LLVM.
The main goal of this tool is not just to predict the performance of the code
when run on the target, but also help with diagnosing potential performance
issues.
Given an assembly code sequence, llvm-mca estimates the IPC (instructions per
cycle), as well as hardware resources pressure. The analysis and reporting style
were mostly inspired by the IACA tool from Intel.
This patch is related to the RFC on llvm-dev visible at this link:
http://lists.llvm.org/pipermail/llvm-dev/2018-March/121490.html
Differential Revision: https://reviews.llvm.org/D43951
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326998
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James Henderson [Thu, 8 Mar 2018 10:53:34 +0000 (10:53 +0000)]
[DWARF] Don't attempt to parse line tables at invalid offsets
Whilst working on improvements to the error handling of the debug line
parsing code, I noticed that if an invalid offset were to be specified
in a call to getOrParseLineTable(), an entry in the LineTableMap would
still be created, even if the offset was not within the section range.
The immediate parsing attempt afterwards would fail (it would end up
getting a version of 0), and thereafter, any subsequent calls to
getOrParseLineTable or getLineTable would return the default-
constructed, invalid line table. In reality, we shouldn't even attempt
to parse this table, and we should always return a nullptr from these
two functions for this situation.
I have tested this via a unit test, which required some new framework
for unit testing debug line. My plan is to add quite a few more unit
tests for the new error reporting mechanism that will follow shortly,
hence the reason why the supporting code for the tests are written the
way they are - I intend to extend the DwarfGenerator class to support
generating debug line. At that point, I'll make sure that there are a
few positive test cases for this and the parsing code too.
Differential Revision: https://reviews.llvm.org/D44200
Reviewers: JDevlieghere, aprantl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326995
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Jonas Devlieghere [Thu, 8 Mar 2018 10:39:12 +0000 (10:39 +0000)]
[dsymutil] Embed toolchain in dSYM bundle
Allow us to embed the (Xcode) toolchain in the dSYM bundle's property
list.
Differential revision: https://reviews.llvm.org/D44151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326994
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Andrea Di Biagio [Thu, 8 Mar 2018 10:38:45 +0000 (10:38 +0000)]
[MCSchedule] Always generate processor resource names.
With this patch, the tablegen 'SubtargetEmitter' always generates processor
resource names.
The impact of this patch on the code size of other llvm tools is small. I have
observed an average increase of 0.03% in code size when doing a release build of
LLVM (on windows, using MSVC) with all the default backends.
This change is done in preparation for the upcoming llvm-mca patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326993
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Craig Topper [Thu, 8 Mar 2018 08:02:52 +0000 (08:02 +0000)]
[X86] Change X86::PMULDQ/PMULUDQ opcodes to take vXi64 type as input instead of vXi32.
This instruction can be thought of as reading either the even elements of a vXi32 input or the lower half of each element of a vXi64 input. We currently use the vXi32 interpretation, but vXi64 matches better with its broadcast behavior in EVEX.
I'm looking at moving MULDQ/MULUDQ creation to a DAG combine so we can do it when AVX512DQ is enabled without having to go through Custom lowering. But in some of the test cases we failed to use a broadcast load due to the size difference. This should help with that.
I'm also wondering if we can model these instructions in native IR and remove the intrinsics and I think using a vXi64 type will work better with that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326991
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Tony Tye [Thu, 8 Mar 2018 05:46:01 +0000 (05:46 +0000)]
[AMDGPU] Update AMDGOUUsage.rst descriptions
- Improve description of XNACK ELF flag.
- Rename all uses of wave to wavefront to be consistent.
Differential Revision: https://reviews.llvm.org/D43983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326989
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Heejin Ahn [Thu, 8 Mar 2018 04:05:37 +0000 (04:05 +0000)]
[WebAssembly] Add except_ref as a first-class type
Summary: Add except_ref as a first-class type, according to the [[https://github.com/WebAssembly/exception-handling/blob/master/proposals/Level-1.md | Level 1 exception handling proposal ]].
Reviewers: dschuff
Subscribers: jfb, sbc100, llvm-commits
Differential Revision: https://reviews.llvm.org/D43706
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326985
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Heejin Ahn [Thu, 8 Mar 2018 03:47:52 +0000 (03:47 +0000)]
[WebAssembly] Add IntrNoReturn property to throw/rethrow intrinsics
Reviewers: dschuff
Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D43740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326984
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Daniel Sanders [Thu, 8 Mar 2018 02:36:25 +0000 (02:36 +0000)]
Support resetting STATISTIC() values using llvm::ResetStatistics()
Summary:
Most of the time, compiler statistics can be obtained using a process that
performs a single compilation and terminates such as llc. However, this isn't
always the case. JITs for example, perform multiple compilations over their
lifetime and STATISTIC() will record cumulative values across all of them.
Provide tools like this with the facilities needed to measure individual
compilations by allowing them to reset the STATISTIC() values back to zero using
llvm::ResetStatistics(). It's still the tools responsibility to ensure that they
perform compilations in such a way that the results are meaningful to their
intended use.
Reviewers: qcolombet, rtereshin, bogner, aditya_nandakumar
Reviewed By: bogner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326981
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Fangrui Song [Thu, 8 Mar 2018 01:28:45 +0000 (01:28 +0000)]
Add attributes and fix some keywords in llvm-mode.el
Reviewers: rafael, echristo
Reviewed By: echristo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326978
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Bob Haarman [Thu, 8 Mar 2018 01:13:10 +0000 (01:13 +0000)]
Revert "[LTO] Support filtering by hotness threshold"
This reverts commit
1f3bd185c53beb6aa68446974b7e80837abd6ef0 (r326107)
because it fails
ThinLTO/X86/diagnostic-handler-remarks-with-hotness.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326975
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Rafael Auler [Thu, 8 Mar 2018 00:46:53 +0000 (00:46 +0000)]
Reland "[DebugInfo] Support DWARF expressions in eh_frame"
Summary:
Original change was D43313 (r326932) and reverted by r326953 because it
broke an LLD test and a windows build. The LLD test was already fixed in
lld commit r326944 (thanks maskray). This is the original change with
the windows build fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326970
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Weiming Zhao [Thu, 8 Mar 2018 00:28:25 +0000 (00:28 +0000)]
[AArch64] Fix UB about shift amount exceeds data bit-width
Summary:
Fixes an UB caught by sanitizer. The shift amount might be larger than 32 so the operand should be 1ULL.
In this patch, we replace the original expression with existing API with uint64_t type.
Reviewers: eli.friedman, rengolin
Reviewed By: rengolin
Subscribers: rengolin, javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D44234
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326969
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Craig Topper [Thu, 8 Mar 2018 00:21:17 +0000 (00:21 +0000)]
[X86] Fix some isel patterns that used aligned vector load instructions with unaligned predicates.
These patterns weren't checking the alignment of the load, but were using the aligned instructions. This will cause a GP fault if the data isn't aligned.
I believe these were introduced in r312450.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326967
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Rafael Espindola [Thu, 8 Mar 2018 00:17:13 +0000 (00:17 +0000)]
Delete code that is probably dead since r249303.
With r249303 the expression evaluation should expand variables that
are not in sections (and so don't have an atom).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326966
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Eugene Zemtsov [Thu, 8 Mar 2018 00:07:26 +0000 (00:07 +0000)]
Fix build broken by r326959
Adding Demangle to link time dependencies of Symbolize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326964
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Simon Pilgrim [Wed, 7 Mar 2018 23:56:42 +0000 (23:56 +0000)]
[X86][SSE] LowerBUILD_VECTORAsVariablePermute - reorder permute types. NFCI.
Reorder into 128/256/512 bit vector size groupings.
NFCI commit before some new features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326963
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Eugene Zemtsov [Wed, 7 Mar 2018 23:07:34 +0000 (23:07 +0000)]
Use itaniumDemangle in llvm-symbolizer
Currently on Windows (_MSC_VER) LLVMSymbolizer supports only Microsoft mangling.
This fix just explicitly uses itaniumDemangle when mangled name starts with _Z.
Differential Revision: https://reviews.llvm.org/D44192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326959
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Sanjay Patel [Wed, 7 Mar 2018 22:43:08 +0000 (22:43 +0000)]
[TTI] add explanatory comments for getArithmeticInstrCost; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326956
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Evandro Menezes [Wed, 7 Mar 2018 22:35:32 +0000 (22:35 +0000)]
[AArch64] Adjust the cost of integer vector division
Since there is no instruction for integer vector division, factor in the
cost of singling out each element to be used with the scalar division
instruction.
Differential revision: https://reviews.llvm.org/D43974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326955
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Rui Ueyama [Wed, 7 Mar 2018 22:29:48 +0000 (22:29 +0000)]
Revert r326932: [DebugInfo] Support DWARF expressions in eh_frame
This reverts commit rr326932 because it broke lld/test/ELF/eh-frame-hdr-augmentation.s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326953
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Sebastian Pop [Wed, 7 Mar 2018 22:07:13 +0000 (22:07 +0000)]
[AArch64] add missing pattern for insert_subvector undef
The attached testcase started failing after the patch to define
isExtractSubvectorCheap with the following pattern mismatch:
ISEL: Starting pattern match
Initial Opcode index to 85068
Match failed at index 85076
LLVM ERROR: Cannot select: t47: v8i16 = insert_subvector undef:v8i16, t43, Constant:i64<0>
The code generated from llvm/lib/Target/AArch64/AArch64InstrInfo.td
def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
(INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
is in ninja/lib/Target/AArch64/AArch64GenDAGISel.inc
At the location of the error it is:
/* 85076*/ OPC_CheckChild2Type, MVT::i32,
And it failed to match the type of operand 2.
Adding another def-pat for i64 fixes the failed def-pat error:
def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i64 0)),
(INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326949
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Jake Ehrlich [Wed, 7 Mar 2018 20:33:02 +0000 (20:33 +0000)]
Revert "[llvm-objcopy] Add support for large indexes"
Not all build bots have unzip which I used in a test.
This reverts commit
0b1f26d39ea42dd3716b525fbc8c78d8c7bb4479.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326941
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Jake Ehrlich [Wed, 7 Mar 2018 19:59:15 +0000 (19:59 +0000)]
[llvm-objcopy] Add support for large indexes
Because of -ffunction-sections (and maybe other use cases I'm not aware of?) it
can occur that we need more than 0xfeff sections but ELF dosn't support that
many sections. To solve this problem SHN_XINDEX exists and with it come a whole
host of changes for section indexes everywhere. This change adds support for
those cases which should allow llvm-objcopy to copy binaries that have an
arbitrary number of sections.
Differential Revision: https://reviews.llvm.org/D42516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326940
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Craig Topper [Wed, 7 Mar 2018 19:45:45 +0000 (19:45 +0000)]
[X86] Remove unused function argument. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326939
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Daniel Sanders [Wed, 7 Mar 2018 19:32:36 +0000 (19:32 +0000)]
Fix cmake's multi-config generators after r326738
LLVM_ENABLE_STATS isn't known at configure-time in these generators so we must
defer it to build-time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326936
91177308-0d34-0410-b5e6-
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Rafael Auler [Wed, 7 Mar 2018 19:19:51 +0000 (19:19 +0000)]
[DebugInfo] Support DWARF expressions in eh_frame
This patch enhances DWARFDebugFrame with the capability of parsing and
printing DWARF expressions in CFI instructions. It also makes FDEs and
CIEs accessible to lib users, so they can process them in client tools
that rely on LLVM. To make it self-contained with a test case, it
teaches llvm-readobj to be able to dump EH frames and checks they are
correct in a unit test. The llvm-readobj code is Maksim Panchenko's work
(maksfb).
Reviewers: JDevlieghere, espindola
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D43313
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326932
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 7 Mar 2018 19:14:05 +0000 (19:14 +0000)]
[X86][SSE] Regenerate float maxnum/minnum tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326930
91177308-0d34-0410-b5e6-
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Zachary Turner [Wed, 7 Mar 2018 19:12:36 +0000 (19:12 +0000)]
Fix a bug regarding a mis-identified file type in pdbutil.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326929
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Wed, 7 Mar 2018 18:58:33 +0000 (18:58 +0000)]
Update a few switch statements to handle file_magic::pdb.
This fixes a couple of warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326927
91177308-0d34-0410-b5e6-
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Roorda, Jan-Willem [Wed, 7 Mar 2018 18:53:36 +0000 (18:53 +0000)]
[Pipeliner] Fixed node order issue related to zero latency edges
Summary:
A desired property of the node order in Swing Modulo Scheduling is
that for nodes outside circuits the following holds: none of them is
scheduled after both a successor and a predecessor. We call
node orders that meet this property valid.
Although invalid node orders do not lead to the generation of incorrect
code, they can cause the pipeliner not being able to find a pipelined schedule
for arbitrary II. The reason is that after scheduling the successor and the
predecessor of a node, no room may be left to schedule the node itself.
For data flow graphs with 0-latency edges, the node ordering algorithm
of Swing Modulo Scheduling can generate such undesired invalid node orders.
This patch fixes that.
In the remainder of this commit message, I will give an example
demonstrating the issue, explain the fix, and explain how the the fix is tested.
Consider, as an example, the following data flow graph with all
edge latencies 0 and all edges pointing downward.
```
n0
/ \
n1 n3
\ /
n2
|
n4
```
Consider the implemented node order algorithm in top-down mode. In that mode,
the algorithm orders the nodes based on greatest Height and in case of equal
Height on lowest Movability. Finally, in case of equal Height and
Movability, given two nodes with an edge between them, the algorithm prefers
the source-node.
In the graph, for every node, the Height and Movability are equal to 0.
As will be explained below, the algorithm can generate the order n0, n1, n2, n3, n4.
So, node n3 is scheduled after its predecessor n0 and after its successor n2.
The reason that the algorithm can put node n2 in the order before node n3,
even though they have an edge between them in which node n3 is the source,
is the following: Suppose the algorithm has constructed the partial node
order n0, n1. Then, the nodes left to be ordered are nodes n2, n3, and n4. Suppose
that the while-loop in the implemented algorithm considers the nodes in
the order n4, n3, n2. The algorithm will start with node n4, and look for
more preferable nodes. First, node n4 will be compared with node n3. As the nodes
have equal Height and Movability and have no edge between them, the algorithm
will stick with node n4. Then node n4 is compared with node n2. Again the
Height and Movability are equal. But, this time, there is an edge between
the two nodes, and the algorithm will prefer the source node n2.
As there are no nodes left to compare, the algorithm will add node n2 to
the node order, yielding the partial node order n0, n1, n2. In this way node n2
arrives in the node-order before node n3.
To solve this, this patch introduces the ZeroLatencyHeight (ZLH) property
for nodes. It is defined as the maximum unweighted length of a path from the
given node to an arbitrary node in which each edge has latency 0.
So, ZLH(n0)=3, ZLH(n1)=ZLH(n3)=2, ZLH(n2)=1, and ZLH(n4)=0
In this patch, the preference for a greater ZeroLatencyHeight
is added in the top-down mode of the node ordering algorithm, after the
preference for a greater Height, and before the preference for a
lower Movability.
Therefore, the two allowed node-orders are n0, n1, n3, n2, n4 and n0, n3, n1, n2, n4.
Both of them are valid node orders.
In the same way, the bottom-up mode of the node ordering algorithm is adapted
by introducing the ZeroLatencyDepth property for nodes.
The patch is tested by adding extra checks to the following existing
lit-tests:
test/CodeGen/Hexagon/SUnit-boundary-prob.ll
test/CodeGen/Hexagon/frame-offset-overflow.ll
test/CodeGen/Hexagon/vect/vect-shuffle.ll
Before this patch, the pipeliner failed to pipeline the loops in these tests
due to invalid node-orders. After the patch, the pipeliner successfully
pipelines all these loops.
Reviewers: bcahoon
Reviewed By: bcahoon
Subscribers: Ayal, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D43620
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326925
91177308-0d34-0410-b5e6-
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Zachary Turner [Wed, 7 Mar 2018 18:40:41 +0000 (18:40 +0000)]
Teach identify_file_magic to identify PDB files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326924
91177308-0d34-0410-b5e6-
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Stefan Pintilie [Wed, 7 Mar 2018 18:27:10 +0000 (18:27 +0000)]
[PowerPC] Move test to correct location.
Test was added in r326906 to an incorrect location.
Moving the test to PPC CodeGen directory as the test is PPC specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326923
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 7 Mar 2018 17:53:18 +0000 (17:53 +0000)]
[X86] Make the MUL->VPMADDWD work before op legalization on AVX1 targets. Simplify feature checks by using isTypeLegal.
The v8i32 conversion on AVX1 targets was only working after LowerMUL splits 256-bit vectors.
While I was there I've also made it so we don't have to check for AVX2 and BWI directly and instead just ask if the type is legal.
Differential Revision: https://reviews.llvm.org/D44190
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326917
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 7 Mar 2018 17:53:16 +0000 (17:53 +0000)]
[Support] Stop passing StringRefs by const reference in some of the getHostCPUname implementations. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326916
91177308-0d34-0410-b5e6-
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Krzysztof Parzyszek [Wed, 7 Mar 2018 17:27:18 +0000 (17:27 +0000)]
[Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned ones
This is a follow-up to r325169, this time for all types, not just HVX
vector types.
Disable this by default, since it's not always safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326915
91177308-0d34-0410-b5e6-
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Sanjay Patel [Wed, 7 Mar 2018 17:18:22 +0000 (17:18 +0000)]
[LangRef] fix formatting in FP descriptions; NFC
This is a clean-up step to reduce diffs ahead of real
changes to the FP semantics as discussed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2018-February/121444.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326913
91177308-0d34-0410-b5e6-
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Farhana Aleen [Wed, 7 Mar 2018 17:09:18 +0000 (17:09 +0000)]
[AMDGPU] Increased vector length for global/constant loads.
Summary: GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache;
loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords.
Author: FarhanaAleen
Reviewed By: rampitec
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D44179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326910
91177308-0d34-0410-b5e6-
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Justin Lebar [Wed, 7 Mar 2018 16:56:49 +0000 (16:56 +0000)]
Re-land: Teach CorrelatedValuePropagation to reduce the width of udiv/urem instructions.
Summary:
If the operands of a udiv/urem can be proved to fit within a smaller
power-of-two-sized type, reduce the width of the udiv/urem.
Backed out for failing an assert in clang bootstrap builds. Re-landing
with a fix for handling non-power-of-two inputs (e.g. udiv i24).
Original Differential Revision: https://reviews.llvm.org/D44102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326908
91177308-0d34-0410-b5e6-
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Farhana Aleen [Wed, 7 Mar 2018 16:55:27 +0000 (16:55 +0000)]
Revert "[AMDGPU] Widened vector length for global/constant address space."
This reverts commit
ce988cc100dc65e7c6c727aff31ceb99231cab03.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326907
91177308-0d34-0410-b5e6-
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Stefan Pintilie [Wed, 7 Mar 2018 16:53:09 +0000 (16:53 +0000)]
[PowerPC] LSR tunings for PowerPC
The purpose of this patch is to have LSR generate better code on Power.
This is done by overriding isLSRCostLess.
Differential Revision: https://reviews.llvm.org/D40855
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326906
91177308-0d34-0410-b5e6-
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Wei Mi [Wed, 7 Mar 2018 16:45:33 +0000 (16:45 +0000)]
[SampleFDO] Extend SampleProfReader to handle demangled names.
SampleProfReader assumes function names in the profile are all mangled names.
However, there are cases that few demangled names are somehow contained in
the profile (usually because of debug info problems), which may trigger parsing
error in SampleProfReader and cause the whole profile to be unusable. The patch
extends SampleProfReader to handle profiles with demangled names, so that those
profiles can still be useful.
Differential revision: https://reviews.llvm.org/D44161
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326905
91177308-0d34-0410-b5e6-
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Farhana Aleen [Wed, 7 Mar 2018 16:29:05 +0000 (16:29 +0000)]
[AMDGPU] Widened vector length for global/constant address space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326904
91177308-0d34-0410-b5e6-
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Jonas Devlieghere [Wed, 7 Mar 2018 16:28:53 +0000 (16:28 +0000)]
[dwarfdump] Only print CU relative offset in verbose mode
Instead of only printing the CU-relative offset in non-verbose mode, it
makes more sense to only printed the resolved address. In verbose mode
we still print both.
Differential revision: https://reviews.llvm.org/D44148
rdar://
33525475
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326903
91177308-0d34-0410-b5e6-
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Alexander Kornienko [Wed, 7 Mar 2018 16:27:44 +0000 (16:27 +0000)]
Revert "Reapply "[DWARFv5] Emit file 0 to the line table.""
This reverts commit r326839.
r326839 breaks assembly file parsing:
$ cat q.c
void g() {}
$ clang -S q.c -g
$ clang -g -c q.s
q.s:9:2: error: file number already allocated
.file 1 "/tmp/test" "q.c"
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326902
91177308-0d34-0410-b5e6-
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Justin Lebar [Wed, 7 Mar 2018 16:05:43 +0000 (16:05 +0000)]
Revert rL326898: "Teach CorrelatedValuePropagation to reduce the width of udiv/urem instructions."
Breaks bootstrap builds: clang built with this patch asserts while
building MCDwarf.cpp: Assertion `castIsValid(op, S, Ty) && "Invalid
cast!"' failed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326900
91177308-0d34-0410-b5e6-
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Justin Lebar [Wed, 7 Mar 2018 15:11:13 +0000 (15:11 +0000)]
Teach CorrelatedValuePropagation to reduce the width of udiv/urem instructions.
Summary:
If the operands of a udiv/urem can be proved to fit within a smaller
power-of-two-sized type, reduce the width of the udiv/urem.
Reviewers: spatel, sanjoy
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D44102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326898
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 7 Mar 2018 14:13:14 +0000 (14:13 +0000)]
[X86][X87] Add X87 fp80 conversion tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326897
91177308-0d34-0410-b5e6-
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Simon Dardis [Wed, 7 Mar 2018 11:39:48 +0000 (11:39 +0000)]
[mips] Correct the definition of m(f|t)c(0|2)
These instructions are defined as taking a GPR register and a
coprocessor register for ISAs up to MIPS32. MIPS32 extended the
definition to allow a selector--a value from 0 to 32--to access
another register.
These instructions are now internally defined as being MIPS-I
instructions, but are rejected for pre-MIPS32 ISA's if they have
an explicit selector which is non-zero. This deviates slightly from
GAS's behaviour which rejects assembly instructions with an
explicit selector for pre-MIPS32 ISAs.
E.g:
mfc0 $4, $5, 0
is rejected by GAS for MIPS-I to MIPS-V but will be accepted
with this patch for MIPS-I to MIPS-V.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D41662
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326890
91177308-0d34-0410-b5e6-
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Sven van Haastregt [Wed, 7 Mar 2018 10:29:28 +0000 (10:29 +0000)]
[LoadStoreVectorizer] Differentiate between <1 x T> and T
The LoadStoreVectorizer thought that <1 x T> and T were the same types
when merging stores, leading to a crash later.
Patch by Erik Hogeman.
Differential Revision: https://reviews.llvm.org/D44014
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326884
91177308-0d34-0410-b5e6-
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Sjoerd Meijer [Wed, 7 Mar 2018 09:10:44 +0000 (09:10 +0000)]
[ARM] Fix for PR36577
Don't PerformSHLSimplify if the given node is used by a node that also uses a
constant because we may get stuck in an infinite combine loop.
bugzilla: https://bugs.llvm.org/show_bug.cgi?id=36577
Patch by Sam Parker.
Differential Revision: https://reviews.llvm.org/D44097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326882
91177308-0d34-0410-b5e6-
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Jonas Paulsson [Wed, 7 Mar 2018 08:57:09 +0000 (08:57 +0000)]
[SystemZ] NFC refactoring in SystemZHazardRecognizer.
Use Reset() after emitting a call.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326881
91177308-0d34-0410-b5e6-
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Jonas Paulsson [Wed, 7 Mar 2018 08:54:32 +0000 (08:54 +0000)]
[SystemZ] Improve getCurrCycleIdx() in SystemZHazardRecognizer.
getCurrCycleIdx() returns the decoder cycle index which the next candidate SU
will be placed on.
This patch improves this method by passing the candidate SU to it so that if
SU will begin a new group, the index of that group is returned instead.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326880
91177308-0d34-0410-b5e6-
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Jonas Paulsson [Wed, 7 Mar 2018 08:45:09 +0000 (08:45 +0000)]
[SystemZ] NFC refactoring in SystemZHazardRecognizer.
Handle the not-taken branch in emitInstruction() where the TakenBranch
argument is available. This is cleaner than relying on EmitInstruction().
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326879
91177308-0d34-0410-b5e6-
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Jonas Paulsson [Wed, 7 Mar 2018 08:39:00 +0000 (08:39 +0000)]
[SystemZ] Improved debug dumping during post-RA scheduling.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326878
91177308-0d34-0410-b5e6-
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Clement Courbet [Wed, 7 Mar 2018 08:14:02 +0000 (08:14 +0000)]
[X86] Add IMUL scheduling info on sandybridge, fix it on >=haswell.
Summary:
Only IMUL16rri uses an extra P0156. IMUL32* and IMUL16rr only use
P1.
This was computed using https://github.com/google/EXEgesis/blob/master/exegesis/tools/compute_itineraries.cc
This can easily be validated by running perf on the following code:
```
int main(int argc, char**argv) {
int a = argc;
int b = argc;
int c = argc;
int d = argc;
for (int i = 0; i < LOOP_ITERATIONS; ++i) {
asm volatile(
R"(
.rept 10000
imull $0x2, %%edx, %%eax
imull $0x2, %%ecx, %%ebx
imull $0x2, %%eax, %%edx
imull $0x2, %%ebx, %%ecx
.endr
)"
: "+a"(a), "+b"(b), "+c"(c), "+d"(d)
:
:);
}
return a+b+c+d;
}
```
-> test.cc
perf stat -x, -e cycles --pfm-events=uops_executed_port:port_0:u,uops_executed_port:port_1:u,uops_executed_port:port_2:u,uops_executed_port:port_3:u,uops_executed_port:port_4:u,uops_executed_port:port_5:u,uops_executed_port:port_6:u,uops_executed_port:port_7:u test
Reviewers: craig.topper, RKSimon, gadi.haber
Subscribers: llvm-commits, gchatelet, chandlerc
Differential Revision: https://reviews.llvm.org/D43460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326877
91177308-0d34-0410-b5e6-
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Aaron Smith [Wed, 7 Mar 2018 02:23:08 +0000 (02:23 +0000)]
[llvm-pdbdump] Add guard for null pointers and remove unused code
Summary: This avoids crashing when a user tries to dump a pdb with the `-native` option.
Reviewers: zturner, llvm-commits, rnk
Reviewed By: zturner
Subscribers: mgrang
Differential Revision: https://reviews.llvm.org/D44117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326863
91177308-0d34-0410-b5e6-
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Evgeny Stupachenko [Wed, 7 Mar 2018 02:17:08 +0000 (02:17 +0000)]
Add early exit on reassociation of 0 expression.
Summary:
Before the patch a try to reassociate ((v * 16) * 0) * 1 fall into infinite loop
Reviewers: pankajchawla
Differential Revision: http://reviews.llvm.org/D41467
From: Evgeny Stupachenko <evstupac@gmail.com>
<evgeny.v.stupachenko@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326861
91177308-0d34-0410-b5e6-
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Aaron Smith [Wed, 7 Mar 2018 00:33:09 +0000 (00:33 +0000)]
[DebugInfoPDB] Add DIA implementation for getSrcLineOnTypeDefn
Summary: This helps to determine the line number for a PDB type with definition
Reviewers: zturner, llvm-commits, rnk
Reviewed By: zturner
Subscribers: rengolin, JDevlieghere
Differential Revision: https://reviews.llvm.org/D44119
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326857
91177308-0d34-0410-b5e6-
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Eugene Zelenko [Tue, 6 Mar 2018 23:06:13 +0000 (23:06 +0000)]
[Transforms] Add missing header for InstructionCombining.cpp, in order to export LLVMInitializeInstCombine as extern "C". Fixes PR35947.
Patch by Brenton Bostick.
Differential revision: https://reviews.llvm.org/D44140
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326843
91177308-0d34-0410-b5e6-
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Craig Topper [Tue, 6 Mar 2018 22:45:31 +0000 (22:45 +0000)]
[X86] Fix a typo in Host.cpp that causes us to misidentify KNL, Silvermont, Goldmont and probably other CPUs for -march=native
I think most of the Intel Core CPUs and recent AMD CPUs are unaffected. All the CPUs that have a "subtype" should work. The ones that were broken are the ones that are a "type" with no subtypes.
Fixes PR36619.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326840
91177308-0d34-0410-b5e6-
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Paul Robinson [Tue, 6 Mar 2018 22:37:45 +0000 (22:37 +0000)]
Reapply "[DWARFv5] Emit file 0 to the line table."
Fixes the bug found by asan. Also XFAIL the new test for Darwin,
which is stuck on DWARF v2, and fix up other tests so they stop
failing on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326839
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 6 Mar 2018 22:32:01 +0000 (22:32 +0000)]
[TargetLowering] Add vector BITCAST support to SimplifyDemandedVectorElts
Notably helps cleanup after legalization of vector types
Differential Revision: https://reviews.llvm.org/D43674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326838
91177308-0d34-0410-b5e6-
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Sebastian Pop [Tue, 6 Mar 2018 21:55:59 +0000 (21:55 +0000)]
DA: remove uses of GEP, only ask SCEV
It's been quite some time the Dependence Analysis (DA) is broken,
as it uses the GEP representation to "identify" multi-dimensional arrays.
It even wrongly detects multi-dimensional arrays in single nested loops:
from test/Analysis/DependenceAnalysis/Coupled.ll, example @couple6
;; for (long int i = 0; i < 50; i++) {
;; A[i][3*i - 6] = i;
;; *B++ = A[i][i];
DA used to detect two subscripts, which makes no sense in the LLVM IR
or in C/C++ semantics, as there are no guarantees as in Fortran of
subscripts not overlapping into a next array dimension:
maximum nesting levels = 1
SrcPtrSCEV = %A
DstPtrSCEV = %A
using GEPs
subscript 0
src = {0,+,1}<nuw><nsw><%for.body>
dst = {0,+,1}<nuw><nsw><%for.body>
class = 1
loops = {1}
subscript 1
src = {-6,+,3}<nsw><%for.body>
dst = {0,+,1}<nuw><nsw><%for.body>
class = 1
loops = {1}
Separable = {}
Coupled = {1}
With the current patch, DA will correctly work on only one dimension:
maximum nesting levels = 1
SrcSCEV = {(-2424 + %A)<nsw>,+,1212}<%for.body>
DstSCEV = {%A,+,404}<%for.body>
subscript 0
src = {(-2424 + %A)<nsw>,+,1212}<%for.body>
dst = {%A,+,404}<%for.body>
class = 1
loops = {1}
Separable = {0}
Coupled = {}
This change removes all uses of GEP from DA, and we now only rely
on the SCEV representation.
The patch does not turn on -da-delinearize by default, and so the DA analysis
will be more conservative in the case of multi-dimensional memory accesses in
nested loops.
I disabled some interchange tests, as the DA is not able to disambiguate
the dependence anymore. To make DA stronger, we may need to
compute a bound on the number of iterations based on the access functions
and array dimensions.
The patch cleans up all the CHECKs in test/Transforms/LoopInterchange/*.ll to
avoid checking for snippets of LLVM IR: this form of checking is very hard to
maintain. Instead, we now check for output of the pass that are more meaningful
than dozens of lines of LLVM IR. Some tests now require -debug messages and thus
only enabled with asserts.
Patch written by Sebastian Pop and Aditya Kumar.
Differential Revision: https://reviews.llvm.org/D35430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326837
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Daniel Sanders [Tue, 6 Mar 2018 21:16:42 +0000 (21:16 +0000)]
PrintStatistics() and PrintStatisticsJSON() should take StatLock
These two functions iterate over the list of statistics but don't take the lock
that protects the iterators from being invalidated by
StatisticInfo::addStatistic().
So far, this hasn't been an issue since (in-tree at least) these functions are
called by the StatisticInfo destructor so addStatistic() shouldn't be called
anymore. However, we do expose them in the public API.
Note that this only protects against iterator invalidation and does not protect
against ordering issues caused by statistic updates that race with
PrintStatistics()/PrintStatisticsJSON().
Thanks to Roman Tereshin for spotting it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326834
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Craig Topper [Tue, 6 Mar 2018 19:44:52 +0000 (19:44 +0000)]
[TargetLowering] Rename DAGCombinerInfo::isAfterLegalizeVectorOps to DAGCombiner::isAfterLegalizeDAG since that's what it checks. NFC
The code checks Level == AfterLegalizeDAG which is the fourth and last of the possible DAG combine stages that we have.
There is a Level called AfterLegalVectorOps, but that's the third DAG combine and it doesn't always run.
A function called isAfterLegalVectorOps should imply it returns true in either of the DAG combines that runs after the legalize vector ops stage, but that's not what this function does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326832
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Aaron Smith [Tue, 6 Mar 2018 19:36:17 +0000 (19:36 +0000)]
[SymboleFilePDB] Put the test input back that my previous commit clobbered
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326831
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Krzysztof Parzyszek [Tue, 6 Mar 2018 19:15:58 +0000 (19:15 +0000)]
[Hexagon] Update more testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326830
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Krzysztof Parzyszek [Tue, 6 Mar 2018 19:07:21 +0000 (19:07 +0000)]
[Hexagon] Remove {{ *}} from testcases
The spaces in the instructions are now consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326829
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Sanjay Patel [Tue, 6 Mar 2018 19:01:18 +0000 (19:01 +0000)]
[InstCombine] simplify min/max canonicalization; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326828
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Craig Topper [Tue, 6 Mar 2018 18:56:33 +0000 (18:56 +0000)]
[X86] Reject registers that require a REX prefix in inline asm constraints in 32-bit mode
We don't currently reject r8-r15 or xmm8-32 or bpl/spl/sil/dil in 32-bit mode.
Differential Revision: https://reviews.llvm.org/D44031
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326826
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Stanislav Mekhanoshin [Tue, 6 Mar 2018 18:33:55 +0000 (18:33 +0000)]
[AMDGPU] Add default ISA version targets
In case if -mattr used to modify feature set bits in llvm-mc call
getIsaVersion can fail to identify specific ISA due to test mismatch.
Adding default fallback tests which will always correctly report at
least major version.
Differential Revision: https://reviews.llvm.org/D44163
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326825
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Aaron Smith [Tue, 6 Mar 2018 18:20:22 +0000 (18:20 +0000)]
[CodeView] Emit UdtSourceLine information for enums
Summary:
- Emit UdtSourceLine information for enums to match MSVC
- Add a method to add UDTSrcLine and call it for all Class/Struct/Union/Enum
- Update test cases to verify the changes
Reviewers: zturner, llvm-commits, rnk
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D44116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326824
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Sanjay Patel [Tue, 6 Mar 2018 18:19:42 +0000 (18:19 +0000)]
[PatternMatch] define m_Not using m_Xor and cst_pred_ty
Using cst_pred_ty in the definition allows us to match vectors with undef elements.
This is a continuation of an effort to make all pattern matchers allow undef elements in vectors:
rL325437
rL325466
D43792
Differential Revision: https://reviews.llvm.org/D44076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326823
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Rafael Espindola [Tue, 6 Mar 2018 17:19:23 +0000 (17:19 +0000)]
Refactor check for dllimport in the Verifier.
This avoids duplicated code and now also rejects dllimport aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326814
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Sanjay Patel [Tue, 6 Mar 2018 16:57:55 +0000 (16:57 +0000)]
[ValueTracking] move helpers for SelectPatterns from InstCombine to ValueTracking
Most of the folds based on SelectPatternResult belong in InstSimplify rather than
InstCombine, so the helper code should be available to other passes/analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326812
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