OSDN Git Service
Simon Pilgrim [Wed, 5 Apr 2017 10:44:42 +0000 (10:44 +0000)]
[X86][SSE] Renamed combine to make it clear that it only handles the vector shift by immediate opcodes. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299532
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James Molloy [Wed, 5 Apr 2017 10:44:38 +0000 (10:44 +0000)]
[AArch64] Crypto requires FP.
So if FP is disabled, crypto should also be disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299531
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Alex Bradbury [Wed, 5 Apr 2017 10:16:14 +0000 (10:16 +0000)]
Add MCContext argument to MCAsmBackend::applyFixup for error reporting
A number of backends (AArch64, MIPS, ARM) have been using
MCContext::reportError to report issues such as out-of-range fixup values in
their TgtAsmBackend. This is great, but because MCContext couldn't easily be
threaded through to the adjustFixupValue helper function from its usual
callsite (applyFixup), these backends ended up adding an MCContext* argument
and adding another call to applyFixup to processFixupValue. Adding an
MCContext parameter to applyFixup makes this unnecessary, and even better -
applyFixup can take a reference to MCContext rather than a potentially null
pointer.
Differential Revision: https://reviews.llvm.org/D30264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299529
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James Molloy [Wed, 5 Apr 2017 09:24:26 +0000 (09:24 +0000)]
[LAA] Correctly return a half-open range in expandBounds
This is a latent bug that's been hanging around for a while. For a loop-invariant
pointer, expandBounds would return the range {Ptr, Ptr}, but this was interpreted
as a half-open range, not a closed range. So we ended up planting incorrect
bounds checks. Even worse, they were tautological, so we ended up incorrectly
executing the optimized loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299526
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Gor Nishanov [Wed, 5 Apr 2017 05:26:26 +0000 (05:26 +0000)]
[coroutines] Add syntax coloring to examples in Coroutines.rst
Subscribers: EricWF
Differential Revision: https://reviews.llvm.org/D31699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299517
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Akira Hatanaka [Wed, 5 Apr 2017 03:44:09 +0000 (03:44 +0000)]
[ObjCArc] Do not dereference an invalidated iterator.
Fix a bug in ARC contract pass where an iterator that pointed to a
deleted instruction was dereferenced.
It appears that tryToContractReleaseIntoStoreStrong was incorrectly
assuming that a call to objc_retain would not immediately follow a call
to objc_release.
rdar://problem/
25276306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299507
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Lang Hames [Wed, 5 Apr 2017 01:43:59 +0000 (01:43 +0000)]
[RuntimeDyld] Remove an unused static member left over from r299449.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299497
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Bob Haarman [Wed, 5 Apr 2017 00:42:07 +0000 (00:42 +0000)]
ThinLTOBitcodeWriter: handle aliases first in filterModule
Summary: This change fixes a "local linkage requires default visibility" assert when attempting to build LLVM with ThinLTO on Windows.
Reviewers: pcc, tejohnson, mehdi_amini
Reviewed By: pcc
Subscribers: llvm-commits, Prazek
Differential Revision: https://reviews.llvm.org/D31632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299491
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Ahmed Bougacha [Wed, 5 Apr 2017 00:14:39 +0000 (00:14 +0000)]
[X86] Relax assert in broadcast-of-subvector lowering.
Before r294774, there was a problem when lowering broadcasts to use
128-bit subvectors.
When we looked through a bitcast to find the broadcast input, we'd keep
using the original type, so you'd end up with things like:
(v8f32 (broadcast
(v4f32 (extract_subvector
(v8i32 V),
...))
))
r294774 fixed it to always emit subvectors with the scalar type of the
original source.
It also introduced some asserts, to check that we use scalars with
the same size, and vectors with the same number of elements.
The scalar size equality is checked earlier when looking through bitcasts,
and is a useful assert.
However, the number of elements don't have to be identical: we're always
going to extract a 128-bit subvector, and we can have different size
inputs if we looked through a concat_vector to find a 256-bit source.
Relax the overzealous assert.
Replace it with a check of the original source vector being 256 or 512
bits. If it's 128 bits, we can't extract_subvector from it.
Fixes PR32371.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299490
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Matt Arsenault [Tue, 4 Apr 2017 23:44:46 +0000 (23:44 +0000)]
Allow targets to opt-in to codegen in SCC order
Decouple this setting from EnableIRPA.
To support function calls on AMDGPU, it is necessary to
report the global register usage throughout the kernel's
call graph, so callees need to be handled first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299487
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Daniel Berlin [Tue, 4 Apr 2017 23:43:10 +0000 (23:43 +0000)]
Re-apply MemorySSA: Add support for caching clobbering access in
stores with some fixes.
Summary:
This enables us to cache the clobbering access for stores, despite the
fact that we can't rewrite the use-def chains themselves.
Early testing shows that, after this change, for larger testcases, it
will be a significant net positive (memory and time) to remove the
walker caching.
Reviewers: george.burgess.iv, davide
Subscribers: Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D31567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299486
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Daniel Berlin [Tue, 4 Apr 2017 23:43:04 +0000 (23:43 +0000)]
Revert "MemorySSA: Add support for caching clobbering access in stores"
This reverts revision r299322.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299485
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Petr Hosek [Tue, 4 Apr 2017 23:32:45 +0000 (23:32 +0000)]
[MC] Set defaults based on section names and support name suffixes
Set correct default flags and section type based on its name for .text,
.data, .bss, .init_array, .fini_array, .preinit_array, .tdata, and .tbss
and support section name suffixes for .data.*, .rodata.*, .text.*,
.bss.*, .tdata.* and .tbss.* which matches the behavior of GAS.
Fixes PR31888.
Differential Revision: https://reviews.llvm.org/D30229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299484
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Ahmed Bougacha [Tue, 4 Apr 2017 22:55:53 +0000 (22:55 +0000)]
[AArch64] Avoid partial register deps on insertelt of load into lane 0.
This improves upon r246462: that prevented FMOVs from being emitted
for the cross-class INSERT_SUBREGs by disabling the formation of
INSERT_SUBREGs of LOAD. But the ld1.s that we started selecting
caused us to introduce partial dependencies on the vector register.
Avoid that by using SCALAR_TO_VECTOR: it's a first-class citizen that
is folded away by many patterns, including the scalar LDRS that we
want in this case.
Credit goes to Adam for finding the issue!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299482
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Evgeniy Stepanov [Tue, 4 Apr 2017 22:35:08 +0000 (22:35 +0000)]
Change section flag character for SHF_LINK_ORDER to "o".
GAS uses "m" as a compatibility alias for "M" (SHF_MERGE).
"o" is free, except on ia64, where it already means SHF_LINK_ORDER.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299479
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Craig Topper [Tue, 4 Apr 2017 22:22:30 +0000 (22:22 +0000)]
[InstCombine] Add test cases for various add/subtracts of constants(scalar, splat, and vector) with phis and selects. Improvements coming in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299476
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Rafael Espindola [Tue, 4 Apr 2017 22:20:18 +0000 (22:20 +0000)]
[lit] Add a minimum export implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299475
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Sanjay Patel [Tue, 4 Apr 2017 22:06:03 +0000 (22:06 +0000)]
[InstCombine] rename variable for easier reading; NFC
We usually give constants a 'C' somewhere in the name...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299474
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Craig Topper [Tue, 4 Apr 2017 21:44:56 +0000 (21:44 +0000)]
[InstCombine] Turn subtract of vectors of i1 into xor like we do for scalar i1. Matches what we already do for add.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299472
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Balaram Makam [Tue, 4 Apr 2017 21:15:53 +0000 (21:15 +0000)]
[AArch64] Add missing schedinfo, check completeness for Falkor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299468
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Keno Fischer [Tue, 4 Apr 2017 20:30:47 +0000 (20:30 +0000)]
[ExecutionDepsFix] Don't revisit true dependencies
If an instruction has a true dependency, it makes sense for to use that
register for any undef read operands in the same instruction (we'll have
to wait for that register to become available anyway). This logic
was already implemented. However, the code would then still try to
revisit that instruction and break the dependency (and always fail,
since by definition a true dependency has to be live before the
instruction). Avoid revisiting such instructions as a performance
optimization. No functional change.
Differential Revision: https://reviews.llvm.org/D30173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299467
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Craig Topper [Tue, 4 Apr 2017 20:26:25 +0000 (20:26 +0000)]
[InstCombine] Support folding and/or/xor with a constant vector RHS into selects and phis
Currently we only fold with ConstantInt RHS. This generalizes to any Constant RHS.
Differential Revision: https://reviews.llvm.org/D31610
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299466
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Petr Hosek [Tue, 4 Apr 2017 19:51:53 +0000 (19:51 +0000)]
[AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsia
This mode is just like -mcmodel=small except that it moves the
thread pointer from TPIDR_EL0 to TPIDR_EL1.
Patch by Roland McGrath.
Differential Revision: https://reviews.llvm.org/D31624
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299462
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Craig Topper [Tue, 4 Apr 2017 19:31:21 +0000 (19:31 +0000)]
[InstCombine] Add test cases for missing combines of phis with and/or/xor with constant argument. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299460
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Yi Kong [Tue, 4 Apr 2017 19:06:04 +0000 (19:06 +0000)]
Implement host CPU detection for AArch64
This shares detection logic with ARM(32), since AArch64 capable CPUs may
also run in 32-bit system mode.
We observe weird /proc/cpuinfo output for MSM8992 and MSM8994, where
they report all CPU cores as one single model, depending on which CPU
core the kernel is running on. As a workaround, we hardcode the known
CPU part name for these SoCs.
For big.LITTLE systems, this patch would only return the part name of
the first core (usually the little core). Proper support will be added
in a follow-up change.
Differential Revision: D31675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299458
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Matt Arsenault [Tue, 4 Apr 2017 18:43:11 +0000 (18:43 +0000)]
Verifier: Check some amdgpu calling convention restrictions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299457
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Balaram Makam [Tue, 4 Apr 2017 18:42:14 +0000 (18:42 +0000)]
[AArch64] Refine Falkor Machine Model - Part 2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299456
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Coby Tayree [Tue, 4 Apr 2017 17:57:23 +0000 (17:57 +0000)]
[X86][inline-asm] Add support for MS 'EVEN' directive
MS assembly syntax provide us with the 'EVEN' directive as a synonymous to at&t '.even'.
This patch include the (small, simple) changes need to allow it.
Test is provided at the following (clang-side) review:
https://reviews.llvm.org/D27418
Differential Revision: https://reviews.llvm.org/D27417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299453
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Craig Topper [Tue, 4 Apr 2017 17:48:08 +0000 (17:48 +0000)]
[InstCombine] Add more test cases for missing combines of selects with and/or/xor with constant argument. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299450
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Lang Hames [Tue, 4 Apr 2017 17:03:49 +0000 (17:03 +0000)]
[RuntimeDyld] Make RuntimeDyld honor the ProcessAllSections flag.
When the ProcessAllSections flag (introduced in r204398) is set RuntimeDyld is
supposed to make a call to the client's memory manager for every section in each
object that is loaded. Due to some missing checks, this was not happening in all
cases. This patch adds the missing cases, and fixes the Orc unit test that
verifies correct behavior for ProcessAllSections (The unit test had been
silently bailing out due to an ordering issue: a change in the test order meant
that this unit-test was running before the native target was registered. This
issue has also been fixed in this patch).
This fixes <rdar://problem/
22789965>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299449
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Sanjay Patel [Tue, 4 Apr 2017 16:54:58 +0000 (16:54 +0000)]
[x86] remove dead select-of-constants transform; NFCI
https://reviews.llvm.org/D30537 / https://reviews.llvm.org/rL296977 added these transforms
and other related transforms to the generic DAGCombiner (with a hook that x86 sets to true),
so these patterns should not exist by the time we reach the target-specific combiner hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299448
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Rong Xu [Tue, 4 Apr 2017 16:42:20 +0000 (16:42 +0000)]
[PGO] Memory intrinsic calls optimization based on profiled size
This patch optimizes two memory intrinsic operations: memset and memcpy based
on the profiled size of the operation. The high level transformation is like:
mem_op(..., size)
==>
switch (size) {
case s1:
mem_op(..., s1);
goto merge_bb;
case s2:
mem_op(..., s2);
goto merge_bb;
...
default:
mem_op(..., size);
goto merge_bb;
}
merge_bb:
Differential Revision: http://reviews.llvm.org/D28966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299446
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Matt Arsenault [Tue, 4 Apr 2017 16:34:39 +0000 (16:34 +0000)]
AMDGPU: Remove legacy export intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299444
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Matt Arsenault [Tue, 4 Apr 2017 16:34:35 +0000 (16:34 +0000)]
AMDGPU: Remove legacy image intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299443
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Coby Tayree [Tue, 4 Apr 2017 14:43:23 +0000 (14:43 +0000)]
[X86][MS-compatability]Allow named synonymous for MS-assembly operators
This patch enhances X86AsmParser's immediate expression parsing abilities, to include a named synonymous for selected binary/unary bitwise operators: {and,shl,shr,or,xor,not}, ultimately achieving better MS-compatability
MASM reference:
https://msdn.microsoft.com/en-us/library/94b6khh4.aspx
Differential Revision: D31277
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299439
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Simon Pilgrim [Tue, 4 Apr 2017 14:40:53 +0000 (14:40 +0000)]
Strip trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299438
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Daniel Sanders [Tue, 4 Apr 2017 14:27:06 +0000 (14:27 +0000)]
[globalisel][tablegen] Fix non-determinism introduced in r299430.
This should fix the last issue on llvm-clang-x86_64-expensive-checks-win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299436
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Daniel Sanders [Tue, 4 Apr 2017 13:52:00 +0000 (13:52 +0000)]
[globalisel][tablegen] Try to make MSVC happy with r299430
Fix other cases of 'const StringRef' creeping back in at the same time.
This should fix the llvm-clang-x86_64-expensive-checks-win buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299433
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Michael Zuckerman [Tue, 4 Apr 2017 13:32:14 +0000 (13:32 +0000)]
[X86][LLVM] Converting __mm{|256|512}_movm_epi{8|16|32|64} LLVMIR call into generic intrinsics.
This patch is a part one of two reviews, one for the clang and the other for LLVM.
The patch deletes the back-end intrinsics and adds support for them in the auto upgrade.
Differential Revision: https://reviews.llvm.org/D31393
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299432
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Daniel Sanders [Tue, 4 Apr 2017 13:25:23 +0000 (13:25 +0000)]
[tablegen][globalisel] Add support for nested instruction matching.
Summary:
Lift the restrictions that prevented the tree walking introduced in the
previous change and add support for patterns like:
(G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3
Also adds support for G_SEXT and G_ZEXT to support these cases.
One particular aspect of this that I should draw attention to is that I've
tried to be overly conservative in determining the safety of matches that
involve non-adjacent instructions and multiple basic blocks. This is intended
to be used as a cheap initial check and we may add a more expensive check in
the future. The current rules are:
* Reject if any instruction may load/store (we'd need to check for intervening
memory operations.
* Reject if any instruction has implicit operands.
* Reject if any instruction has unmodelled side-effects.
See isObviouslySafeToFold().
Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka
Reviewed By: ab
Subscribers: igorb, dberris, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D30539
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299430
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Simon Dardis [Tue, 4 Apr 2017 11:28:53 +0000 (11:28 +0000)]
[mips] Deal with empty blocks in the mips hazard scheduler
This patch teaches the hazard scheduler how to handle empty blocks
when search for the next real instruction when dealing with forbidden
slots.
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D31293
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299427
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Oren Ben Simhon [Tue, 4 Apr 2017 10:23:18 +0000 (10:23 +0000)]
[X86] Add 64 bit pattern matching for PSADBW
PSADBW pattern currently supports the 32 bit IR pattern and only GLT (greather than) comparison.
The patch extends the pattern to catch also 64 bit IR pattern and includes all other comparison types (not only GLT).
Differential Revision: https://reviews.llvm.org/D31577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299425
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Jonas Hahnfeld [Tue, 4 Apr 2017 06:02:32 +0000 (06:02 +0000)]
Align all scalar numbers to LLVM_YAML_IS_FLOW_SEQUENCE_VECTOR
Otherwise, yamlize in YAMLTraits.h might be wrongly defined.
This makes some AMDGPU tests fail when LLVM_LINK_LLVM_DYLIB is set.
Differential Revision: https://reviews.llvm.org/D30508
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299415
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Craig Topper [Tue, 4 Apr 2017 05:03:02 +0000 (05:03 +0000)]
[InstCombine] Use setAllBits in place of getAllOnesValue since we know the bitwidths are the same. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299413
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Zvi Rackover [Tue, 4 Apr 2017 04:47:57 +0000 (04:47 +0000)]
InstCombine: Use the InstSimplify hook for shufflevector
Summary: Start using the recently added InstSimplify hook for shuffles in the respective InstCombine visitor.
Reviewers: spatel, RKSimon, craig.topper, majnemer
Reviewed By: majnemer
Subscribers: majnemer, llvm-commits
Differential Revision: https://reviews.llvm.org/D31526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299412
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Reid Kleckner [Tue, 4 Apr 2017 00:56:34 +0000 (00:56 +0000)]
[PDB] Save one type record copy
Summary:
The TypeTableBuilder provides stable storage for type records. We don't
need to copy all of the bytes into a flat vector before adding it to the
TpiStreamBuilder.
This makes addTypeRecord take an ArrayRef<uint8_t> and a hash code to go
with it, which seems like a simplification.
Reviewers: ruiu, zturner, inglorion
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299406
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Reid Kleckner [Mon, 3 Apr 2017 23:58:15 +0000 (23:58 +0000)]
[codeview] Cope with unsorted streams in type merging
Summary:
MASM can produce type streams that are not topologically sorted. It can
even produce type streams with circular references, but those are not
common in practice.
Reviewers: inglorion, ruiu
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31629
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299403
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Reid Kleckner [Mon, 3 Apr 2017 23:00:25 +0000 (23:00 +0000)]
[Fuzzer] Flush std::cout before aborting in CxxStringEqTest
On Windows, abort() does not appear to flush std::cout. Should fix red
sanitizer-windows bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299398
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Sanjay Patel [Mon, 3 Apr 2017 22:45:46 +0000 (22:45 +0000)]
add/move codegen tests for and/or of setcc; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299396
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Tim Northover [Mon, 3 Apr 2017 22:24:32 +0000 (22:24 +0000)]
Update stale doxygen links in ProgrammersManual.rst
Patch by Wei-Ren Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299395
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Zvi Rackover [Mon, 3 Apr 2017 22:05:30 +0000 (22:05 +0000)]
InstSimplify: Add a hook for shufflevector
Summary:
Add a hook for simplification of shufflevector's with the following rules:
- Constant folding - NFC, as it was already being done by the default handler.
- If only one of the operands is constant, constant fold the shuffle if the
mask does not select elements from the variable operand - to show the hook is firing and affecting the test-cases.
Reviewers: RKSimon, craig.topper, spatel, sanjoy, nlopes, majnemer
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31525
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299393
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Weiming Zhao [Mon, 3 Apr 2017 21:50:04 +0000 (21:50 +0000)]
Reland r298901 with modifications (reverted in r298932)
Dont emit Mapping symbols for sections that contain only data.
Summary:
Dont emit mapping symbols for sections that contain only data.
Reviewers: rengolin, weimingz, kparzysz, t.p.northover, peter.smith
Reviewed By: t.p.northover
Patched by Shankar Easwaran <shankare@codeaurora.org>
Subscribers: alekseyshl, t.p.northover, llvm-commits
Differential Revision: https://reviews.llvm.org/D30724
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299392
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Matt Arsenault [Mon, 3 Apr 2017 21:45:13 +0000 (21:45 +0000)]
AMDGPU: Remove llvm.SI.vs.load.input
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299391
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Matt Arsenault [Mon, 3 Apr 2017 21:28:13 +0000 (21:28 +0000)]
DAG: Fix missing legalization for any_extend_vector_inreg operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299389
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Reid Kleckner [Mon, 3 Apr 2017 21:25:20 +0000 (21:25 +0000)]
[codeview] Add support for label type records
MASM can produce these type records.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299388
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Simon Pilgrim [Mon, 3 Apr 2017 21:06:51 +0000 (21:06 +0000)]
[X86][SSE]] Lower BUILD_VECTOR with repeated elts as BUILD_VECTOR + VECTOR_SHUFFLE
It can be costly to transfer from the gprs to the xmm registers and can prevent loads merging.
This patch splits vXi16/vXi32/vXi64 BUILD_VECTORS that use the same operand in multiple elements into a BUILD_VECTOR with only a single insertion of each of those elements and then performs an unary shuffle to duplicate the values.
There are a couple of minor regressions this patch unearths due to some missing MOVDDUP/BROADCAST folds that I will address in a future patch.
Note: Now that vector shuffle lowering and combining is pretty good we should be reusing that instead of duplicating so much in LowerBUILD_VECTOR - this is the first of several patches to address this.
Differential Revision: https://reviews.llvm.org/D31373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299387
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Craig Topper [Mon, 3 Apr 2017 20:41:47 +0000 (20:41 +0000)]
[InstCombine] Remove canonicalization for (X & C1) | C2 --> (X | C2) & (C1|C2) when C1 & C2 have common bits.
It turns out that SimplifyDemandedInstructionBits will get called earlier and remove bits from C1 first. Effectively doing (X & (C1&C2)) | C2. So by the time it got to this check there could be no common bits.
I think the DAGCombiner has the same check but its check can be executed because it handles demanded bits later. I'll look at it next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299384
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Amjad Aboud [Mon, 3 Apr 2017 20:28:45 +0000 (20:28 +0000)]
x86 interrupt calling convention: re-align stack pointer on 64-bit if an error code was pushed
The x86_64 ABI requires that the stack is 16 byte aligned on function calls. Thus, the 8-byte error code, which is pushed by the CPU for certain exceptions, leads to a misaligned stack. This results in bugs such as Bug 26413, where misaligned movaps instructions are generated.
This commit fixes the misalignment by adjusting the stack pointer in these cases. The adjustment is done at the beginning of the prologue generation by subtracting another 8 bytes from the stack pointer. These additional bytes are popped again in the function epilogue.
Fixes Bug 26413
Patch by Philipp Oppermann.
Differential Revision: https://reviews.llvm.org/D30049
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299383
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Jun Bum Lim [Mon, 3 Apr 2017 19:20:07 +0000 (19:20 +0000)]
[CodeGenPrep] move aarch64-type-promotion to CGP
Summary:
Move the aarch64-type-promotion pass within the existing type promotion framework in CGP.
This change also support forking sexts when a new sext is required for promotion.
Note that change is based on D27853 and I am submitting this out early to provide a better idea on D27853.
Reviewers: jmolloy, mcrosier, javed.absar, qcolombet
Reviewed By: qcolombet
Subscribers: llvm-commits, aemerson, rengolin, mcrosier
Differential Revision: https://reviews.llvm.org/D28680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299379
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Craig Topper [Mon, 3 Apr 2017 19:18:48 +0000 (19:18 +0000)]
[DAGCombine][InstCombine] Fix inverted if condition in equivalent comments in DAGCombine and InstCombine. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299378
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Joel Jones [Mon, 3 Apr 2017 18:21:50 +0000 (18:21 +0000)]
Fix LLVMBuild.txt typo. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299373
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Matt Arsenault [Mon, 3 Apr 2017 18:08:08 +0000 (18:08 +0000)]
AMDGPU: Remove legacy bfe intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299372
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Graydon Hoare [Mon, 3 Apr 2017 18:04:15 +0000 (18:04 +0000)]
[Support] Make printAllJSONValues public, for custom output.
Summary:
This changes the static method TimerGroup::printAllJSONValues from private to
public, to match the static method TimerGroup::printAll. When trying to drive
the reporting machinery by hand, the existing API is _almost_ flexible enough,
but this entrypoint is required to intermix printing timers with other
non-timer output.
The underlying motive here is a Swift change to consolidate the collection of
timers, LLVM statistics and other (non-assert-dependent) counters into JSON
files, which requires a bit of manual intervention in LLVM's stat and timer
output routines. See https://github.com/apple/swift/pull/8477 for details.
Reviewers: MatzeB
Reviewed By: MatzeB
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D31566
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299371
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Peter Collingbourne [Mon, 3 Apr 2017 17:58:48 +0000 (17:58 +0000)]
Bitcode: Remove reader support for MODULE_CODE_PURGEVALS.
Support for writing this module code was removed in r73220, which was well
before the LLVM 3.0 release, so we do not need to be able to understand it
for backwards compatibility.
Differential Revision: https://reviews.llvm.org/D31563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299370
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Craig Topper [Mon, 3 Apr 2017 17:49:15 +0000 (17:49 +0000)]
[InstCombine] Add test cases showing how we fail to fold vector constants into selects the way we do with scalars.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299369
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Zvi Rackover [Mon, 3 Apr 2017 17:41:19 +0000 (17:41 +0000)]
Revert "[DAGCombine] A shuffle of a splat is always the splat itself"
This reverts commit r299047 which is incorrect because the
simplification may result in incorrect propogation of undefs to users of
the folded shuffle.
Thanks to Andrea Di Biagio for pointing this out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299368
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Krzysztof Parzyszek [Mon, 3 Apr 2017 17:26:40 +0000 (17:26 +0000)]
[Hexagon] Factor out some common code in HexagonEarlyIfConv.cpp, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299367
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Craig Topper [Mon, 3 Apr 2017 17:22:23 +0000 (17:22 +0000)]
Revert r299337 "[InstCombine] Remove redundant combine from visitAnd"
One of the tsan bots started failing at this commit. I don't see anything obviously wrong with the commit so trying this to see if it recovers.
Failing log: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/6792
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299366
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Sanjay Patel [Mon, 3 Apr 2017 16:53:12 +0000 (16:53 +0000)]
[InstCombine] fix formatting for foldLogOpOfMaskedICmps and related bits; NFCI
1. Improve enum, function, and variable names.
2. Improve comments.
3. Fix variable capitalization.
4. Run clang-format.
As an existing code comment suggests, this should work with vector types / splat constants too,
so making this look right first will reduce the diffs needed for that change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299365
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Craig Topper [Mon, 3 Apr 2017 16:34:59 +0000 (16:34 +0000)]
[APInt] Move isMask and isShiftedMask out of APIntOps and into the APInt class. Implement them without memory allocation for multiword
This moves the isMask and isShiftedMask functions to be class methods. They now use the MathExtras.h function for single word size and leading/trailing zeros/ones or countPopulation for the multiword size. The previous implementation made multiple temorary memory allocations to do the bitwise arithmetic operations to match the MathExtras.h implementation.
Differential Revision: https://reviews.llvm.org/D31565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299362
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Simon Pilgrim [Mon, 3 Apr 2017 15:27:49 +0000 (15:27 +0000)]
[DAGCombiner] Check limits before accessing array element (PR32502)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299361
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Sjoerd Meijer [Mon, 3 Apr 2017 14:50:04 +0000 (14:50 +0000)]
ARMAsmParser: clean up of isImmediate functions
- we are now using immediate AsmOperands so that the range check functions are
tablegen'ed.
- Big bonus is that error messages become much more accurate, i.e. instead of a
useless "invalid operand" error message it will not say that the immediate
operand must in range [x,y], which is why regression tests needed updating.
More tablegen operand descriptions could probably benefit from using
immediateAsmOperand, but this is a first good step to get rid of most of the
nearly identical range check functions. I will address the remaining immediate
operands in next clean ups.
Differential Revision: https://reviews.llvm.org/D31333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299358
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Craig Topper [Mon, 3 Apr 2017 07:08:08 +0000 (07:08 +0000)]
[InstCombine] Make foldOpWithConstantIntoOperand take a BinaryOperator instead of a generic Instruction.
It blindly assumes there are two operands so make it explicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299351
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Craig Topper [Mon, 3 Apr 2017 06:02:09 +0000 (06:02 +0000)]
[InstCombine] Remove a And transform that should be handled by SimplifyDemandedInstructionBits. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299349
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NAKAMURA Takumi [Sun, 2 Apr 2017 23:57:17 +0000 (23:57 +0000)]
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299344
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NAKAMURA Takumi [Sun, 2 Apr 2017 23:57:10 +0000 (23:57 +0000)]
Reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299343
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Craig Topper [Sun, 2 Apr 2017 19:35:18 +0000 (19:35 +0000)]
[APInt] Make use of whichWord and maskBit to simplify some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299342
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Craig Topper [Sun, 2 Apr 2017 19:17:22 +0000 (19:17 +0000)]
[APInt] Add a public typedef for the internal type of APInt use it instead of integerPart. Make APINT_BITS_PER_WORD and APINT_WORD_SIZE public.
This patch is one step to attempt to unify the main APInt interface and the tc functions used by APFloat.
This patch adds a WordType to APInt and uses that in all the tc functions. I've added temporary typedefs to APFloat to alias it to integerPart to keep the patch size down. I'll work on removing that in a future patch.
In future patches I hope to reuse the tc functions to implement some of the main APInt functionality.
I may remove APINT_ from BITS_PER_WORD and WORD_SIZE constants so that we don't have the repetitive APInt::APINT_ externally.
Differential Revision: https://reviews.llvm.org/D31523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299341
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Craig Topper [Sun, 2 Apr 2017 17:57:30 +0000 (17:57 +0000)]
[InstCombine] Make InstCombiner::OptAndOp take a BinaryOperator instead of an Instruction.
The callers have already performed the necessary cast before calling. This allows us to remove a comment that says the instruction must be a BinaryOperator and make it explicit in the argument type.
Had to add a default case to the switch because BinaryOperator::getOpcode() returns a BinaryOps enum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299339
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Simon Pilgrim [Sun, 2 Apr 2017 17:45:41 +0000 (17:45 +0000)]
[X86][MMX] Improve support for folding fptosi from XMM to MMX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299338
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Craig Topper [Sun, 2 Apr 2017 17:34:30 +0000 (17:34 +0000)]
[InstCombine] Remove redundant combine from visitAnd
As far as I can tell this combine is fully handled by SimplifyDemandedInstructionBits.
I was only looking at this because it is the only user of APIntOps::isShiftedMask which is itself broken. As demonstrated by r299187. I was going to fix isShiftedMask and needed to make sure we had coverage for the new cases it would expose to this combine. But looks like we can nuke it instead.
Differential Revision: https://reviews.llvm.org/D31543
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299337
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Simon Pilgrim [Sun, 2 Apr 2017 16:20:34 +0000 (16:20 +0000)]
[X86][MMX] Simplify tablegen patterns by always combining MOVDQ2Q from v2i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299336
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Simon Pilgrim [Sun, 2 Apr 2017 15:52:28 +0000 (15:52 +0000)]
[X86][MMX] Added support for subvector extraction to MMX register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299335
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NAKAMURA Takumi [Sun, 2 Apr 2017 15:05:18 +0000 (15:05 +0000)]
APInt.h: Prune \param(s) in \returns. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299334
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Simon Pilgrim [Sun, 2 Apr 2017 14:21:14 +0000 (14:21 +0000)]
Regenerate test with codegen. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299333
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Simon Pilgrim [Sun, 2 Apr 2017 13:59:37 +0000 (13:59 +0000)]
Regenerate test with codegen. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299332
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Simon Pilgrim [Sun, 2 Apr 2017 13:50:44 +0000 (13:50 +0000)]
Regenerate test. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299331
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Daniel Berlin [Sun, 2 Apr 2017 13:23:44 +0000 (13:23 +0000)]
NewGVN: Handle coercion of constant stores, loads, memory insts.
Summary:
Depends on D30928.
This adds support for coercion of stores and memory instructions that do not require insertion to process.
Another few tests down.
I added the relevant tests from rle.ll
Reviewers: davide
Subscribers: llvm-commits, Prazek
Differential Revision: https://reviews.llvm.org/D30929
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299330
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Nikolai Bozhenov [Sun, 2 Apr 2017 13:14:30 +0000 (13:14 +0000)]
[BypassSlowDivision] Do not bypass division of hash-like values
Disable bypassing if one of the operands looks like a hash value. Slow
division often occurs in hashtable implementations and fast division is
never taken there because a hash value is extremely unlikely to have
enough upper bits set to zero.
A value is considered to be hash-like if it is produced by
1) XOR operation
2) Multiplication by a constant wider than the shorter type
3) PHI node with all incoming values being hash-like
Differential Revision: https://reviews.llvm.org/D28200
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299329
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Simon Pilgrim [Sun, 2 Apr 2017 13:10:20 +0000 (13:10 +0000)]
[X86][MMX] Add generic fptosi 4f32-4i32 test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299328
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Zvi Rackover [Sun, 2 Apr 2017 10:42:21 +0000 (10:42 +0000)]
Add another interesting shufflevector test case for InstSimplify. NFC.
Test case shows opportunity to constant fold a shuffle with one variable
input vector operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299327
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Craig Topper [Sun, 2 Apr 2017 06:59:43 +0000 (06:59 +0000)]
[X86] Use tcAdd/tcSubtract to implement the slow case of operator+=/operator-=.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299326
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Craig Topper [Sun, 2 Apr 2017 06:59:41 +0000 (06:59 +0000)]
[APInt] Combine declaration and initialization. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299325
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Craig Topper [Sun, 2 Apr 2017 06:59:38 +0000 (06:59 +0000)]
[APInt] Simplify some code by using operator+=(uint64_t) instead of doing a more complex assignment into a temporary APInt just to use the APInt operator+=.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299324
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Craig Topper [Sun, 2 Apr 2017 06:59:36 +0000 (06:59 +0000)]
[APInt] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299323
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Daniel Berlin [Sun, 2 Apr 2017 05:09:15 +0000 (05:09 +0000)]
MemorySSA: Add support for caching clobbering access in stores
Summary:
This enables us to cache the clobbering access for stores, despite the
fact that we can't rewrite the use-def chains themselves.
Early testing shows that, after this change, for larger testcases, it will be a significant net positive (memory and time) to remove the walker caching.
Reviewers: george.burgess.iv, davide
Subscribers: Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D31567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299322
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Craig Topper [Sat, 1 Apr 2017 21:50:10 +0000 (21:50 +0000)]
[APInt] Use conditional operator to simplify some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299320
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Craig Topper [Sat, 1 Apr 2017 21:50:08 +0000 (21:50 +0000)]
[APInt] Implement flipAllBitsSlowCase with tcComplement. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299319
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Craig Topper [Sat, 1 Apr 2017 21:50:06 +0000 (21:50 +0000)]
[APInt] Fix indentation. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299318
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Craig Topper [Sat, 1 Apr 2017 21:50:03 +0000 (21:50 +0000)]
[APInt] Implement AndAssignSlowCase using tcAnd. Do the same for Or and Xor. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299317
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