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Teresa Johnson [Wed, 27 Jun 2018 19:00:35 +0000 (19:00 +0000)]
[ThinLTO] Fix test
Fix test changes added in r335760. Even though we are invoking llvm-lto2
in single threaded mode, the order of processing the modules in the
backend is apparently not deterministic. Handle the expected debug
messages in any order. (The determinism would be good to fix, but not
related to this change.)
This also undoes the change I made in r335764 to help debug this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335766
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Teresa Johnson [Wed, 27 Jun 2018 18:36:53 +0000 (18:36 +0000)]
[ThinLTO] Modify test to help diagnose bot failures
I am getting bot failures from r335760 that are difficult to diagnose
since the stderr is getting redirected to FileCheck. Save and dump the
debug output to stderr to help debug the issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335764
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Sanjay Patel [Wed, 27 Jun 2018 18:16:40 +0000 (18:16 +0000)]
[DAGCombiner] restrict (float)((int) f) --> ftrunc with no-signed-zeros
As noted in the D44909 review, the transform from (fptosi+sitofp) to ftrunc
can produce -0.0 where the original code does not:
#include <stdio.h>
int main(int argc) {
float x;
x = -0.8 * argc;
printf("%f\n", (float)((int)x));
return 0;
}
$ clang -O0 -mavx fp.c ; ./a.out
0.000000
$ clang -O1 -mavx fp.c ; ./a.out
-0.000000
Ideally, we'd use IR/node flags to predicate the transform, but the IR parser
doesn't currently allow fast-math-flags on the cast instructions. So for now,
just use the function attribute that corresponds to clang's "-fno-signed-zeros"
option.
Differential Revision: https://reviews.llvm.org/D48085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335761
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Teresa Johnson [Wed, 27 Jun 2018 18:03:39 +0000 (18:03 +0000)]
[ThinLTO] Print names in function import debug messages when available
Summary:
Rather than just print the GUID, when it is available in the index,
print the global name as well in the function import thin link debug
messages. Names will be available when the combined index is being
built by the same process, e.g. a linker or "llvm-lto2 run".
Reviewers: davidxl
Subscribers: mehdi_amini, inglorion, eraman, steven_wu, llvm-commits
Differential Revision: https://reviews.llvm.org/D48612
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335760
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Justin Bogner [Wed, 27 Jun 2018 17:58:32 +0000 (17:58 +0000)]
[Object] Allow iterating over an IRObjectFile's modules
If you've already loaded an IRObjectFile and need access to the
Modules themselves you shouldn't have to reparse a byte stream to do
it. Adds an accessor for the modules in IRObjectFile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335759
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Jessica Paquette [Wed, 27 Jun 2018 17:43:27 +0000 (17:43 +0000)]
[MachineOutliner] Don't outline sequences where x16/x17/nzcv are live across
It isn't safe to outline sequences of instructions where x16/x17/nzcv live
across the sequence.
This teaches the outliner to check whether or not a specific canidate has
x16/x17/nzcv live across it and discard the candidate in the case that that is
true.
https://bugs.llvm.org/show_bug.cgi?id=37573
https://reviews.llvm.org/D47655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335758
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Sanjay Patel [Wed, 27 Jun 2018 17:21:57 +0000 (17:21 +0000)]
[InstCombine] add more tests for shuffle with different binops; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335756
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Craig Topper [Wed, 27 Jun 2018 16:47:39 +0000 (16:47 +0000)]
[X86] Use bts/btr/btc for single bit set/clear/complement of a variable bit position
If we are just modifying a single bit at a variable bit position we can use the BT* instructions to make the change instead of shifting a 1(or rotating a -1) and doing a binop. These instruction also ignore the upper bits of their index input so we can also remove an and if one is present on the index.
Fixes PR37938.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335754
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Craig Topper [Wed, 27 Jun 2018 16:47:36 +0000 (16:47 +0000)]
[X86] Add test cases for D48606.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335753
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Jakub Kuderski [Wed, 27 Jun 2018 16:34:30 +0000 (16:34 +0000)]
[AliasSet] Fix UnknownInstructions printing
Summary:
AliasSet::print uses `I->printAsOperand` to print UnknownInstructions. The problem is that not all UnknownInstructions have names (e.g. call instructions). When such instructions are printed, they appear as `<badref>` in AliasSets, which is very confusing, as the values are perfectly valid.
This patch fixes that by printing UnknownInstructions without a name using `print` instead of `printAsOperand`.
Reviewers: asbirlea, chandlerc, sanjoy, grosser
Reviewed By: asbirlea
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48609
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335751
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Jonas Devlieghere [Wed, 27 Jun 2018 16:13:40 +0000 (16:13 +0000)]
[dsymutil] Move abstractions into separate files (NFC)
This patch splits off some abstractions used by dsymutil's dwarf linker
and moves them into separate header and implementation files. This
almost halves the number of LOC in DwarfLinker.cpp and makes it a lot
easier to understand what functionality lives where.
Differential revision: https://reviews.llvm.org/D48647
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335749
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Matt Davis [Wed, 27 Jun 2018 16:09:33 +0000 (16:09 +0000)]
[llvm-mca] Register listeners with stages; remove Pipeline dependency from Stage.
Summary:
This patch removes a few callbacks from Pipeline. It comes at the cost of
registering Listeners with all Stages. Not all stages need listeners or issue
callbacks, this registration is a bit redundant. However, as we build-out the
API, this redundancy can disappear.
The main purpose here is to move callback code from the Pipeline and into the
stages that actually issue those callbacks. This removes the back-pointer to
the Pipeline that was put into a few Stage subclasses.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb, courbet
Subscribers: tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335748
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Simon Pilgrim [Wed, 27 Jun 2018 16:00:53 +0000 (16:00 +0000)]
[X86][SSE] Add missing AVX512 rotation tests
Increase coverage to make sure we're not doing anything stupid without AVX512BW
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335746
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Craig Topper [Wed, 27 Jun 2018 15:57:53 +0000 (15:57 +0000)]
[X86] Rename the autoupgraded of packed fp compare and fpclass intrinsics that don't take a mask as input to exclude '.mask.' from their name.
I think the intrinsics named 'avx512.mask.' should refer to the previous behavior of taking a mask argument in the intrinsic instead of using a 'select' or 'and' instruction in IR to accomplish the masking. This is more consistent with the goal that eventually we will have no intrinsics that have masking builtin. When we reach that goal, we should have no intrinsics named "avx512.mask".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335744
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Stanislav Mekhanoshin [Wed, 27 Jun 2018 15:33:33 +0000 (15:33 +0000)]
[AMDGPU] Convert rcp to rcp_iflag
If a source of rcp instruction is a result of any conversion from
an integer convert it into rcp_iflag instruction. No FP exception
can ever happen except division by zero if a single precision rcp
argument is a representation of an integral number.
Differential Revision: https://reviews.llvm.org/D48569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335742
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Luke Geeson [Wed, 27 Jun 2018 14:34:40 +0000 (14:34 +0000)]
[AArch64] Reverting FP16 vcvth_n_s64_f16 to fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335737
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Adhemerval Zanella [Wed, 27 Jun 2018 13:58:46 +0000 (13:58 +0000)]
[AArch64] Add custom lowering for v4i8 trunc store
This patch adds a custom trunc store lowering for v4i8 vector types.
Since there is not v.4b register, the v4i8 is promoted to v4i16 (v.4h)
and default action for v4i8 is to extract each element and issue 4
byte stores.
A better strategy would be to extended the promoted v4i16 to v8i16
(with undef elements) and extract and store the word lane which
represents the v4i8 subvectores. The construction:
define void @foo(<4 x i16> %x, i8* nocapture %p) {
%0 = trunc <4 x i16> %x to <4 x i8>
%1 = bitcast i8* %p to <4 x i8>*
store <4 x i8> %0, <4 x i8>* %1, align 4, !tbaa !2
ret void
}
Can be optimized from:
umov w8, v0.h[3]
umov w9, v0.h[2]
umov w10, v0.h[1]
umov w11, v0.h[0]
strb w8, [x0, #3]
strb w9, [x0, #2]
strb w10, [x0, #1]
strb w11, [x0]
ret
To:
xtn v0.8b, v0.8h
str s0, [x0]
ret
The patch also adjust the memory cost for autovectorization, so the C
code:
void foo (const int *src, int width, unsigned char *dst)
{
for (int i = 0; i < width; i++)
*dst++ = *src++;
}
can be vectorized to:
.LBB0_4: // %vector.body
// =>This Inner Loop Header: Depth=1
ldr q0, [x0], #16
subs x12, x12, #4 // =4
xtn v0.4h, v0.4s
xtn v0.8b, v0.8h
st1 { v0.s }[0], [x2], #4
b.ne .LBB0_4
Instead of byte operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335735
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Ivan A. Kosarev [Wed, 27 Jun 2018 13:57:52 +0000 (13:57 +0000)]
[NEON] Support vldNq intrinsics in AArch32 (LLVM part)
This patch adds support for the q versions of the dup
(load-to-all-lanes) NEON intrinsics, such as vld2q_dup_f16() for
example.
Currently, non-q versions of the dup intrinsics are implemented
in clang by generating IR that first loads the elements of the
structure into the first lane with the lane (to-single-lane)
intrinsics, and then propagating it other lanes. There are at
least two problems with this approach. First, there are no
double-spaced to-single-lane byte-element instructions. For
example, there is no such instruction as 'vld2.8 { d0[0], d2[0]
}, [r0]'. That means we cannot rely on the to-single-lane
intrinsics and instructions to implement the q versions of the
dup intrinsics. Note that to-all-lanes instructions do support
all sizes of data items, including bytes.
The second problem with the current approach is that we need a
separate vdup instruction to propagate the structure to each
lane. So for vld4q_dup_f16() we would need four vdup instructions
in addition to the initial vld instruction.
This patch introduces dup LLVM intrinsics and reworks handling of
the currently supported (non-q) NEON dup intrinsics to expand
them into those LLVM intrinsics, thus eliminating the need for
using to-single-lane intrinsics and instructions.
Additionally, this patch adds support for u64 and s64 dup NEON
intrinsics. These are marked as Arch64-only in the ARM NEON
Reference, but it seems there are no reasons to not support them
in AArch32 mode. Please correct, if that is wrong.
That's what we generate with this patch applied:
vld2q_dup_f16:
vld2.16 {d0[], d2[]}, [r0]
vld2.16 {d1[], d3[]}, [r0]
vld3q_dup_f16:
vld3.16 {d0[], d2[], d4[]}, [r0]
vld3.16 {d1[], d3[], d5[]}, [r0]
vld4q_dup_f16:
vld4.16 {d0[], d2[], d4[], d6[]}, [r0]
vld4.16 {d1[], d3[], d5[], d7[]}, [r0]
Differential Revision: https://reviews.llvm.org/D48439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335733
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Florian Hahn [Wed, 27 Jun 2018 12:57:51 +0000 (12:57 +0000)]
[ValueLattice] Return false if value range did not change in mergeIn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335729
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Simon Pilgrim [Wed, 27 Jun 2018 12:45:31 +0000 (12:45 +0000)]
[DAGCombiner] visitSDIV - add special case handling for (sdiv X, 1) -> X in pow2 expansion
For divisor = 1, perform a select of X - reduces scalarisation of simple SDIVs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335727
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Nico Weber [Wed, 27 Jun 2018 11:52:30 +0000 (11:52 +0000)]
Build TaskQueueTest in threads=on builds, fixes regression from r335608.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335724
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Andrea Di Biagio [Wed, 27 Jun 2018 11:17:07 +0000 (11:17 +0000)]
[llvm-mca] Avoid calling method update() on instructions that are already in the IS_READY state. NFCI
When promoting instructions from the wait queue to the ready queue, we should
check if an instruction has already reached the IS_READY state before
calling method update().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335722
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Simon Pilgrim [Wed, 27 Jun 2018 10:59:36 +0000 (10:59 +0000)]
[X86][SSE] Include MIN_SIGNED element in non-uniform SDIV pow2 tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335721
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Simon Pilgrim [Wed, 27 Jun 2018 10:51:55 +0000 (10:51 +0000)]
[DAGCombiner] visitSDIV - simplify pow2 handling. NFCI.
Use the builtin constant folding of getNode() etc. instead of doing it manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335720
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Simon Pilgrim [Wed, 27 Jun 2018 10:21:06 +0000 (10:21 +0000)]
[DAGCombiner] Fold SDIV(%X, MIN_SIGNED) -> SELECT(%X == MIN_SIGNED, 1, 0)
Fixes PR37569.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335719
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Simon Pilgrim [Wed, 27 Jun 2018 09:41:22 +0000 (09:41 +0000)]
[DAGCombiner] Don't accept signbit sdiv divisors in sdiv-by-pow2 vector expansion (PR37569)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335717
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Luke Geeson [Wed, 27 Jun 2018 09:23:38 +0000 (09:23 +0000)]
Removing empty CodeGen dir in root
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335716
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Luke Geeson [Wed, 27 Jun 2018 09:20:13 +0000 (09:20 +0000)]
[AArch64] Remove Duplicate FP16 Patterns with same encoding, match on existing patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335715
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Konstantin Zhuravlyov [Wed, 27 Jun 2018 05:36:03 +0000 (05:36 +0000)]
AMDGPU/NFC: Fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335707
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Konstantin Zhuravlyov [Wed, 27 Jun 2018 05:18:50 +0000 (05:18 +0000)]
AMDHSA: Rename RESERVED -> RESERVED0, mark gfx9-specific field
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335706
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Konstantin Zhuravlyov [Wed, 27 Jun 2018 04:56:00 +0000 (04:56 +0000)]
AMDHSA/NFC: Address missed review feedback from
https://reviews.llvm.org/D47566
Change wording from "Must be backwards compatible" to
"Must match hardware definition" for enums that are
defined by hardware.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335705
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Petr Hosek [Wed, 27 Jun 2018 03:35:53 +0000 (03:35 +0000)]
[CMake] Provide direct support for building sanitized runtimes
This avoids having to rely on magic separators and special parsing.
Differential Revision: https://reviews.llvm.org/D48061
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335704
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Petr Hosek [Wed, 27 Jun 2018 03:14:41 +0000 (03:14 +0000)]
[CMake] Use variables rather than ":" delimiters
This is a more idiomatic CMake.
Differential Revision: https://reviews.llvm.org/D37644
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335703
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Justin Bogner [Wed, 27 Jun 2018 00:54:36 +0000 (00:54 +0000)]
[ADT] Pass DerivedT from pointe{e,r}_iterator to iterator_adaptor_base
These were passing the wrong type into iterator_adaptor_base if T was
anything but the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335698
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Matt Davis [Wed, 27 Jun 2018 00:54:11 +0000 (00:54 +0000)]
[llvm-mca] Add a comment to Stage::execute and fix a spelling error. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335697
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Vedant Kumar [Wed, 27 Jun 2018 00:47:53 +0000 (00:47 +0000)]
[InstCombine] Avoid creating mis-sized dbg.values in commonCastTransforms()
This prevents InstCombine from creating mis-sized dbg.values when
replacing a sequence of casts with a simpler cast. For example, in:
(fptrunc (floor (fpext X))) -> (floorf X)
We no longer emit dbg.value(X) (with a 32-bit float operand) to describe
(fpext X) (which is a 64-bit float).
This was diagnosed by the debugify check added in r335682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335696
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Vedant Kumar [Wed, 27 Jun 2018 00:47:52 +0000 (00:47 +0000)]
[Debugify] Handle failure to get fragment size when checking dbg.values
It's not possible to get the fragment size of some dbg.values. Teach the
mis-sized dbg.value diagnostic to detect this scenario and bail out.
Tested with:
$ find test/Transforms -print -exec opt -debugify-each -instcombine {} \;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335695
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Craig Topper [Wed, 27 Jun 2018 00:42:24 +0000 (00:42 +0000)]
[X86] Don't store register and memory FMA3 opcodes in the same X86InstrFMA3Group.
Nothing was using this relationship. By splitting them we no longer need to worry about register or memory entries being empty in a group.
The memory folding tables in X86InstrInfo.cpp can be used to access this relationship if needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335694
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Vedant Kumar [Tue, 26 Jun 2018 22:46:41 +0000 (22:46 +0000)]
[Debugify] Diagnose mis-sized dbg.values
Report an error in -check-debugify when the size of a dbg.value operand
doesn't match up with the size of the variable it describes.
Eventually this check should be moved into the IR verifier. For the
moment, it's useful to include the check in -check-debugify as a means
of catching regressions and finding existing bugs.
Here are some instances of bugs the new check finds in the -O2 pipeline
(all in InstCombine):
1) A float is used where a double is expected:
ERROR: dbg.value operand has size 32, but its variable has size 64:
call void @llvm.dbg.value(metadata float %expf, metadata !12, metadata
!DIExpression()), !dbg !15
2) An i8 is used where an i32 is expected:
ERROR: dbg.value operand has size 8, but its variable has size 32:
call void @llvm.dbg.value(metadata i8 %t4, metadata !14, metadata
!DIExpression()), !dbg !24
3) A <4 x i32> is used where something twice as large is expected
(perhaps a <4 x i64>, I haven't double-checked):
ERROR: dbg.value operand has size 128, but its variable has size 256:
call void @llvm.dbg.value(metadata <4 x i32> %4, metadata !40, metadata
!DIExpression()), !dbg !95
Differential Revision: https://reviews.llvm.org/D48408
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335682
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Evgeniy Stepanov [Tue, 26 Jun 2018 22:43:48 +0000 (22:43 +0000)]
Revert "[asan] Instrument comdat globals on COFF targets"
Causes false positive ODR violation reports on __llvm_profile_raw_version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335681
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Lang Hames [Tue, 26 Jun 2018 22:43:01 +0000 (22:43 +0000)]
[ORC] Don't call isa<> on a null value.
This should fix the recent builder failures in the test-global-ctors.ll testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335680
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Lang Hames [Tue, 26 Jun 2018 22:30:42 +0000 (22:30 +0000)]
[ORC] Fix a missing return value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335677
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Michael Zolotukhin [Tue, 26 Jun 2018 22:19:48 +0000 (22:19 +0000)]
[JumpThreading] Don't try to rewrite a use if it's already valid.
Summary:
When recording uses we need to rewrite after cloning a loop we need to
check if the use is not dominated by the original def. The initial
assumption was that the cloned basic block will introduce a new path and
thus the original def will only dominate the use if they are in the same
BB, but as the reproducer from PR37745 shows it's not always the case.
This fixes PR37745.
Reviewers: haicheng, Ka-Ka
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D48111
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335675
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Lang Hames [Tue, 26 Jun 2018 22:12:02 +0000 (22:12 +0000)]
[ORC] Add a dependence on MC to LLVMBuild.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335673
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Simon Pilgrim [Tue, 26 Jun 2018 22:03:00 +0000 (22:03 +0000)]
[X86] Add test for SDIV by sign bit (minsigned) value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335671
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Lang Hames [Tue, 26 Jun 2018 21:35:48 +0000 (21:35 +0000)]
[ORC] Add LLJIT and LLLazyJIT, and replace OrcLazyJIT in LLI with LLLazyJIT.
LLJIT is a prefabricated ORC based JIT class that is meant to be the go-to
replacement for MCJIT. Unlike OrcMCJITReplacement (which will continue to be
supported) it is not API or bug-for-bug compatible, but targets the same
use cases: Simple, non-lazy compilation and execution of LLVM IR.
LLLazyJIT extends LLJIT with support for function-at-a-time lazy compilation,
similar to what was provided by LLVM's original (now long deprecated) JIT APIs.
This commit also contains some simple utility classes (CtorDtorRunner2,
LocalCXXRuntimeOverrides2, JITTargetMachineBuilder) to support LLJIT and
LLLazyJIT.
Both of these classes are works in progress. Feedback from JIT clients is very
welcome!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335670
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Konstantin Zhuravlyov [Tue, 26 Jun 2018 21:33:38 +0000 (21:33 +0000)]
AMDGPU: Silence unused warnings in waitcnt insertion pass in release build
Differential Revision: https://reviews.llvm.org/D48607
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335669
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Jessica Paquette [Tue, 26 Jun 2018 21:30:34 +0000 (21:30 +0000)]
[X86][AsmParser] Recommit r335658
Recommit of r335658 so that it does not change the behaviour of any
existing error output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335668
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Vedant Kumar [Tue, 26 Jun 2018 21:16:59 +0000 (21:16 +0000)]
Rename skipDebugInfo -> skipDebugIntrinsics, NFC
This addresses post-commit feedback about the name 'skipDebugInfo' being
misleading. This name could be interpreted as meaning 'a function that
skips instructions with debug locations'.
The new name, 'skipDebugIntrinsics', makes it clear that this function
only skips debug info intrinsics.
Thanks to Adrian Prantl for pointing this out!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335667
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Lang Hames [Tue, 26 Jun 2018 20:59:51 +0000 (20:59 +0000)]
[ORC] Allow IRTransformLayer2's transform to be modified after initialization.
Also give the constructor's transform parameter a default no-op transform value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335665
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Lang Hames [Tue, 26 Jun 2018 20:59:50 +0000 (20:59 +0000)]
[ORC] Reset AsynchronousSymbolQuery's NotifySymbolsResolved callback on error.
AsynchronousSymbolQuery::canStillFail checks the value of the callback to
prevent sending it redundant error notifications, so we need to reset it after
running it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335664
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Lang Hames [Tue, 26 Jun 2018 20:59:49 +0000 (20:59 +0000)]
[ORC] Move the VSOList typedef out of VSO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335663
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Lang Hames [Tue, 26 Jun 2018 20:59:49 +0000 (20:59 +0000)]
[ORC] Add a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335662
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Lang Hames [Tue, 26 Jun 2018 20:59:46 +0000 (20:59 +0000)]
[ORC] Fix a FIXME by moving MangleAndInterner to Core.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335661
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Jessica Paquette [Tue, 26 Jun 2018 20:57:19 +0000 (20:57 +0000)]
Revert "[X86][AsmParser] Emit an error when RIP-relative instructions are used in 32-bit mode"
This reverts commit
4850a9aae8b38c7deadc103d634ec7397e6c323b.
It caused MC/X86/x86_errors.s to fail. Will fix and recommit shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335660
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Jessica Paquette [Tue, 26 Jun 2018 20:33:46 +0000 (20:33 +0000)]
[X86][AsmParser] Emit an error when RIP-relative instructions are used in 32-bit mode
Right now, when we use RIP-relative instructions in 32-bit mode, we'll just
assert and crash.
This adds an error message which tells the user that they can't do that in
32-bit mode, so that we don't crash (and also can see the issue outside of
assert builds).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335658
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Stanislav Mekhanoshin [Tue, 26 Jun 2018 20:04:19 +0000 (20:04 +0000)]
[AMDGPU] Add llvm.amdgcn.fmad.ftz intrinsic
This intrinsic selects v_mad_f32 regardless of fp32 denorm support.
Differential Revision: https://reviews.llvm.org/D48573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335654
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Sanjay Patel [Tue, 26 Jun 2018 19:46:56 +0000 (19:46 +0000)]
[DAGCombiner] use isBitwiseNot to simplify code; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335652
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Matt Arsenault [Tue, 26 Jun 2018 19:10:00 +0000 (19:10 +0000)]
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335650
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Matt Arsenault [Tue, 26 Jun 2018 18:55:43 +0000 (18:55 +0000)]
ConstantFold: Don't fold global address vs. null for addrspace != 0
Not sure why this logic seems to be repeated in 2 different places,
one called by the other.
On AMDGPU addrspace(3) globals start allocating at 0, so these
checks will be incorrect (not that real code actually tries
to compare these addresses)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335649
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Vedant Kumar [Tue, 26 Jun 2018 18:55:26 +0000 (18:55 +0000)]
Use a variable to appease a no-asserts bot, NFC
Failure URL:
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/22836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335648
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Vedant Kumar [Tue, 26 Jun 2018 18:54:10 +0000 (18:54 +0000)]
[Debugify] Don't treat missing dbg.values as an error (PR37942)
When checking the debug info in a module, don't treat a missing
dbg.value as an error. The dbg.value may simply have been DCE'd, in
which case the debugger has enough information to display the variable
as <optimized out>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335647
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Tim Shen [Tue, 26 Jun 2018 18:54:10 +0000 (18:54 +0000)]
[ConstantRange] Add support of mul in makeGuaranteedNoWrapRegion.
Summary: This is trying to add support for r334428.
Reviewers: sanjoy
Subscribers: jlebar, hiraditya, bixia, llvm-commits
Differential Revision: https://reviews.llvm.org/D48399
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335646
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Matt Arsenault [Tue, 26 Jun 2018 18:51:17 +0000 (18:51 +0000)]
LoopUnroll: Allow analyzing intrinsic call costs
I'm not sure why the code here is skipping calls since
TTI does try to do something for general calls, but it
at least should allow intrinsics.
Skip intrinsics that should not be omitted as calls, which
is by far the most common case on AMDGPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335645
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Vedant Kumar [Tue, 26 Jun 2018 18:44:53 +0000 (18:44 +0000)]
[Local] Add a convenient insertReplacementDbgValues overload, NFC
Add an overload for the common case where the replacement dbg.values
have the same DIExpressions as the originals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335643
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Vedant Kumar [Tue, 26 Jun 2018 18:44:52 +0000 (18:44 +0000)]
[Local] Sink salvageDI's early exit into helper functions, NFC
salvageDebugInfo() performs a check that allows it to exit early without
doing a DenseMap lookup. It's a bit neater and marginally more useful to
sink this early exit into the findDbg{Addr,Users,Values} helpers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335642
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Brendon Cahoon [Tue, 26 Jun 2018 18:44:05 +0000 (18:44 +0000)]
[Hexagon] Add a "generic" cpu
Add the generic processor for Hexagon so that it can be used
with 3rd party programs that create a back-end with the
"generic" CPU. This patch also enables the JIT for Hexagon.
Differential Revision: https://reviews.llvm.org/D48571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335641
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Simon Pilgrim [Tue, 26 Jun 2018 17:46:51 +0000 (17:46 +0000)]
[DAGCombiner] Don't accept -1 sdiv divisors in sdiv-by-pow2 vector expansion (PR37119)
Temporary fix until I've managed to get D45806 updated - both +1 and -1 special cases need to be properly supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335637
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Fangrui Song [Tue, 26 Jun 2018 17:44:23 +0000 (17:44 +0000)]
Move `REQUIRES:` line to the top
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335635
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Sanjay Patel [Tue, 26 Jun 2018 17:31:38 +0000 (17:31 +0000)]
[InstSimplify] fold shifts by sext bool
https://rise4fun.com/Alive/c3Y
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335633
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Sanjay Patel [Tue, 26 Jun 2018 17:15:07 +0000 (17:15 +0000)]
[InstSimplify] add tests for shifts by sext bool; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335631
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Simon Pilgrim [Tue, 26 Jun 2018 17:06:05 +0000 (17:06 +0000)]
[X86][SSE] Add another sdiv by (nonuniform) minus one test (PR37119)
Include a test that divides by -1 but not by 1 (another special case)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335629
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Sanjay Patel [Tue, 26 Jun 2018 16:39:29 +0000 (16:39 +0000)]
[InstCombine] simplify code for urem fold; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335623
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Sanjay Patel [Tue, 26 Jun 2018 16:30:00 +0000 (16:30 +0000)]
[InstCombine] fold urem with sext bool divisor
Similar to other patches in this series:
https://reviews.llvm.org/rL335512
https://reviews.llvm.org/rL335527
https://reviews.llvm.org/rL335597
https://reviews.llvm.org/rL335616
...this is filling a gap in analysis that is exposed by an unrelated select-of-constants transform.
I didn't see a way to unify the sext cases because each div/rem opcode results in a different fold.
Note that in this case, the backend might want to convert the select into math:
Name: sext urem
%e = sext i1 %x to i32
%r = urem i32 %y, %e
=>
%c = icmp eq i32 %y, -1
%z = zext i1 %c to i32
%r = add i32 %z, %y
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335622
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Simon Pilgrim [Tue, 26 Jun 2018 16:20:16 +0000 (16:20 +0000)]
[SLPVectorizer] Recognise non uniform power of 2 constants
Since D46637 we are better at handling uniform/non-uniform constant Pow2 detection; this patch tweaks the SLP argument handling to support them.
As SLP works with arrays of values I don't think we can easily use the pattern match helpers here.
Differential Revision: https://reviews.llvm.org/D48214
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335621
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Sanjay Patel [Tue, 26 Jun 2018 16:01:24 +0000 (16:01 +0000)]
[InstCombine] add tests for urem with sext bool divisor; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335619
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Simon Pilgrim [Tue, 26 Jun 2018 15:39:16 +0000 (15:39 +0000)]
[DAGCombiner] Pull out VT bitwidth in visitSDIV. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335617
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Sanjay Patel [Tue, 26 Jun 2018 15:32:54 +0000 (15:32 +0000)]
[InstSimplify] fold srem with sext bool divisor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335616
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James Henderson [Tue, 26 Jun 2018 15:29:09 +0000 (15:29 +0000)]
Fix doc title underlining.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335615
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James Henderson [Tue, 26 Jun 2018 15:15:45 +0000 (15:15 +0000)]
[FileCheck] Add CHECK-EMPTY directive for checking for blank lines
Prior to this change, there was no clean way of getting FileCheck to
check that a line is completely empty. The expected way of using
"CHECK: {{^$}}" does not work because the '^' matches the end of the
previous match (this behaviour may be desirable in certain instances).
For the same reason, "CHECK-NEXT: {{^$}}" will fail when the previous
match was at the end of the line, as the pattern will match there.
Using the recommended [[:space:]] to match an explicit new line could
also match a space, and thus is not always desired. Literal '\n'
matches also do not work. A workaround was suggested in the review, but
it is a little clunky.
This change adds a new directive that behaves the same as CHECK-NEXT,
except that it only matches against empty lines (nothing, not even
whitespace, is allowed). As with CHECK-NEXT, it will fail if more than
one newline occurs before the next blank line. Example usage:
; test.txt
foo
bar
; CHECK: foo
; CHECK-EMPTY:
; CHECK-NEXT: bar
Differential Revision: https://reviews.llvm.org/D28896
Reviewed by: probinson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335613
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Krzysztof Parzyszek [Tue, 26 Jun 2018 14:55:04 +0000 (14:55 +0000)]
Silence "unused variable" warning in LiveIntervals.cpp after r335607
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335610
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Sanjay Patel [Tue, 26 Jun 2018 14:47:31 +0000 (14:47 +0000)]
[InstSimplify] add tests for srem with sext bool divisor; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335609
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Nico Weber [Tue, 26 Jun 2018 14:42:48 +0000 (14:42 +0000)]
Fix LLVM_ENABLE_THREADS=0 builds after r335440.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335608
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Krzysztof Parzyszek [Tue, 26 Jun 2018 14:37:16 +0000 (14:37 +0000)]
Account for undef values from predecessors in extendSegmentsToUses
It is legal for a PHI node not to have a live value in a predecessor
as long as the end of the predecessor is jointly dominated by an undef
value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335607
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Simon Pilgrim [Tue, 26 Jun 2018 14:15:31 +0000 (14:15 +0000)]
[TargetLowering] isVectorClearMaskLegal - use ArrayRef<int> instead of const SmallVectorImpl<int>&
This is more generic and matches isShuffleMaskLegal.
Differential Revision: https://reviews.llvm.org/D48591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335605
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Than McIntosh [Tue, 26 Jun 2018 14:11:30 +0000 (14:11 +0000)]
[X86,ARM] Retain split-stack prolog check for sibling calls
Summary:
If a routine with no stack frame makes a sibling call, we need to
preserve the stack space check even if the local stack frame is empty,
since the call target could be a "no-split" function (in which case
the linker needs to be able to fix up the prolog sequence in order to
switch to a larger stack).
This fixes PR37807.
Reviewers: cherry, javed.absar
Subscribers: srhines, llvm-commits
Differential Revision: https://reviews.llvm.org/D48444
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335604
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Simon Pilgrim [Tue, 26 Jun 2018 14:06:23 +0000 (14:06 +0000)]
Fix spelling mistakes in comments. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335603
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Teresa Johnson [Tue, 26 Jun 2018 13:56:49 +0000 (13:56 +0000)]
[ThinLTO] Parse module summary index from assembly
Summary:
Adds assembly parsing support for the module summary index (follow on
to r333335 which added the assembly writing support).
I added support to llvm-as to invoke the index parsing, so that it can
create either a bitcode file with a Module and a per-module index, or
a combined index without a Module.
I will send follow on patches soon to do the following:
- add support to tools such as llvm-lto2 to parse the per-module indexes
from assembly instead of bitcode when testing the thin link.
- verification support.
Depends on D47844 and D47842.
Reviewers: pcc, dexonsmith, mehdi_amini
Subscribers: inglorion, eraman, steven_wu, llvm-commits
Differential Revision: https://reviews.llvm.org/D47905
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335602
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Sanjay Patel [Tue, 26 Jun 2018 12:41:15 +0000 (12:41 +0000)]
[InstCombine] fold udiv with sext bool divisor
Note: I didn't add a hasOneUse() check because the existing,
related fold doesn't have that check. I suspect that the
improved analysis and codegen make these some of the rare
canonicalization cases where we allow an increase in
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335597
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Tim Northover [Tue, 26 Jun 2018 12:28:47 +0000 (12:28 +0000)]
ARM: add binary file git swallowed.
Should fix bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335596
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Tim Northover [Tue, 26 Jun 2018 11:39:20 +0000 (11:39 +0000)]
ARM: correctly decode VFP instructions following unpredictable t2IT
When the condition code for an IT instruction is "AL" we get strange "15"
predicates on subsequent instructions. These are dealt with for most
instructions by treating them as "ARMCC::AL", but VFP takes a different path
which didn't have this code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335594
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Tim Northover [Tue, 26 Jun 2018 11:38:41 +0000 (11:38 +0000)]
ARM: diagnose unpredictable IT instructions
IT instructions are allowed to have the 'AL' predicate, but it must never
result in an 'NV' predicated instruction. Essentially this means that all
branches must be 't' rather than 'e' if the predicate is 'AL'.
This patch adds a diagnostic for this during assembly (error because parsing
hits an assertion if allowed to continue) and an annotation during disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335593
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Andrea Di Biagio [Tue, 26 Jun 2018 11:00:21 +0000 (11:00 +0000)]
[llvm-mca] Removed wrong NDEBUG guards introduced by my last commit.
This partially reverts r335589.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335592
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Clement Courbet [Tue, 26 Jun 2018 10:52:41 +0000 (10:52 +0000)]
[llvm-exegesis][NFC] Fix windows warning in rL335465.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335591
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Simon Pilgrim [Tue, 26 Jun 2018 10:45:41 +0000 (10:45 +0000)]
[X86] Just use ArrayRef instead of SmallVectorImpl in a few static method arguments. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335590
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Andrea Di Biagio [Tue, 26 Jun 2018 10:44:12 +0000 (10:44 +0000)]
[llvm-mca] Remove unused header files and correctly guard some include headers under NDEBUG. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335589
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Florian Hahn [Tue, 26 Jun 2018 10:15:02 +0000 (10:15 +0000)]
[IPSCCP] Change dead blocks to unreachable after visiting all executable blocks.
changeToUnreachable may remove PHI nodes from executable blocks we found values
for and we would fail to replace them. By changing dead blocks to unreachable after
we replaced constants in all executable blocks, we ensure such PHI nodes are replaced
by their known value before.
Fixes PR37780.
Reviewers: efriedma, davide
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D48421
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335588
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Simon Pilgrim [Tue, 26 Jun 2018 10:02:12 +0000 (10:02 +0000)]
Fix MSVC "signed/unsigned mismatch" warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335587
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Bernard Ogden [Tue, 26 Jun 2018 09:49:31 +0000 (09:49 +0000)]
[AArch64] Tighten up directives tests
Move expected-fail cases from directive-cpu.s to
directive-cpu-err.s. This allows us to remove the 'not' from the
llvm-mc invocation in directive-cpu.s so that this test will fail
in unexpected error cases. It also means that we are not relying
on all stderr coming before any stdout, which seems fragile.
Also make use of CHECK-NEXT to ensure that multiline error messages
really are occuring together.
And add a test to verify that .cpu with an arch version as extension
is rejected.
Differential Revision: https://reviews.llvm.org/D47873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335586
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Bernard Ogden [Tue, 26 Jun 2018 09:36:13 +0000 (09:36 +0000)]
[AArch64] Clean up LSE directive tests
These were specifying an architecture version with .cpu directive,
which is invalid. As the error for this case outputs the problem
instruction we were still matching the expectations of FileCheck.
This patch fixes up the LSE tests to do what they seem to intend. A
follow-up patch will tighten up the directive tests.
Differential Revision: https://reviews.llvm.org/D47872
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335585
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