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Eric Christopher [Fri, 14 Oct 2016 17:28:23 +0000 (17:28 +0000)]
Revert "In preparation for removing getNameWithPrefix off of
TargetMachine," as it's causing sanitizer/memory issues until I
can track down this set.
This reverts commit r284203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284252
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Vedant Kumar [Fri, 14 Oct 2016 17:16:53 +0000 (17:16 +0000)]
[Coverage] Support loading multiple binaries into a CoverageMapping
Add support for loading multiple coverage readers into a single
CoverageMapping instance. This should make it easier to prepare a
unified coverage report for multiple binaries.
Differential Revision: https://reviews.llvm.org/D25535
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284251
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Rafael Espindola [Fri, 14 Oct 2016 17:01:39 +0000 (17:01 +0000)]
Move alignTo computation inside the if.
This is an improvement when compiling with llvm. llvm doesn't inline
the call to insert, so the align is always executed and shows up in
the profile.
With gcc the call to insert is inlined and the align computation moved
and done only if needed.
With this patch we explicitly only compute it if it is needed.
In the two tests with debug info, the speedup was
scylla
master 3.
008959365
patch 2.
932080942 1.02621974786x faster
firefox
master 6.
709823604
patch 6.
592387227 1.01781393795x faster
In all others the difference was in the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284249
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Pierre Gousseau [Fri, 14 Oct 2016 16:41:38 +0000 (16:41 +0000)]
[X86] Take advantage of the lzcnt instruction on btver2 architectures when ORing comparisons to zero.
This change adds transformations such as:
zext(or(setcc(eq, (cmp x, 0)), setcc(eq, (cmp y, 0))))
To:
srl(or(ctlz(x), ctlz(y)), log2(bitsize(x))
This optimisation is beneficial on Jaguar architecture only, where lzcnt has a good reciprocal throughput.
Other architectures such as Intel's Haswell/Broadwell or AMD's Bulldozer/PileDriver do not benefit from it.
For this reason the change also adds a "HasFastLZCNT" feature which gets enabled for Jaguar.
Differential Revision: https://reviews.llvm.org/D23446
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284248
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Sanjay Patel [Fri, 14 Oct 2016 16:31:54 +0000 (16:31 +0000)]
[InstCombine] use m_APInt to allow sub with constant folds for splat vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284247
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Mehdi Amini [Fri, 14 Oct 2016 16:23:09 +0000 (16:23 +0000)]
[docs] Update some obsolete information in BitCodeFormat docs.
Summary:
* Describe new (3.3) parameter attribute group encoding, leaving old encoding there with a note about legacy
* Bring TYPE_BLOCK docs up to date
* Remove docs about obsolete (pre 3.0) TYPE_SYMTAB_BLOCK, TST_CODE_ENTRY
* Fix a couple of incorrect comments and remove one unused enum definition along the way
This addresses https://llvm.org/bugs/show_bug.cgi?id=28941.
Patch by: Ismail Badawi <ibadawi@cisco.com>
Differential Revision: https://reviews.llvm.org/D25623
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284246
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Sanjay Patel [Fri, 14 Oct 2016 15:55:34 +0000 (15:55 +0000)]
[InstCombine] add tests for missing vector folds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284245
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Sanjay Patel [Fri, 14 Oct 2016 15:41:25 +0000 (15:41 +0000)]
[InstCombine] auto-generate checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284244
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Sanjay Patel [Fri, 14 Oct 2016 15:36:28 +0000 (15:36 +0000)]
[InstCombine] remove redundant test
This test was apparently checking for 2 independent folds, but we have
plenty of tests for those individual folds already. We are lacking
vector tests, however, because we don't have the shift folds for vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284243
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Sanjay Patel [Fri, 14 Oct 2016 15:30:31 +0000 (15:30 +0000)]
[InstCombine] update test to use FileCheck and auto-generate checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284242
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Sanjay Patel [Fri, 14 Oct 2016 15:24:31 +0000 (15:24 +0000)]
[InstCombine] sub X, sext(bool Y) -> add X, zext(bool Y)
Prefer add/zext because they are better supported in terms of value-tracking.
Note that the backend should be prepared for this IR canonicalization
(including vector types) after:
https://reviews.llvm.org/rL284015
Differential Revision: https://reviews.llvm.org/D25135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284241
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David L Kreitzer [Fri, 14 Oct 2016 14:41:46 +0000 (14:41 +0000)]
Define "contiki" OS specifier.
Patch by Michael LeMay
Differential revision: http://reviews.llvm.org/D24897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284240
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Sanjay Patel [Fri, 14 Oct 2016 14:26:47 +0000 (14:26 +0000)]
[DAG] add folds for negated shifted sign bit
The same folds exist in InstCombine already.
This came up as part of:
https://reviews.llvm.org/D25485
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284239
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Sanjay Patel [Fri, 14 Oct 2016 14:14:40 +0000 (14:14 +0000)]
[x86] add tests to show missing folds for negated shifted sign bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284238
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Nicolai Haehnle [Fri, 14 Oct 2016 10:30:00 +0000 (10:30 +0000)]
AMDGPU: Select 64-bit {ADD,SUB}{C,E} nodes
Summary:
This will be used for 64-bit MULHU, which is in turn used for the 64-bit
divide-by-constant optimization (see D24822).
Reviewers: arsenm, tstellarAMD
Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284224
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Diana Picus [Fri, 14 Oct 2016 10:19:40 +0000 (10:19 +0000)]
[GlobalISel] Get the AArch64 tests to work on Linux
Mostly this just means changing the triple from aarch64-apple-ios to the generic
aarch64--. Only one test needs more significant changes, but GlobalISel already
does the right thing so it's ok to just change the checks.
Differential Revision: https://reviews.llvm.org/D25532
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284223
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Nicolai Haehnle [Fri, 14 Oct 2016 09:49:51 +0000 (09:49 +0000)]
Fix use-after-frees
Extracted from D25313, as suggested by Justin Bogner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284220
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Simon Dardis [Fri, 14 Oct 2016 09:31:42 +0000 (09:31 +0000)]
[mips] Fix aui/daui/dahi/dati for MIPSR6
For compatiblity with binutils, define these instructions to take
two registers with a 16bit unsigned immediate. Both of the registers
have to be same for dahi and dati.
Reviewers: dsanders, zoran.jovanovic
Differential Review: https://reviews.llvm.org/D21473
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284218
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Nicolai Haehnle [Fri, 14 Oct 2016 09:03:04 +0000 (09:03 +0000)]
AMDGPU: Fix use-after-frees
Reviewers: arsenm, tstellarAMD
Subscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284215
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Michael Zuckerman [Fri, 14 Oct 2016 08:09:40 +0000 (08:09 +0000)]
[x86][ms-inline-asm] use of "jmp short" in asm is not supported
Committing in the name of Ziv Izhar: After check-all and LGTM .
The following patch is for compatability with Microsoft.
Microsoft ignores the keyword "short" when used after a jmp, for example:
__asm {
jmp short label
label:
}
A test for that patch will be added in another patch, since it's located in clang's codegen tests. Link will be added shortly.
link to test: https://reviews.llvm.org/D24958
Differential Revision: https://reviews.llvm.org/D24957
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284211
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Craig Topper [Fri, 14 Oct 2016 06:00:42 +0000 (06:00 +0000)]
[DAGCombiner] Teach createBuildVecShuffle to handle cases where input vectors are less than half of the output vector size.
This will be needed by a future commit to support sign/zero extending from v8i8 to v8i64 which requires a sign/zero_extend_vector_inreg to be created which requires v8i8 to be concatenated upto v64i8 and goes through this code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284204
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Eric Christopher [Fri, 14 Oct 2016 05:47:41 +0000 (05:47 +0000)]
In preparation for removing getNameWithPrefix off of TargetMachine,
sink the current behavior into the callers and sink
TargetMachine::getNameWithPrefix into TargetMachine::getSymbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284203
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Eric Christopher [Fri, 14 Oct 2016 05:47:37 +0000 (05:47 +0000)]
Tidy the calls to getCurrentSection().first -> getCurrentSectionOnly to help
readability a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284202
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Eric Christopher [Fri, 14 Oct 2016 05:45:46 +0000 (05:45 +0000)]
Tidy up example of getting the pointer size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284201
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Konstantin Zhuravlyov [Fri, 14 Oct 2016 04:37:34 +0000 (04:37 +0000)]
[AMDGPU] Emit 32-bit lo/hi got and pc relative variant kinds for external and global address space variables
Differential Revision: https://reviews.llvm.org/D25562
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284196
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Konstantin Zhuravlyov [Fri, 14 Oct 2016 04:21:32 +0000 (04:21 +0000)]
[AMDGPU] Add 32-bit lo/hi got and pc relative variant kinds and emit appropriate relocations
Differential Revision: https://reviews.llvm.org/D25548
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284195
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Konstantin Zhuravlyov [Fri, 14 Oct 2016 04:03:49 +0000 (04:03 +0000)]
[Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations
Added relocation names:
- R_AMDGPU_GOTPCREL32_LO
- R_AMDGPU_GOTPCREL32_HI
- R_AMDGPU_REL32_LO
- R_AMDGPU_REL32_HI
AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above.
Differential Revision: https://reviews.llvm.org/D25546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284191
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Mehdi Amini [Fri, 14 Oct 2016 03:54:46 +0000 (03:54 +0000)]
Add `llvm::` in clEnumVal macro (NFC)
This allows to use llvm:cl::opt without `using namespace llvm;`
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284190
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Matthias Braun [Fri, 14 Oct 2016 00:17:19 +0000 (00:17 +0000)]
Timer: Fix doxygen comments, use member initializer; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284181
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Teresa Johnson [Fri, 14 Oct 2016 00:13:59 +0000 (00:13 +0000)]
Add interface for querying physical hardware concurrency
Summary:
This will be used by ThinLTO to set the amount of backend
parallelism, which performs better when restricted to the number
of physical cores (on X86 at least, where getHostNumPhysicalCores is
currently defined). If not available this falls back to
thread::hardware_concurrency.
Note I didn't add to the thread class since that is a typedef to
std::thread where available.
Reviewers: mehdi_amini
Subscribers: beanz, llvm-commits, mgorny
Differential Revision: https://reviews.llvm.org/D25585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284180
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Saleem Abdulrasool [Thu, 13 Oct 2016 23:00:11 +0000 (23:00 +0000)]
CodeGen: use MSVC division on windows itanium
Windows itanium is identical to MSVC when dealing with everything but C++.
Lower the math routines into msvcrt rather than compiler-rt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284175
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Saleem Abdulrasool [Thu, 13 Oct 2016 22:38:15 +0000 (22:38 +0000)]
CodeGen: adjust floating point operations in Windows itanium
Windows itanium is equivalent to MSVC except in C++ mode. Ensure that the
promote the 32-bit floating point operations to their 64-bit equivalences.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284173
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Sanjay Patel [Thu, 13 Oct 2016 22:27:10 +0000 (22:27 +0000)]
[DAG] hoist DL(N) and fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284170
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Kostya Serebryany [Thu, 13 Oct 2016 22:24:10 +0000 (22:24 +0000)]
[libFuzzer] more detailed message for disabled leak detection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284169
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Tom Stellard [Thu, 13 Oct 2016 21:03:49 +0000 (21:03 +0000)]
LegalizeDAG: Implement PROMOTE for ISD::BITREVERSE
Summary:
This operation is promoted the same way was ISD::BSWAP. This will
prevent a regression in test/Target/AMDGOU/bitreverse.ll when i16
support is implemented.
Reviewers: bogner, hfinkel
Subscribers: hfinkel, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D25202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284163
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David L Kreitzer [Thu, 13 Oct 2016 20:57:51 +0000 (20:57 +0000)]
[safestack] Reapply r283248 after moving X86-targeted SafeStack tests into
the X86 subdirectory. Original commit message:
Requires a valid TargetMachine to be passed to the SafeStack pass.
Patch by Michael LeMay
Differential revision: http://reviews.llvm.org/D24896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284161
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Sriraman Tallam [Thu, 13 Oct 2016 20:54:39 +0000 (20:54 +0000)]
New llc option pie-copy-relocations to optimize access to extern globals.
This option indicates copy relocations support is available from the linker
when building as PIE and allows accesses to extern globals to avoid the GOT.
Differential Revision: https://reviews.llvm.org/D24849
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284160
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Nirav Dave [Thu, 13 Oct 2016 20:23:25 +0000 (20:23 +0000)]
Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."
This reverts commit r284151 which appears to be triggering a LTO
failures on Hexagon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284157
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Quentin Colombet [Thu, 13 Oct 2016 19:27:48 +0000 (19:27 +0000)]
[RAGreedy] Empty live-ranges always succeed in last chance recoloring.
Relax the constraint for empty live-ranges while doing last chance
recoloring. Indeed, those live-ranges do not need an actual color to be
fond for the recoloring to work.
Empty live-range may happen as a result of splitting/spilling.
Unfortunately no test case for in-tree targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284152
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Nirav Dave [Thu, 13 Oct 2016 19:20:16 +0000 (19:20 +0000)]
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Retrying after upstream changes.
Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search which only checks for parallel stores
through the chain subgraph. This is cleaner as the separation of
non-interfering loads/stores from the store-merging logic.
Whem merging stores, search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited. This improves the quality of the
output SelectionDAG and generally the output CodeGen (with some
exceptions).
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the the chain aggregation in the merged stores across
code paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seemed sufficient to not cause regressions in
tests.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable. Some tests relying on the order were changed to use
volatile memory operations
Noteworthy tests:
CodeGen/AArch64/argument-blocks.ll -
It's not entirely clear what the test_varargs_stackalign test is
supposed to be asserting, but the new code looks right.
CodeGen/AArch64/arm64-memset-inline.lli -
CodeGen/AArch64/arm64-stur.ll -
CodeGen/ARM/memset-inline.ll -
The backend now generates *worse* code due to store merging
succeeding, as we do do a 16-byte constant-zero store efficiently.
CodeGen/AArch64/merge-store.ll -
Improved, but there still seems to be an extraneous vector insert
from an element to itself?
CodeGen/PowerPC/ppc64-align-long-double.ll -
Worse code emitted in this case, due to the improved store->load
forwarding.
CodeGen/X86/dag-merge-fast-accesses.ll -
CodeGen/X86/MergeConsecutiveStores.ll -
CodeGen/X86/stores-merging.ll -
CodeGen/Mips/load-store-left-right.ll -
Restored correct merging of non-aligned stores
CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll -
Improved. Correctly merges buffer_store_dword calls
CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll -
Improved. Sidesteps loading a stored value and
merges two stores
CodeGen/X86/pr18023.ll -
This test has been removed, as it was asserting incorrect
behavior. Non-volatile stores *CAN* be moved past volatile loads,
and now are.
CodeGen/X86/vector-idiv.ll -
CodeGen/X86/vector-lzcnt-128.ll -
It's basically impossible to tell what these tests are actually
testing. But, looks like the code got better due to the memory
operations being recognized as non-aliasing.
CodeGen/X86/win32-eh.ll -
Both loads of the securitycookie are now merged.
CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll -
This test appears to work but no longer exhibits the spill behavior.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
Subscribers: wdng, nhaehnle, nemanjai, arsenm, weimingz, niravd, RKSimon, aemerson, qcolombet, dsanders, resistor, tstellarAMD, t.p.northover, spatel
Differential Revision: https://reviews.llvm.org/D14834
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284151
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Kostya Serebryany [Thu, 13 Oct 2016 19:06:46 +0000 (19:06 +0000)]
[libFuzzer] add -trace_malloc= flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284149
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Quentin Colombet [Thu, 13 Oct 2016 18:46:38 +0000 (18:46 +0000)]
[AArch64][RegisterBankInfo] Switch to fully static opds mapping for G_BITCAST.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284146
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David L Kreitzer [Thu, 13 Oct 2016 17:51:59 +0000 (17:51 +0000)]
[safestack] Move X86-targeted tests into the X86 subdirectory.
Patch by Michael LeMay
Differential revision: http://reviews.llvm.org/D25340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284139
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Teresa Johnson [Thu, 13 Oct 2016 17:43:20 +0000 (17:43 +0000)]
Add interface to compute number of physical cores on host system
Summary:
For now I have only added support for x86_64 Linux, but other systems
can be added incrementally.
This is to be used for setting the default parallelism for ThinLTO
backends (instead of thread::hardware_concurrency which includes
hyperthreading and is too aggressive). I'll send this as a follow-on
patch, and it will fall back to hardware_concurrency when the new
getHostNumPhysicalCores returns -1 (when not supported for a given
host system).
I also added an interface to MemoryBuffer to force reading a file
as a stream - this is required for /proc/cpuinfo which is a special
file that looks like a normal file but appears to have 0 size.
The existing readers of this file in Host.cpp are reading the first
1024 or so bytes from it, because the necessary info is near the top.
But for the new functionality we need to be able to read the entire
file. I can go back and change the other readers to use the new
getFileAsStream as a follow-on patch since it seems much more robust.
Added a unittest.
Reviewers: mehdi_amini
Subscribers: beanz, mgorny, llvm-commits, modocache
Differential Revision: https://reviews.llvm.org/D25564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284138
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Reid Kleckner [Thu, 13 Oct 2016 17:33:22 +0000 (17:33 +0000)]
Truncate long names in type records
In the MS ABI, the frontend is supposed to MD5 such pathologically long
names. LLVM should still defend itself from long names, though.
Fixes part of PR29098.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284136
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Vedant Kumar [Thu, 13 Oct 2016 17:22:44 +0000 (17:22 +0000)]
[unittests] Remove a redundant test fixture (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284135
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Igor Breger [Thu, 13 Oct 2016 17:20:38 +0000 (17:20 +0000)]
[X86][AVX512] Fix sext v32i1 -> v32i8 lowering.
Fix PR30600.
Differential Revision: https://reviews.llvm.org/D25554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284134
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Kostya Serebryany [Thu, 13 Oct 2016 16:19:09 +0000 (16:19 +0000)]
[libFuzzer] reapply r283946: refactoring to speed things up, NFC. Now with a fix for gcc build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284132
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Reid Kleckner [Thu, 13 Oct 2016 15:48:48 +0000 (15:48 +0000)]
Fix for PR30687. Avoid dereferencing MBB.end().
We don't need to return a MachineInstr* from these stack probe insertion
calls anyway. If we ever need to add it back, we can return an iterator
instead.
Based on a patch by David Kreitzer
This bug is a consequence of
r279314 | dexonsmith | 2016-08-19 13:40:12 -0700 (Fri, 19 Aug 2016) | 110 lines
We hit the "Assertion `!NodePtr->isKnownSentinel()' failed" assertion,
but only when inserting a stack probe call at the end of an MBB, which
isn't necessarily a common situation.
Differential Revision: https://reviews.llvm.org/D25566
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284130
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Eric Liu [Thu, 13 Oct 2016 15:07:14 +0000 (15:07 +0000)]
Do not delete leading ../ in remove_dots.
Reviewers: bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D25561
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284129
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Javed Absar [Thu, 13 Oct 2016 14:57:43 +0000 (14:57 +0000)]
[ARM]: Assign cost of scaling used in addressing mode for ARM cores
This patch assigns cost of the scaling used in addressing.
On many ARM cores, a negated register offset takes longer than a
non-negated register offset, in a register-offset addressing mode.
For instance:
LDR R0, [R1, R2 LSL #2]
LDR R0, [R1, -R2 LSL #2]
Above, (1) takes less cycles than (2).
By assigning appropriate scaling factor cost, we enable the LLVM
to make the right trade-offs in the optimization and code-selection phase.
Differential Revision: http://reviews.llvm.org/D24857
Reviewers: jmolloy, rengolin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284127
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Matthew Simpson [Thu, 13 Oct 2016 14:54:31 +0000 (14:54 +0000)]
[LV] Account for predicated stores in instruction costs
This patch ensures that we scale the estimated cost of predicated stores by
block probability. This is a follow-on patch for r284123.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284126
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Sanjay Patel [Thu, 13 Oct 2016 14:27:08 +0000 (14:27 +0000)]
[x86] add negate-i1 run for 32-bit target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284124
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Matthew Simpson [Thu, 13 Oct 2016 14:19:48 +0000 (14:19 +0000)]
[LV] Avoid rounding errors for predicated instruction costs
This patch modifies the cost calculation of predicated instructions (div and
rem) to avoid the accumulation of rounding errors due to multiple truncating
integer divisions. The calculation for predicated stores will be addressed in a
follow-on patch since we currently don't scale the cost of predicated stores by
block probability.
Differential Revision: https://reviews.llvm.org/D25333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284123
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Simon Pilgrim [Thu, 13 Oct 2016 14:04:35 +0000 (14:04 +0000)]
[DAGCombiner] Add vector support to (mul (shl X, Y), Z) -> (shl (mul X, Z), Y) style combines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284122
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Matt Arsenault [Thu, 13 Oct 2016 13:10:00 +0000 (13:10 +0000)]
AMDGPU: Assume spilling will occur at -O0
Because everything live is spilled at the end of a
block by fast regalloc, assume this will happen and
avoid the copies of the resource descriptor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284119
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Simon Pilgrim [Thu, 13 Oct 2016 12:54:32 +0000 (12:54 +0000)]
Copy+pasts typo in comment describing combine test
Repeated the "fold (mul x, 0) -> 0" instead of "fold (mul x, 1) -> x"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284118
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Simon Pilgrim [Thu, 13 Oct 2016 12:49:31 +0000 (12:49 +0000)]
[DAGCombiner] Add vector support to C2-(A+C1) -> (C2-C1)-A folding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284117
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Matt Arsenault [Thu, 13 Oct 2016 12:45:16 +0000 (12:45 +0000)]
AMDGPU: Fix truncate to bool warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284116
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Simon Dardis [Thu, 13 Oct 2016 12:12:56 +0000 (12:12 +0000)]
[mips] Add IAS support for dvp, evp
These instructions were only defined for microMIPSR6 previously. Add
definitions for MIPSR6, correct definitions for microMIPSR6, flag these
instructions as having unmodelled side effects (they disable/enable
virtual processors) and add missing disassember tests for microMIPSR6.
Reviewers: vkalintiris
Differential Review: https://reviews.llvm.org/D24291
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284115
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Simon Pilgrim [Thu, 13 Oct 2016 12:05:20 +0000 (12:05 +0000)]
[DAGCombiner] Add vector support to (sub -1, x) -> (xor x, -1) canonicalization
Improves commutation potential
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284113
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Oren Ben Simhon [Thu, 13 Oct 2016 07:53:43 +0000 (07:53 +0000)]
[X86] Basic additions to support RegCall Calling Convention.
The Register Calling Convention (RegCall) was introduced by Intel to optimize parameter transfer on function call.
This calling convention ensures that as many values as possible are passed or returned in registers.
This commit presents the basic additions to LLVM CodeGen in order to support RegCall in X86.
Differential Revision: http://reviews.llvm.org/D25022
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284108
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Daniel Jasper [Thu, 13 Oct 2016 06:39:44 +0000 (06:39 +0000)]
Silence unused warning in non-assert builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284107
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Craig Topper [Thu, 13 Oct 2016 05:41:01 +0000 (05:41 +0000)]
[AVX-512] Fix v16i32 zero extending shuffle test case so it's really zero extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284106
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Craig Topper [Thu, 13 Oct 2016 05:29:41 +0000 (05:29 +0000)]
[AVX-512] Teach shuffle lowering to recognize 512-bit zero extends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284105
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Craig Topper [Thu, 13 Oct 2016 05:29:37 +0000 (05:29 +0000)]
[AVX-512] Add tests for basic 512-bit zero extending shuffle patterns. Code will be improved in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284104
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Diana Picus [Thu, 13 Oct 2016 05:28:55 +0000 (05:28 +0000)]
Remove a FIXME that I forgot about. NFC.
Sorry about the noise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284103
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Craig Topper [Thu, 13 Oct 2016 04:14:47 +0000 (04:14 +0000)]
[X86] Simplify the lowering code for extracting and inserting subvectors.
We don't need to check if AVX is enabled. It's implied by the operation action being set to Custom.
We don't need to check both the input and output type widths. We only need to check the type that's being inserted or extracted. The other type is known to be a legal type and we can assume its a different width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284102
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Sebastian Pop [Thu, 13 Oct 2016 03:23:33 +0000 (03:23 +0000)]
Memory-SSA: strengthen defClobbersUseOrDef interface
As Danny pointed out, defClobbersUseOrDef should use MemoryLocOrCall to make
sure fences are properly handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284099
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Sebastian Pop [Thu, 13 Oct 2016 01:39:10 +0000 (01:39 +0000)]
commit back "GVN-hoist: fix store past load dependence analysis (PR30216, PR30499)"
This is with an extra change to avoid calling MemoryLocation::get() on a call instruction.
Differential Revision: https://reviews.llvm.org/D25542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284098
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Quentin Colombet [Thu, 13 Oct 2016 01:01:23 +0000 (01:01 +0000)]
[AArch64][RegisterBankInfo] Provide alternative mappings for 64-bit load
This allows RegBankSelect in greedy mode to get rid some of the cross
register bank copies when loads are involved in the chain of
computation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284097
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Reid Kleckner [Thu, 13 Oct 2016 00:55:24 +0000 (00:55 +0000)]
Correct PrivateLinkage for COFF
- Use storage class C_STAT for 'PrivateLinkage' The storage class for
PrivateLinkage should equal to the Internal Linkage.
- Set 'PrivateGlobalPrefix' from "L" to ".L" for MM_WinCOFF (includes
x86_64) MM_WinCOFF has empty GlobalPrefix '\0' so PrivateGlobalPrefix
"L" may conflict to the normal symbol name starting with 'L'.
Based on a patch by Han Sangjin! Manually updated test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284096
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Quentin Colombet [Thu, 13 Oct 2016 00:34:48 +0000 (00:34 +0000)]
[AArch64][RegisterBankInfo] Provide alternative mappings for G_BITCASTs.
Thanks to this patch, RegBankSelect is able to get rid of some register
bank copies as demonstrated in the test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284094
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Reid Kleckner [Thu, 13 Oct 2016 00:18:26 +0000 (00:18 +0000)]
Revert "GVN-hoist: fix store past load dependence analysis (PR30216, PR30499)"
This CL didn't actually address the test case in PR30499, and clang
still crashes.
Also revert dependent change "Memory-SSA cleanup of clobbers interface, NFC"
Reverts r283965 and r283967.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284093
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Quentin Colombet [Thu, 13 Oct 2016 00:12:06 +0000 (00:12 +0000)]
[AArch64][RegisterBankInfo] Describe cross regbank copies statically.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284091
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Quentin Colombet [Thu, 13 Oct 2016 00:12:04 +0000 (00:12 +0000)]
[AArch64][RegisterBankInfo] Use static mapping for same bank G_BITCAST.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284090
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Quentin Colombet [Thu, 13 Oct 2016 00:12:01 +0000 (00:12 +0000)]
[AArch64][MachineLegalizer] Mark more G_BITCAST as legal.
Basically any vector types that fits in a 32-bit register is also valid
as far as copies are concerned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284089
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Quentin Colombet [Thu, 13 Oct 2016 00:11:59 +0000 (00:11 +0000)]
[AArch64][RegisterBankInfo] Bump the cost of vector loads.
This does not change anything yet, because we do not offer any
alternative mapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284088
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Quentin Colombet [Thu, 13 Oct 2016 00:11:57 +0000 (00:11 +0000)]
[AArch64][RegisterBankInfo] Use a proper cost for cross regbank G_BITCASTs.
This does not change anything yet, because we do not offer any
alternative mapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284087
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Quentin Colombet [Thu, 13 Oct 2016 00:11:55 +0000 (00:11 +0000)]
[AArch64][RegisterBankInfo] Provide more realistic copy costs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284086
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Albert Gutowski [Wed, 12 Oct 2016 23:58:45 +0000 (23:58 +0000)]
fix function label name in addressofreturnaddress test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284085
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Mehdi Amini [Wed, 12 Oct 2016 23:36:11 +0000 (23:36 +0000)]
[GitHubMove Doc] Properly nest a subsection in the proposal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284082
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Albert Gutowski [Wed, 12 Oct 2016 23:10:02 +0000 (23:10 +0000)]
fix title underline length
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284078
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Mehdi Amini [Wed, 12 Oct 2016 23:02:02 +0000 (23:02 +0000)]
Moving to GitHub - Unified Proposal
This document describes the proposal to move to GitHub, and
compare the two proposals through various workflow examples,
presenting the current set of commands following by the ones
involved in each of the two proposals.
It is intended to supersede the previous "submodule proposal"
document entirely, and drive the discussion at the BoF during
the next Dev Meeting.
Differential Revision: https://reviews.llvm.org/D24167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284077
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Krzysztof Parzyszek [Wed, 12 Oct 2016 22:53:41 +0000 (22:53 +0000)]
Handle lane masks in LivePhysRegs when adding live-ins
Differential Revision: https://reviews.llvm.org/D25533
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284076
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Tim Northover [Wed, 12 Oct 2016 22:49:15 +0000 (22:49 +0000)]
GlobalISel: support G_TRUNC selection on AArch64.
Ahmed's patch again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284075
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Tim Northover [Wed, 12 Oct 2016 22:49:11 +0000 (22:49 +0000)]
GlobalISel: support int <-> float conversions on AArch64.
More of Ahmed's work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284074
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Tim Northover [Wed, 12 Oct 2016 22:49:07 +0000 (22:49 +0000)]
GlobalISel: select G_FCMP instructions on AArch64.
Another of Ahmed's patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284073
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Tim Northover [Wed, 12 Oct 2016 22:49:04 +0000 (22:49 +0000)]
GlobalISel: support selection of G_ICMP on AArch64.
Patch from Ahmed Bougaca again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284072
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Tim Northover [Wed, 12 Oct 2016 22:49:01 +0000 (22:49 +0000)]
GlobalISel: select G_BRCOND instructions on AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284071
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Tim Northover [Wed, 12 Oct 2016 22:48:36 +0000 (22:48 +0000)]
GlobalISel: mark G_BRCOND on s1 as legal.
It's going to be a TBNZ (at -O0) anyway, so the high bits don't matter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284070
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Vedant Kumar [Wed, 12 Oct 2016 22:44:50 +0000 (22:44 +0000)]
[unittests] Delete even more copy constructors (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284069
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Vedant Kumar [Wed, 12 Oct 2016 22:27:54 +0000 (22:27 +0000)]
[unittests] Delete some copy constructors (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284066
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Vedant Kumar [Wed, 12 Oct 2016 22:27:52 +0000 (22:27 +0000)]
[unittest] Pass a reference instead of making a copy (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284065
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Vedant Kumar [Wed, 12 Oct 2016 22:27:49 +0000 (22:27 +0000)]
[Coverage] Delete some copy constructors (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284064
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Vedant Kumar [Wed, 12 Oct 2016 22:27:45 +0000 (22:27 +0000)]
[Coverage] Factor out logic to create FunctionRecords (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284063
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Albert Gutowski [Wed, 12 Oct 2016 22:13:19 +0000 (22:13 +0000)]
Create llvm.addressofreturnaddress intrinsic
Summary: We need a new LLVM intrinsic to implement MS _AddressOfReturnAddress builtin on 64-bit Windows.
Reviewers: majnemer, rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D25293
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284061
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Reid Kleckner [Wed, 12 Oct 2016 21:51:14 +0000 (21:51 +0000)]
Update _MSC_VER equality checks for msdiaNNN.dll
Use inequality instead of equality to defend against minor version
increases in _MSC_VER. An _MSC_VER value of 1901 should still use
msdia140.dll, as described in this blog post:
https://blogs.msdn.microsoft.com/vcblog/2016/10/05/visual-c-compiler-version/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284058
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Michal Gorny [Wed, 12 Oct 2016 21:40:08 +0000 (21:40 +0000)]
[lit] Fix test shtest-timeout.py for modern output
Update the CHECK lines in the shtest-timeout.py lit test to account for
the current output. The output has been changed in r271610 without
adjusting the tests.
Differential Revision: https://reviews.llvm.org/D25236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284057
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Michal Gorny [Wed, 12 Oct 2016 21:40:04 +0000 (21:40 +0000)]
[lit] Fix FormatError on individual test timeout
Differential Revision: https://reviews.llvm.org/D25195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284056
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