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Roman Tereshin [Fri, 1 Jun 2018 23:15:09 +0000 (23:15 +0000)]
[DebugInfo] Refactoring DIType::setFlags to DIType::cloneWithFlags, NFC
and using the latter in DIBuilder::createArtificialType and
DIBuilder::createObjectPointerType methods as well as introducing
mirroring DISubprogram::cloneWithFlags and
DIBuilder::createArtificialSubprogram methods.
The primary goal here is to add createArtificialSubprogram to support
a pass downstream while keeping the method consistent with the
existing ones and making sure we don't encourage changing already
created DI-nodes.
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D47615
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333806
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Chris Bieneman [Fri, 1 Jun 2018 23:09:37 +0000 (23:09 +0000)]
Revert "Re-land: [MachO] Fixing ub in MachO BinaryFormat"
This reverts commit r333803.
Still breaking on big endian. Will sort this out later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333805
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Craig Topper [Fri, 1 Jun 2018 22:59:07 +0000 (22:59 +0000)]
[X86] Do something sensible when an expand load intrinsic is passed a 0 mask.
Previously we just returned undef, but really we should be returning the pass thru input. We also need to make sure we preserve the chain output that the original intrinsic node had to maintain connectivity in the DAG. So we should just return the incoming chain as the output chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333804
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Chris Bieneman [Fri, 1 Jun 2018 22:52:59 +0000 (22:52 +0000)]
Re-land: [MachO] Fixing ub in MachO BinaryFormat
This re-lands r333797 with a fix for big endian systems.
Original commit message:
This isn't encountered anywhere inside LLVM, so I wrote a test case to expose the issue and verify that it is fixed.
The basic problem is that the macho_load_command union contains all load comamnd structs. Load command structs in 32-bit macho files can be 32-bit aligned instead of 64-bit aligned.
There are some strange circumstances in which this can be exposed in a 64-bit macho if the load commands are invalid or if a 32-bit aligned load command is used. In the past we've worked around this type of problem with changes like r264232.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333803
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Vedant Kumar [Fri, 1 Jun 2018 22:33:15 +0000 (22:33 +0000)]
Add a debug dump for DbgValueHistoryMap
This makes it easier to inspect the results of
DbgValueHistoryCalculator.
Differential Revision: https://reviews.llvm.org/D47663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333801
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Craig Topper [Fri, 1 Jun 2018 22:28:28 +0000 (22:28 +0000)]
[X86] Add isel patterns to use vexpand with zero masking when the passthru value is a zero vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333800
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Chris Bieneman [Fri, 1 Jun 2018 22:28:23 +0000 (22:28 +0000)]
Revert "[MachO] Fixing ub in MachO BinaryFormat"
This reverts commit r333797.
This patch is failing on BigEndian bots. I will fix and re-land:
http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/19505/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333799
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Zachary Turner [Fri, 1 Jun 2018 22:23:46 +0000 (22:23 +0000)]
Move some function declarations out of WindowsSupport.h
The idea behind WindowsSupport.h is that it's in the source directory so
that windows.h'isms don't leak out into the larger LLVM project. To that
end, any symbol that references a symbol from windows.h must be in this
private header, and not in a public header.
However, we had some useful utility functions in WindowsSupport.h which
have no dependency on the Windows API, but still only make sense on
Windows. Those functions should be usable outside of Support since there
is no risk of causing a windows.h leak. Although this introduces some
preprocessor logic in some header files, It's not too egregious and it's
better than the alternative of duplicating a ton of code.
Differential Revision: https://reviews.llvm.org/D47662
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333798
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Chris Bieneman [Fri, 1 Jun 2018 22:07:36 +0000 (22:07 +0000)]
[MachO] Fixing ub in MachO BinaryFormat
This isn't encountered anywhere inside LLVM, so I wrote a test case to expose the issue and verify that it is fixed.
The basic problem is that the macho_load_command union contains all load comamnd structs. Load command structs in 32-bit macho files can be 32-bit aligned instead of 64-bit aligned.
There are some strange circumstances in which this can be exposed in a 64-bit macho if the load commands are invalid or if a 32-bit aligned load command is used. In the past we've worked around this type of problem with changes like r264232.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333797
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Craig Topper [Fri, 1 Jun 2018 21:59:24 +0000 (21:59 +0000)]
[X86] Expand the testing of expand and compress intrinsics
The avx512f intrinsic tests were in the avx512vl file. We were also missing some combinations of masking.
This does show that we fail to use the zero masking form of expand loads when the passthru is zero. I'll try to get that fixed shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333795
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Craig Topper [Fri, 1 Jun 2018 21:59:22 +0000 (21:59 +0000)]
[X86] Add fast-isel tests for avx512vbmi2 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333794
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Karl-Johan Karlsson [Fri, 1 Jun 2018 19:34:35 +0000 (19:34 +0000)]
[ConstantFold] Disallow folding vector geps into bitcasts
Summary:
Getelementptr returns a vector of pointers, instead of a single address,
when one or more of its arguments is a vector. In such case it is not
possible to simplify the expression by inserting a bitcast of operand(0)
into the destination type, as it will create a bitcast between different
sizes.
Reviewers: majnemer, mkuper, mssimpso, spatel
Reviewed By: spatel
Subscribers: lebedev.ri, llvm-commits
Differential Revision: https://reviews.llvm.org/D46379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333783
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Sanjay Patel [Fri, 1 Jun 2018 19:23:18 +0000 (19:23 +0000)]
[InstCombine] fix vector shuffle transform to replace undef elements (PR37648)
This bug:
https://bugs.llvm.org/show_bug.cgi?id=37648
...was created with the enhancement to this transform with rL332479.
The urem test shows the disaster potential: any undef divisor lane makes
the whole op undef.
The test diffs show that vector demanded elements turns some of the potential,
but not all, unused binop operands back into undef already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333782
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Sanjay Patel [Fri, 1 Jun 2018 18:52:38 +0000 (18:52 +0000)]
[InstCombine] add tests for broken shuffle transform (PR37648)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333779
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Simon Atanasyan [Fri, 1 Jun 2018 16:37:53 +0000 (16:37 +0000)]
[mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions
The `MipsAsmParser::loadImmediate` can load immediates of various sizes
into a register. Idea of this change is to use `loadImmediate` in the
`MipsAsmParser::expandMemInst` method to load offset into a register and
then call required load/store instruction.
The patch removes separate `expandLoadInst` and `expandStoreInst`
methods and does everything in the `expandMemInst` method to escape code
duplication.
Differential Revision: https://reviews.llvm.org/D47316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333774
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Simon Atanasyan [Fri, 1 Jun 2018 16:37:42 +0000 (16:37 +0000)]
[mips] Extend list of relocations supported by the `.reloc` directive
Supporting GOT and TLS related relocations by the `.reloc` directive is
useful for purpose of testing various tools like a linker, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333773
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Paul Semel [Fri, 1 Jun 2018 16:19:46 +0000 (16:19 +0000)]
[llvm-objcopy] Fix null symbol handling
This fixes the bug where strip-all option was
leading to a malformed outputted ELF file.
Differential Revision: https://reviews.llvm.org/D47414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333772
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Krzysztof Parzyszek [Fri, 1 Jun 2018 15:39:10 +0000 (15:39 +0000)]
[Hexagon] Avoid UB when shifting unsigned integer left by 32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333771
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Sanjay Patel [Fri, 1 Jun 2018 15:21:14 +0000 (15:21 +0000)]
[LangRef] fix typo; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333770
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Vlad Tsyrklevich [Fri, 1 Jun 2018 15:20:47 +0000 (15:20 +0000)]
[ThinLTOBitcodeWriter] Emit summaries for regular LTO modules
Summary:
Emit summaries for bitcode modules that are only destined for the
regular LTO portion of the build so they can participate in
summary-based dead stripping.
This change reduces the size of a nacl_helper build with cfi-icall
enabled by 7%, removing the majority of the overhead due to enabling
cfi-icall. The cfi-icall size increase was caused by compiling in lots
of unused code and cfi-icall generating jumptable references to unused
symbols that could no longer be removed by -Wl,-gc-sections. Increasing
the visibility of summary-based dead stripping prevented jumptable
entries being created for unused symbols from the regular LTO portion
of the build.
Reviewers: pcc
Reviewed By: pcc
Subscribers: dschuff, mehdi_amini, inglorion, eraman, llvm-commits, kcc
Differential Revision: https://reviews.llvm.org/D47594
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333768
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Karl-Johan Karlsson [Fri, 1 Jun 2018 15:08:14 +0000 (15:08 +0000)]
[ConstantFold] Add lit testcase for bitcast problem. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333767
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Nirav Dave [Fri, 1 Jun 2018 15:05:55 +0000 (15:05 +0000)]
[DAG] Avoid checking for consecutive stores in store merge. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333766
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Nirav Dave [Fri, 1 Jun 2018 15:05:30 +0000 (15:05 +0000)]
[DAG] Simplify Expression. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333765
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Nirav Dave [Fri, 1 Jun 2018 15:05:05 +0000 (15:05 +0000)]
[DAG] Remove untriggerable check. NFCI.
Candidate check precludes this check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333764
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Nirav Dave [Fri, 1 Jun 2018 15:04:40 +0000 (15:04 +0000)]
[DAG] Prune store merge legal store check to stop invalid size. NFCI.
Do not consider store sizes large than the maximum legal store size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333763
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Krzysztof Parzyszek [Fri, 1 Jun 2018 14:52:58 +0000 (14:52 +0000)]
[Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333760
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Clement Courbet [Fri, 1 Jun 2018 14:49:06 +0000 (14:49 +0000)]
[llvm-exegesis] Fix off-by-one in llvm-exegesis documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333759
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Sanjay Patel [Fri, 1 Jun 2018 14:39:05 +0000 (14:39 +0000)]
[InstCombine] add baseline test for bug with div+select transform (D47576)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333756
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Andrea Di Biagio [Fri, 1 Jun 2018 14:35:21 +0000 (14:35 +0000)]
[llvm-mca] Move the logic that computes the block throughput into Support.h. NFC
This will allow us to share the logic that computes the block throughput with
other views.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333755
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Hiroshi Inoue [Fri, 1 Jun 2018 14:23:15 +0000 (14:23 +0000)]
[NFC] Zero initialize local variables
This patch makes local variables zero initialized to avoid broken values in debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333754
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Clement Courbet [Fri, 1 Jun 2018 14:18:02 +0000 (14:18 +0000)]
[llvm-exegesis] Analysis: Display idealized sched class port pressure.
Summary: Screenshot in phabricator diff.
Reviewers: gchatelet
Subscribers: mgorny, tschuett, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D47329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333753
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Krzysztof Parzyszek [Fri, 1 Jun 2018 14:00:32 +0000 (14:00 +0000)]
[SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for target
Additionally, implement handling of ADD/SUBCARRY on Hexagon, utilizing
the UADDO/USUBO expansion.
Differential Revision: https://reviews.llvm.org/D47559
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333751
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Alexander Ivchenko [Fri, 1 Jun 2018 13:51:53 +0000 (13:51 +0000)]
[x86] NFC. Reautogenerate test/CodeGen/X86/vector-half-conversions.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333750
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Simon Pilgrim [Fri, 1 Jun 2018 13:37:01 +0000 (13:37 +0000)]
[Utils][X86] Help update_llc_test_checks.py to recognise retl/retq to reduce CHECK duplication (PR35003)
This patch replaces the --x86_extra_scrub command line argument to automatically support a second level of regex-scrubbing if it improves the matching of nearly-identical code patterns. The argument '--extra_scrub' is there now to force extra matching if required.
This is mostly useful to help us share 32-bit/64-bit x86 vector tests which only differs by retl/retq instructions, but any scrubber can now technically support this, meaning test checks don't have to be needlessly obfuscated.
I've updated some of the existing checks that had been manually run with --x86_extra_scrub, to demonstrate the extra "ret{{[l|q]}}" scrub now only happens when useful, and re-run the sse42-intrinsics file to show extra matches - most sse/avx intrinsics files should be able to now share 32/64 checks.
Tested with the opt/analysis scripts as well which share common code - AFAICT the other update scripts use their own versions.
Differential Revision: https://reviews.llvm.org/D47485
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333749
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Amaury Sechet [Fri, 1 Jun 2018 13:21:33 +0000 (13:21 +0000)]
Set ADDE/ADDC/SUBE/SUBC to expand by default
Summary:
They've been deprecated in favor of UADDO/ADDCARRY or USUBO/SUBCARRY for a while.
Target that uses these opcodes are changed in order to ensure their behavior doesn't change.
Reviewers: efriedma, craig.topper, dblaikie, bkramer
Subscribers: jholewinski, arsenm, jyknight, sdardis, nemanjai, nhaehnle, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, llvm-commits
Differential Revision: https://reviews.llvm.org/D47422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333748
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Amara Emerson [Fri, 1 Jun 2018 13:20:32 +0000 (13:20 +0000)]
[AArch64][GlobalISel] Zero-extend s1 values when returning.
Before we were relying on the any extend of the s1 to s32, but
for AAPCS we need to zero-extend it to at least s8.
Fixes PR36719
Differential Revision: https://reviews.llvm.org/D47425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333747
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Florian Hahn [Fri, 1 Jun 2018 12:58:43 +0000 (12:58 +0000)]
Revert r333740: IPSCCP] Use PredicateInfo to propagate facts from cmp.
This is breaking the clang-with-thin-lto-ubuntu bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333745
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Sander de Smalen [Fri, 1 Jun 2018 12:54:46 +0000 (12:54 +0000)]
[AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction.
Unpredicated copy of floating-point immediate value into SVE vector,
along with MOV-aliases.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47482
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333744
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Simon Dardis [Fri, 1 Jun 2018 10:57:13 +0000 (10:57 +0000)]
[mips] Guard more aliases correctly.
Also, duplicate an alias for microMIPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333741
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Florian Hahn [Fri, 1 Jun 2018 10:48:54 +0000 (10:48 +0000)]
Recommit r333268: [IPSCCP] Use PredicateInfo to propagate facts from cmp instructions.
This patch updates IPSCCP to use PredicateInfo to propagate
facts to true branches predicated by EQ and to false branches
predicated by NE.
As a follow up, we should be able to extend it to also propagate additional
facts about nonnull.
Reviewers: davide, mssimpso, dberlin, efriedma
Reviewed By: davide, dberlin
Differential Revision: https://reviews.llvm.org/D45330
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333740
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Simon Dardis [Fri, 1 Jun 2018 10:46:00 +0000 (10:46 +0000)]
[mips] Guard 'nop' properly and add mips16's nop instruction
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D47583
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333739
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Pavel Labath [Fri, 1 Jun 2018 10:33:11 +0000 (10:33 +0000)]
DWARFAcceleratorTable: Add an iterator-based api for accessing names in the index
Summary:
Back when we were introducing the DWARF v5 name index, there was a
short discussion whether we shouldn't have a nicer api for iterating
over the index. At that time, I did not find it necessary since the
iteration over names was done only from within the index itself (and I
figured the internal implementation can deal with a slightly rough
interface).
However, now I ran into a use for this kind of API in LLDB (for finding
all names matching a regular expression), so it looked like a nice
opportunity to introduce one. To make the API more useful, I've made the
NameTableEntry class a bit smarter: it now stores the string section
reference (so it can return its name) and its position in the name index
(mainly useful for dumping/logging).
I also convert the internal users to use the new API, which also gives
test coverage for the added code.
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333738
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Simon Dardis [Fri, 1 Jun 2018 10:07:10 +0000 (10:07 +0000)]
[mips] Select the correct instruction for computing frameindexes
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D47582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333736
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Gabor Buella [Fri, 1 Jun 2018 07:47:46 +0000 (07:47 +0000)]
NFC Avoid a warning in WasmEHPrepare.cpp
```
../lib/CodeGen/WasmEHPrepare.cpp:166:30: warning: extra ‘;’ [-Wpedantic]
false, false);
^
```
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333732
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Sander de Smalen [Fri, 1 Jun 2018 07:25:46 +0000 (07:25 +0000)]
[AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction.
Unpredicated copy of repeating immediate pattern to SVE vector, along
with MOV-aliases.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D47328
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333731
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Matt Arsenault [Fri, 1 Jun 2018 07:06:03 +0000 (07:06 +0000)]
AMDGPU: Switch some half using-tests to use amdhsa
The default clover ABI weirdly promotes half to float,
which should probably be fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333730
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Craig Topper [Fri, 1 Jun 2018 06:11:29 +0000 (06:11 +0000)]
[X86][Disassembler] Make it an error to set EVEX.R' to 0 when modrm.reg encodes a GPR.
This is different than the behavior of EVEX.X extending modrm.rm to 5 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333728
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Craig Topper [Fri, 1 Jun 2018 05:36:08 +0000 (05:36 +0000)]
[X86][Disassembler] Ignore EVEX.X extension of modrm.rm to 5-bits when modrm.rm encodes a k-register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333727
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Daniel Cederman [Fri, 1 Jun 2018 05:31:58 +0000 (05:31 +0000)]
Implemented sane default for llvm-objdump's relocation Value format
Summary:
"Unknown" for platforms that were not manually added into the switch
did not make sense at all. Now it prints Target + addend for all
elf-machines that were not explicitly mentioned.
Addresses PR21059 and PR25124.
Original author: fedor.sergeev
Reviewers: jyknight, espindola, fedor.sergeev
Reviewed By: jyknight
Subscribers: eraman, dcederman, jfb, dschuff, aheejin, llvm-commits
Differential Revision: https://reviews.llvm.org/D36464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333726
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Craig Topper [Fri, 1 Jun 2018 05:12:44 +0000 (05:12 +0000)]
[X86][Disassembler] Clamp index to 4-bits when decoding GPR registers.
A 5-bit value can occur when EVEX.X is 0 due to it being used to extend modrm.rm to encode XMM16-31. But if modrm.rm instead encodes a GPR, the Intel documentation says EVEX.X should be ignored so just mask it to 4 bits once we know its a GPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333725
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Craig Topper [Fri, 1 Jun 2018 05:12:43 +0000 (05:12 +0000)]
[X86] Add a test case showing a bad disassembling of an EVEX instruction with EVEX.X=0 and a GPR encoded in modrm.rm.
EVEX.X is used to extended modrm.rm when the instruction encodes a XMM/YMM/ZMM register. But we aren't properly ignoring it when it encodes a GPR and we end up printing whatever registers exist in X86 register enum after the GPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333724
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Craig Topper [Fri, 1 Jun 2018 04:29:34 +0000 (04:29 +0000)]
[X86][Disassembler] Make sure EVEX.X is not used to extend base registers of memory operations.
This was an accidental side effect of EVEX.X being used to encode XMM16-XMM31 using modrm.rm with modrm.mod==0x3.
I think there are still more bugs related to this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333722
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Craig Topper [Fri, 1 Jun 2018 04:29:30 +0000 (04:29 +0000)]
[X86][Disassembler] Use a local variable instead of using a field in the instruction object. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333721
91177308-0d34-0410-b5e6-
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Tom Stellard [Fri, 1 Jun 2018 02:19:46 +0000 (02:19 +0000)]
AMDGPU/R600: Move intrinsics to IntrinsicsAMDGPU.td
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D47487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333720
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Craig Topper [Fri, 1 Jun 2018 01:23:52 +0000 (01:23 +0000)]
[X86] Make sure the check for VEX.vvvv being all ones on instructions that don't use it doesn't ignore a bit in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333717
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 1 Jun 2018 00:10:36 +0000 (00:10 +0000)]
[X86][Disassembler] Suppress reading of EVEX.V' and EVEX.R' in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333714
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Craig Topper [Fri, 1 Jun 2018 00:10:32 +0000 (00:10 +0000)]
[X86] Add test cases showing the disassembler producing an xmm16-xmm31 register in 32-bit mode.
We aren't properly suppressing the reading of VEX.R' and VEX.V' in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333713
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Heejin Ahn [Fri, 1 Jun 2018 00:03:21 +0000 (00:03 +0000)]
Change ambiguous uses of term 'funclet' to 'EH scopes'. NFC.
Summary:
`getEHScopeMembership()` function is used not only for funclet-based
EHs; they apply to all EH schemes that use the scoped IR
(catchpad/cleanuppad/...). D47005 (rL333045) changed some of the uses of
the term 'funclet' to 'EH scopes' in case they apply to all scoped EH,
and this fixes more of them. For `FuncletLayout` pass, I left it as is
because the pass is only used for funclet-based EH.
Reviewers: majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47611
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333711
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Dan Gohman [Thu, 31 May 2018 22:35:25 +0000 (22:35 +0000)]
[WebAssembly] Update to the new names for the memory intrinsics.
The WebAssembly committee has decided on the names `memory.size` and
`memory.grow` for the memory intrinsics, so update the LLVM intrinsics to
follow those names, keeping both sets of old names in place for
compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333708
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Sanjay Patel [Thu, 31 May 2018 22:31:02 +0000 (22:31 +0000)]
[LoopVectorize, x86] add tests to show missing SVML transforms; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333707
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Dan Gohman [Thu, 31 May 2018 22:27:24 +0000 (22:27 +0000)]
[WebAssembly] Fix the signatures for the __mulo* libcalls.
The __mulo* libcalls have an extra i32* to return the overflow value.
Fixes PR37401.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333706
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Heejin Ahn [Thu, 31 May 2018 22:25:54 +0000 (22:25 +0000)]
[WebAssembly] Support instruction selection for catching exceptions
Summary:
This lowers exception catching-related instructions:
1. Lowers `wasm.catch` intrinsic to `catch` instruction
2. Removes `catchpad` and `cleanuppad` instructions; they are not
necessary after isel phase. (`MachineBasicBlock::isEHFuncletEntry()` or
`MachineBasicBlock::isEHPad()` can be used instead.)
3. Lowers `catchret` and `cleanupret` instructions to pseudo `catchret`
and `cleanupret` instructions in isel, which will be replaced with other
instructions in `WebAssemblyExceptionPrepare` pass.
4. Adds 'WebAssemblyExceptionPrepare` pass, which is for running various
transformation for EH. Currently this pass only replaces `catchret` and
`cleanupret` instructions into appropriate wasm instructions to make
this patch successfully run until the end.
Currently this does not handle lowering of intrinsics related to LSDA
info generation (`wasm.landingpad.index` and `wasm.lsda`), because they
cannot be tested without implementing `EHStreamer`'s wasm-specific
handlers. They are marked as TODO, which is needed to make isel pass.
Also this does not generate `try` and `end_try` markers yet, which will
be handled in later patches.
This patch is based on the first wasm EH proposal.
(https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md)
Reviewers: dschuff, majnemer
Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D44090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333705
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Craig Topper [Thu, 31 May 2018 22:16:55 +0000 (22:16 +0000)]
[LoopIdiomRecognize] Only convert loops to ctlz if we can prove that the input is non-negative.
Summary:
Loop idiom recognize tries to convert loops like
```
int foo(int x) {
int cnt = 0;
while (x) {
x >>= 1;
++cnt;
}
return cnt;
}
```
into calls to ctlz, but if x is initially negative this loop should be infinite.
It happens that the cases that motivated this change have an absolute value of x before the loop. So this patch restricts the transform to cases where we know x is positive. Note: We are relying on the absolute value of INT_MIN to be undefined so we can assume that the result is always positive.
Fixes PR37479
Reviewers: spatel, hfinkel, efriedma, javed.absar
Reviewed By: efriedma
Subscribers: dmgreen, llvm-commits
Differential Revision: https://reviews.llvm.org/D47348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333702
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Heejin Ahn [Thu, 31 May 2018 22:02:34 +0000 (22:02 +0000)]
[WebAssembly] Add Wasm exception handling prepare pass
Summary:
This adds a pass that transforms a program to be prepared for Wasm
exception handling. This is using Windows EH instructions and based on
the previous Wasm EH proposal.
(https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md)
Reviewers: dschuff, majnemer
Subscribers: jfb, mgorny, sbc100, jgravelle-google, JDevlieghere, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D43746
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333696
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Sanjay Patel [Thu, 31 May 2018 21:30:36 +0000 (21:30 +0000)]
[LoopVectorize, x86] regenerate checks; NFC
I removed the 'fast' flag from the calls because that's not required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333695
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Alexander Shaposhnikov [Thu, 31 May 2018 20:42:13 +0000 (20:42 +0000)]
[llvm-strip] Add -o option to llvm-strip
This diff implements the option -o
for specifying a file to write the output to.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D47505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333693
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Andrea Di Biagio [Thu, 31 May 2018 20:27:46 +0000 (20:27 +0000)]
[llvm-mca] Fixed a problem caused by an invalid use of a processor resource mask in the Scheduler.
The lambda functions used by method ResourceManager::mustIssueImmediately() was
incorrectly truncating masks of buffered processor resources to 32-bit quantities.
The invalid mask values were then used to access a map of processor
resource descriptors.
Fixes PR37643.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333692
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Stanislav Mekhanoshin [Thu, 31 May 2018 20:13:51 +0000 (20:13 +0000)]
[AMDGPU] Construct memory clauses before RA
Memory clauses are formed into bundles in presence of xnack.
Their source operands are marked as early-clobber.
This allows to allocate distinct source and destination registers
within a clause and prevent breaking the clause with s_nop in the
hazard recognizer.
Clauses are undone before post-RA scheduler to allow some rescheduling,
which will not break the clause since artificial edges are created in
the dag to keep memory operations together. Yet this allows a better
ILP in some cases.
Differential Revision: https://reviews.llvm.org/D47511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333691
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Sanjay Patel [Thu, 31 May 2018 19:55:27 +0000 (19:55 +0000)]
[InstCombine] narrow select to match condition operands' size
This is the planned enhancement to D47163 / rL333611.
We want to match cmp/select sizes because that will be recognized
as min/max more easily and lead to better codegen (especially for
vector types).
As mentioned in D47163, this improves some of the tests that would
also be folded by D46380, so we may want to adjust that patch to
match the new patterns where the extend op occurs after the select.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333689
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Stanislav Mekhanoshin [Thu, 31 May 2018 19:39:54 +0000 (19:39 +0000)]
[AMDGPU] Fixed incorrect -mcpu=gfx800 in xnor.ll test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333687
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Aditya Nandakumar [Thu, 31 May 2018 19:30:01 +0000 (19:30 +0000)]
[GISel]: Pattern matchers for GFSUB, GFNEG
https://reviews.llvm.org/D47547
Add matching templates for G_FSUB, and G_FNEG.
Reviewed by: aemerson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333685
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Lang Hames [Thu, 31 May 2018 19:29:03 +0000 (19:29 +0000)]
[ORC] Add a getRequestedSymbols method to MaterializationResponsibility.
This method returns the set of symbols in the target VSO that have queries
waiting on them. This can be used to make decisions about which symbols to
delegate to another MaterializationUnit (typically this will involve
delegating all symbols that have *not* been requested to another
MaterializationUnit so that materialization of those symbols can be
deferred until they are requested).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333684
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Lang Hames [Thu, 31 May 2018 19:29:01 +0000 (19:29 +0000)]
[ORC] Rename IRMaterializationUnit's Discardable member to SymbolToDefinition,
and make it protected rather than private.
The new name reflects the actual information in the map, and this information
can be useful to derived classes (for example, to quickly look up the IR
definition of a requested symbol).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333683
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Sanjay Patel [Thu, 31 May 2018 19:25:02 +0000 (19:25 +0000)]
[InstCombine] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333682
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Peter Collingbourne [Thu, 31 May 2018 18:25:59 +0000 (18:25 +0000)]
IRGen: Write .dwo files when -split-dwarf-file is used together with -fthinlto-index.
Differential Revision: https://reviews.llvm.org/D47597
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333677
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Sriraman Tallam [Thu, 31 May 2018 18:12:33 +0000 (18:12 +0000)]
Relax GOTPCREL relocations for tail jmp instructions.
Differential Revision: https://reviews.llvm.org/D47563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333676
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Craig Topper [Thu, 31 May 2018 18:08:11 +0000 (18:08 +0000)]
[JumpThreading] Fix some strange formatting of code inside LLVM_DEBUG. NFC
I don't know if clang-format got confused here or what.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333675
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Artem Dergachev [Thu, 31 May 2018 17:32:29 +0000 (17:32 +0000)]
[ADT] Annotate immutable list/set/map update methods with LLVM_NODISCARD.
Because immutable data structures are, well, immutable, methods like "append",
"add", "set" create a copy of the list (set, map) instead of mutating the
existing map. If the updated object is discarded, it clearly indicates a bug.
Such bugs are introduced frequently, hence the warn_unused_result annotation.
Differential Revision: https://reviews.llvm.org/D47496
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333672
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Jonas Devlieghere [Thu, 31 May 2018 17:01:42 +0000 (17:01 +0000)]
[ADT] Make escaping fn conform to coding guidelines
As noted by Adrian on llvm-commits, PrintHTMLEscaped and PrintEscaped in
StringExtras did not conform to the LLVM coding guidelines. This commit
rectifies that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333669
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David Bolvansky [Thu, 31 May 2018 16:39:27 +0000 (16:39 +0000)]
[SimplifyLibcalls] [NFC] Cleanup, improvements
Summary:
* Use "find('%')" instead of loop to find '%' char (we already uses find('%') in optimizePrintFString..)
* Convert getParent() chains to getModule()/getFunction()
Reviewers: lebedev.ri, spatel
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47397
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333668
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Francis Visoiu Mistrih [Thu, 31 May 2018 16:33:26 +0000 (16:33 +0000)]
[MC] Fallback on DWARF when generating compact unwind on AArch64
Instead of asserting when using the def_cfa directive with a register
different from fp, fallback on DWARF.
Easily triggered with:
.cfi_def_cfa x1, 32;
rdar://
40249694
Differential Revision: https://reviews.llvm.org/D47593
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333667
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Roman Tereshin [Thu, 31 May 2018 16:16:49 +0000 (16:16 +0000)]
[GlobalISel][Mips] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) call for Mips
Reviewers: aemerson, qcolombet
Reviewed By: qcolombet
Differential Revision: https://reviews.llvm.org/D46339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333665
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Roman Tereshin [Thu, 31 May 2018 16:16:48 +0000 (16:16 +0000)]
[GlobalISel][AMDGPU] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) call for AMDGPU
Reviewers: aemerson, qcolombet
Reviewed By: qcolombet
Differential Revision: https://reviews.llvm.org/D46339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333664
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Roman Tereshin [Thu, 31 May 2018 16:16:48 +0000 (16:16 +0000)]
[GlobalISel][ARM] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) call and fixing bugs exposed
Reviewers: aemerson, qcolombet
Reviewed By: qcolombet
Differential Revision: https://reviews.llvm.org/D46339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333663
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Roman Tereshin [Thu, 31 May 2018 16:16:47 +0000 (16:16 +0000)]
[GlobalISel][X86] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) call and fixing bugs exposed
Reviewers: aemerson, qcolombet
Reviewed By: qcolombet
Differential Revision: https://reviews.llvm.org/D46339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333662
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Simon Pilgrim [Thu, 31 May 2018 15:47:17 +0000 (15:47 +0000)]
[X86][SSE] Recognise splat rotations and expand back to shift ops.
Noticed while fixing PR37426, for splat rotations (rotation by an uniform value) its better to just expand back to shift ops than performing as a general non-uniform rotation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333661
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Simon Pilgrim [Thu, 31 May 2018 15:15:49 +0000 (15:15 +0000)]
[X86][AVX] Add peekThroughEXTRACT_SUBVECTORs helper (NFCI)
We often need this for AVX1 128-bit integer ops as they may have been split from a 256-bit source.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333660
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Aditya Kumar [Thu, 31 May 2018 15:15:33 +0000 (15:15 +0000)]
make GlobalValueSummary::getOriginalName() a const function
Differential Revision: https://reviews.llvm.org/D46962
Reviewers: craig.topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333659
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David Green [Thu, 31 May 2018 14:55:29 +0000 (14:55 +0000)]
[DA] Fix direction vectors for weakZeroSrcSIV
Both weakZeroSrcSIV and weakZeroDstSIV are currently giving the same
direction vectors. Fix weakZeroSrcSIVtest by flipping the directions
it gives.
Differential Revision: https://reviews.llvm.org/D46678
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333658
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Clement Courbet [Thu, 31 May 2018 14:22:01 +0000 (14:22 +0000)]
[X86] Introduce WriteFLDC for x87 constant loads.
Summary:
{FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI} were using WriteMicrocoded.
- I've measured the values for Broadwell, Haswell, SandyBridge, Skylake.
- For ZnVer1 and Atom, values were transferred form InstRWs.
- For SLM and BtVer2, I've guessed some values :(
Reviewers: RKSimon, craig.topper, andreadb
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D47585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333656
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Nico Weber [Thu, 31 May 2018 13:41:04 +0000 (13:41 +0000)]
Use -Wextra spelling instead of -W
No difference in behavior, but a bit easier to search for.
https://reviews.llvm.org/D47490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333651
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Andrea Di Biagio [Thu, 31 May 2018 13:30:42 +0000 (13:30 +0000)]
[MCSchedule] Add the ability to compute the latency and throughput information for MCInst.
This patch extends the MCSchedModel API with new methods that can be used to
obtain the latency and reciprocal througput information for an MCInst.
Scheduling models have recently gained the ability to resolve variant scheduling
classes associated with MCInst objects. Before, models were only able to resolve
a variant scheduling class from a MachineInstr object.
This patch is mainly required by D47374 to avoid regressing a pair of x86
specific -print-schedule tests for btver2. Patch D47374 introduces a new variant
class to teach the btver scheduling model (x86 target) how to correctly compute
the latency profile for some zero-idioms using the new scheduling predicates.
The new methods added by this patch would be mainly used by llc when flag
-print-schedule is specified. In particular, tests that contain inline assembly
require that code is parsed at code emission stage into a sequence of MCInst.
That forces the print-schedule functionality to query the latency/rthroughput
information for MCInst instructions too. If we don't expose this new API, then
we lose "-print-schedule" test coverage as soon as variant scheduling classes
are added to the x86 models.
The tablegen SubtargetEmitter changes teaches how to query latency profile
information using a object that derives from TargetSubtargetInfo. Note that this
should really have been part of r333286. To avoid code duplication, the logic
that "resolves" variant scheduling classes for MCInst, has been moved to a
common place in MC. That logic is used by the "resolveVariantSchedClass" methods
redefined in override by the tablegen'd GenSubtargetInfo classes.
Differential Revision: https://reviews.llvm.org/D47536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333650
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Benjamin Kramer [Thu, 31 May 2018 13:29:58 +0000 (13:29 +0000)]
Extend the GlobalObject metadata interface
- Make eraseMetadata return whether it changed something
- Wire getMetadata for a single MDNode efficiently into the attachment
map
- Add hasMetadata, which is less weird than checking getMetadata ==
nullptr on a multimap.
Use it to simplify code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333649
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Simon Dardis [Thu, 31 May 2018 12:47:01 +0000 (12:47 +0000)]
[mips] Guard all short instructions correctly.
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D47533
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333645
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Alexandros Lamprineas [Thu, 31 May 2018 12:19:18 +0000 (12:19 +0000)]
[InstCombine, ARM] Convert vld1 to llvm load
Convert a vector load intrinsic into an llvm load instruction.
This is beneficial when the underlying object being addressed
comes from a constant, since we get constant-folding for free.
Differential Revision: https://reviews.llvm.org/D46273
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333643
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Clement Courbet [Thu, 31 May 2018 11:41:27 +0000 (11:41 +0000)]
[X86] Extract latency of fldz/fld1 in separate classes.
Summary:
- I've measured the values for Broadwell, Haswell, SandyBridge, Skylake.
- For ZnVer1 and Atom, values were transferred form `InstRW`s.
- For SLM and BtVer2, values are from Agner.
This is split off from https://reviews.llvm.org/D47377
Reviewers: RKSimon, andreadb
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D47523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333642
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Simon Pilgrim [Thu, 31 May 2018 11:25:16 +0000 (11:25 +0000)]
[X86][SSE] Add support for detecting SUB(SPLAT_BV, SPLAT) cases for shift-rotate patterns.
This improves splat rotations (rotation by an uniform value), to avoid having to use the generic non-uniform shift code (extension to PR37426).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333641
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Pavel Labath [Thu, 31 May 2018 08:47:00 +0000 (08:47 +0000)]
DWARFAcceleratorTable: fix equal_range iterators
Summary:
Both (Apple and DWARF5) implementations of the iterators had bugs which
resulted in crashes if one attempted to iterate through the accelerator
tables all the way.
For the Apple tables, the issue was that we did not clear the DataOffset
field when we reached the end, which made our iterator compare unequal
to the "end" iterator. For the Dwarf5 tables, the problem was that we
incremented the CurrentIndex pointer and then used the incremented
(possibly invalid) pointer to check whether we have reached the end of
the index list.
The reason these bugs went undetected is because their only user
(dwarfdump) only ever searched for the first match. Besides allowing us
to test this fix, changing llvm-dwarfdump --find to display all matches
seems like a good improvement (it makes the behavior consistent with the
--name option), so I change llvm-dwarfdump to do that.
The existing tests would be sufficient to test this fix with the new
llvm-dwarfdump behavior, but I add a special test that demonstrates that
the tool indeed displays multiple results. The find.test test needed to
be tweaked a bit as the tool now does not print the ".debug_info
contents" header (also consistent with how --name works).
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D47543
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333635
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Luke Geeson [Thu, 31 May 2018 08:27:53 +0000 (08:27 +0000)]
[AArch64] Reverted rL333427 fixing Clang UnitTest Failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333634
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Max Kazantsev [Thu, 31 May 2018 08:08:34 +0000 (08:08 +0000)]
[NFC] Factor out a method for further extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333633
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