OSDN Git Service
Craig Topper [Mon, 5 Sep 2016 20:34:50 +0000 (20:34 +0000)]
[AVX-512] Integrate mask register copying more completely into X86InstrInfo::copyPhysReg and simplify. No functional change intended.
The code is now written in terms of source and dest classes with feature checks inside each type of copy instead of having separate functions for each feature set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280673
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Simon Pilgrim [Mon, 5 Sep 2016 18:11:17 +0000 (18:11 +0000)]
[X86][SSE] Add test cases for PR29078
'Failure to recognise i64 sitofp/uitofp conversions that can be performed as i32'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280671
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Simon Pilgrim [Mon, 5 Sep 2016 18:04:38 +0000 (18:04 +0000)]
[X86][SSE] Add test cases for PR29079
'Failure to recognise uitofp conversions that can be performed as sitofp'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280670
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whitequark [Mon, 5 Sep 2016 17:42:46 +0000 (17:42 +0000)]
CODE_OWNERS: bring my entry up to date
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280667
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Simon Pilgrim [Mon, 5 Sep 2016 14:15:38 +0000 (14:15 +0000)]
[X86][SSE] Regenerate odd shuffle tests with common prefixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280661
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Oliver Stannard [Mon, 5 Sep 2016 13:49:26 +0000 (13:49 +0000)]
[SimplifyCFG] Add test for sinking inline asm in if/else
This test code previously caused a failure in the module verifier,
because SimplifyCFG created this invalid instruction, which tries to
take the address of inline asm:
%.sink = select i1 %1, i64 ()* asm "mov $0, #1", "=r", i64 ()* asm %"mov $0, #2", "=r"
This has been fixed recently, presumably by James Molloy's patches that
re-wrote and changed parts of SimplifyCFG, so this patch just adds a
regression test for it.
Differential Revision: https://reviews.llvm.org/D24231
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280660
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Benjamin Kramer [Mon, 5 Sep 2016 12:06:47 +0000 (12:06 +0000)]
[WebAssembly] Unbreak the build.
Not sure why ADL isn't working here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280656
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Valery Pykhtin [Mon, 5 Sep 2016 11:22:51 +0000 (11:22 +0000)]
[AMDGPU] Refactor FLAT TD instructions
Differential revision: https://reviews.llvm.org/D24072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280655
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James Molloy [Mon, 5 Sep 2016 08:29:15 +0000 (08:29 +0000)]
[Thumb1] Add relocations for fixups fixup_arm_thumb_{br,bcc}
These need to be mapped through to R_ARM_THM_JUMP{11,8} respectively.
Fixes PR30279.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280651
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Igor Breger [Mon, 5 Sep 2016 08:26:51 +0000 (08:26 +0000)]
[AVX512] Fix v8i1 /v16i1 zext + bitcast lowering pattern. Explicitly zero upper bits.
Differential Revision: http://reviews.llvm.org/D23983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280650
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Craig Topper [Mon, 5 Sep 2016 07:14:21 +0000 (07:14 +0000)]
[X86] Make some static arrays of opcodes const and shrink to uint16_t. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280649
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Craig Topper [Mon, 5 Sep 2016 06:43:06 +0000 (06:43 +0000)]
[AVX-512] Simplify X86InstrInfo::copyPhysReg for 128/256-bit vectors with AVX512, but not VLX. We should use the VEX opcodes and trust the register allocator to not use the extended XMM/YMM register space.
Previously we were extending to copying the whole ZMM register. The register allocator shouldn't use XMM16-31 or YMM16-31 in this configuration as the instructions to spill them aren't available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280648
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Craig Topper [Mon, 5 Sep 2016 06:43:00 +0000 (06:43 +0000)]
[Target] Remove the AvailableRegClasses vector from TargetLoweringBase. It was a private member with no code reading from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280647
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Gor Nishanov [Mon, 5 Sep 2016 04:44:30 +0000 (04:44 +0000)]
[Coroutines] Part11: Add final suspend handling.
Summary:
A frontend may designate a particular suspend to be final, by setting the second argument of the coro.suspend intrinsic to true. Such a suspend point has two properties:
* it is possible to check whether a suspended coroutine is at the final suspend point via coro.done intrinsic;
* a resumption of a coroutine stopped at the final suspend point leads to undefined behavior. The only possible action for a coroutine at a final suspend point is destroying it via coro.destroy intrinsic.
This patch adds final suspend handling logic to CoroEarly and CoroSplit passes.
Now, the final suspend point example from docs\Coroutines.rst compiles and produces expected result (see test/Transform/Coroutines/ex5.ll).
Reviewers: majnemer
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D24068
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280646
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Craig Topper [Mon, 5 Sep 2016 02:20:53 +0000 (02:20 +0000)]
[X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280645
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Craig Topper [Mon, 5 Sep 2016 02:20:49 +0000 (02:20 +0000)]
[X86] Remove FsVMOVAPSrm/FsVMOVAPDrm/FsMOVAPSrm/FsMOVAPDrm. Due to their placement in the td file they had lower precedence than (V)MOVSS/SD and could almost never be selected.
The only way to select them was in AVX512 mode because EVEX VMOVSS/SD was below them and the patterns weren't qualified properly for AVX only. So if you happened to have an aligned FR32/FR64 load in AVX512 you could get a VEX encoded VMOVAPS/VMOVAPD.
I tried to search back through history and it seems like these instructions were probably unselectable for at least 5 years, at least to the time the VEX versions were added. But I can't prove they ever were.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280644
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Peter Zotov [Mon, 5 Sep 2016 01:42:22 +0000 (01:42 +0000)]
[CMake] [OCaml] Allow building OCaml bindings out of tree.
That is, add build system support for building the OCaml bindings
against preinstalled LLVM libraries. This is important for package
managers such as OPAM, because OCaml libraries need to be built
against a specific OCaml compiler installation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280642
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NAKAMURA Takumi [Mon, 5 Sep 2016 00:00:40 +0000 (00:00 +0000)]
lit/util.py: Another fix for py3.
'str' object has no attribute 'decode'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280641
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Sanjay Patel [Sun, 4 Sep 2016 20:58:27 +0000 (20:58 +0000)]
[InstCombine] allow icmp (and X, C2), C1 folds for splat constant vectors
The code to calculate 'UsesRemoved' could be simplified.
As-is, that code is a victim of PR30273:
https://llvm.org/bugs/show_bug.cgi?id=30273
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280637
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Craig Topper [Sun, 4 Sep 2016 19:33:47 +0000 (19:33 +0000)]
[AVX-512] Add EVEX encoded scalar FMA intrinsic instructions to isNonFoldablePartialRegisterLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280636
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Simon Pilgrim [Sun, 4 Sep 2016 18:14:45 +0000 (18:14 +0000)]
[X86] Regenerate x64 mmx/f64 return value tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280634
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Craig Topper [Sun, 4 Sep 2016 18:13:33 +0000 (18:13 +0000)]
[AVX-512] Remove 128-bit and 256-bit masked floating point add/sub/mul/div intrinsics and upgrade to native IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280633
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Lang Hames [Sun, 4 Sep 2016 17:53:30 +0000 (17:53 +0000)]
[ORC] Clone module flags metadata into the globals module in the
CompileOnDemandLayer.
Also contains a tweak to the orc-lazy jit in LLI to enable the test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280632
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Simon Pilgrim [Sun, 4 Sep 2016 17:50:03 +0000 (17:50 +0000)]
[X86] Regenerate trunc-store legalization test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280631
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Simon Pilgrim [Sun, 4 Sep 2016 17:16:01 +0000 (17:16 +0000)]
[X86][SSE] Regenerate fcmp/uitofp combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280629
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Lang Hames [Sun, 4 Sep 2016 16:31:41 +0000 (16:31 +0000)]
[ORC] Fix an unfinished comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280628
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Sanjay Patel [Sun, 4 Sep 2016 14:32:15 +0000 (14:32 +0000)]
[InstCombine] recode icmp fold in a vector-friendly way; NFC
The transform in question:
icmp (and (trunc W), C2), C1 -> icmp (and W, C2'), C1'
...is still not enabled for vectors, thus no functional change intended.
It's not clear to me if this is a good transform for vectors or even
scalars in general. Changing that behavior may be a follow-on patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280627
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Hal Finkel [Sun, 4 Sep 2016 14:18:29 +0000 (14:18 +0000)]
[PowerPC] During branch relaxation, recompute padding offsets before each iteration
We used to compute the padding contributions to the block sizes during branch
relaxation only at the start of the transformation. As we perform branch
relaxation, we change the sizes of the blocks, and so the amount of inter-block
padding might change. Accordingly, we need to recompute the (alignment-based)
padding in between every iteration on our way toward the fixed point.
Unfortunately, I don't have a test case (and none was provided in the bug
report), and while this obviously seems needed, algorithmically, I don't have
any way of generating a small and/or non-fragile regression test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280626
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Igor Breger [Sun, 4 Sep 2016 14:03:52 +0000 (14:03 +0000)]
revert r279960.
https://llvm.org/bugs/show_bug.cgi?id=30249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280625
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Simon Pilgrim [Sun, 4 Sep 2016 13:30:46 +0000 (13:30 +0000)]
EOL fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280624
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Simon Pilgrim [Sun, 4 Sep 2016 13:28:46 +0000 (13:28 +0000)]
Strip trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280623
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Chandler Carruth [Sun, 4 Sep 2016 08:42:31 +0000 (08:42 +0000)]
[PM] Revert r280447: Add a unittest for invalidating module analyses with an SCC pass.
This was mistakenly committed. The world isn't ready for this test, the
test code has horrible debugging code in it that should never have
landed in tree, it currently passes because of bugs elsewhere, and it
needs to be rewritten to not be susceptible to passing for the wrong
reasons.
I'll re-land this in a better form when the prerequisite patches land.
So sorry that I got this mixed into a series of commits that *were*
ready to land. I shouldn't have. =[ What's worse is that it stuck around
for so long and I discovered it while fixing the underlying bug that
caused it to pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280620
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Chandler Carruth [Sun, 4 Sep 2016 08:34:31 +0000 (08:34 +0000)]
[LCG] Clean up and make NDEBUG verify calls more rigorous with
make_scope_exit now that we have that utility.
This makes the code much more clear and readable by isolating the check.
It also makes it easy to go through and make sure all the interesting
update routines have a start and end verify so we don't slowly let the
graph drift into an invalid state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280619
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Chandler Carruth [Sun, 4 Sep 2016 08:34:24 +0000 (08:34 +0000)]
[LCG] A NFC refactoring to extract the logic for doing
a postorder-sequence based update after edge insertion into a generic
helper function.
This separates the SCC-specific logic into two fairly simple lambdas and
extracts the rest into a generic helper template function. I think this
is a net win on its own merits because it disentangles different pieces
of the algorithm. Now there is one place that does the two-step
partition to identify a set of newly connected components and at the
same time update the postorder sequence.
However, I'm also hoping to re-use this an upcoming patch to update
a cached post-order sequence of RefSCCs when doing the analogous update
to the RefSCC graph, and I don't want to have two copies.
The diff is quite messy but this really is just moving things around and
making types generic rather than specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280618
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Dorit Nuzman [Sun, 4 Sep 2016 07:49:39 +0000 (07:49 +0000)]
[InstCombine] Preserve llvm.mem.parallel_loop_access metadata when replacing
memcpy with ld/st.
When InstCombine replaces a memcpy with loads+stores it does not copy over the
llvm.mem.parallel_loop_access from the memcpy instruction. This patch fixes
that.
Differential Revision: https://reviews.llvm.org/D23499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280617
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Lang Hames [Sun, 4 Sep 2016 07:24:11 +0000 (07:24 +0000)]
[ExecutionEngine] Move ObjectCache::anchor from MCJIT to ExecutionEngine.
ObjectCache is an ExecutionEngine utility, so its anchor belongs there. The
practical impact of this change is that ORC users no longer need to link MCJIT
to use ObjectCaches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280616
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Dorit Nuzman [Sun, 4 Sep 2016 07:06:00 +0000 (07:06 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280615
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Hal Finkel [Sun, 4 Sep 2016 06:07:19 +0000 (06:07 +0000)]
[PowerPC] Zero-extend constants in FastISel
As it turns out, whether we zero-extend or sign-extend i8/i16 constants, which
are illegal types promoted to i32 on PowerPC, is a choice constrained by
assumptions within the infrastructure. Specifically, the logic in
FunctionLoweringInfo::ComputePHILiveOutRegInfo assumes that constant PHI
operands will be zero extended, and so, at least when materializing constants
that are PHI operands, we must do the same.
The rest of our fast-isel implementation does not appear to depend on the fact
that we were sign-extending i8/i16 constants, and all other targets also appear
to zero-extend small-bitwidth constants in fast-isel; we'll now do the same (we
had been doing this only for i1 constants, and sign-extending the others).
Fixes PR27721.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280614
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Craig Topper [Sun, 4 Sep 2016 02:09:53 +0000 (02:09 +0000)]
[AVX-512] Remove masked integer add/sub/mull intrinsics and upgrade to native IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280611
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Joseph Tremoulet [Sun, 4 Sep 2016 01:23:20 +0000 (01:23 +0000)]
Fix inliner funclet unwind memoization
Summary:
The inliner may need to determine where a given funclet unwinds to,
and this determination may depend on other funclets throughout the
funclet tree. The code that performs this walk in getUnwindDestToken
memoizes results to avoid redundant computations. In the case that
a funclet's unwind destination is derived from its ancestor, there's
code to walk back down the tree from the ancestor updating the memo
map of its descendants to record the unwind destination. This change
fixes that code to account for the case that some descendant has a
different unwind destination, which can happen if that unwind dest
is a descendant of the EHPad being queried and thus didn't determine
its unwind destination.
Also update test inline-funclets.ll, which is supposed to cover such
scenarios, to include a case that fails an assertion without this fix
but passes with it.
Fixes PR29151.
Reviewers: majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D24117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280610
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Craig Topper [Sat, 3 Sep 2016 23:55:13 +0000 (23:55 +0000)]
[X86] Combine some of the strings in autoupgrade code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280603
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Xinliang David Li [Sat, 3 Sep 2016 22:26:11 +0000 (22:26 +0000)]
Cleanup : Use metadata preserving API for branch creation
Use the wrapper API in IRBuilder that does meta data copy
to create new branch in LoopUnswitch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280602
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Xinliang David Li [Sat, 3 Sep 2016 21:26:36 +0000 (21:26 +0000)]
[Profile] preserve branch metadata lowering select in CGP
CGP currently drops select's MD_prof profile data when
generating conditional branch which can lead to bad
code layout. The patch fixes the issue.
Differential Revision: http://reviews.llvm.org/D24169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280600
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Mehdi Amini [Sat, 3 Sep 2016 21:12:33 +0000 (21:12 +0000)]
Fix ThinLTO crash with debug info
Because the recent change about ODR type uniquing in the context,
we can reach types defined in another module during IR linking.
This triggered some assertions in case we IR link without starting
from an empty module. To alleviate that, we can self-map metadata
defined in the destination module so that they won't be visited.
Differential Revision: https://reviews.llvm.org/D23841
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280599
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Simon Pilgrim [Sat, 3 Sep 2016 20:36:05 +0000 (20:36 +0000)]
Strip trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280598
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Matt Arsenault [Sat, 3 Sep 2016 17:25:44 +0000 (17:25 +0000)]
AMDGPU: Set sizes of spill pseudos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280595
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Matt Arsenault [Sat, 3 Sep 2016 17:25:39 +0000 (17:25 +0000)]
AMDGPU: Fix adding duplicate implicit exec uses
I'm not sure if this should be considered a bug in
copyImplicitOps or not, but implicit operands that are part
of the static instruction definition should not be copied.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280594
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Craig Topper [Sat, 3 Sep 2016 17:20:07 +0000 (17:20 +0000)]
[AVX-512] Add integer ADD/SUB instructions to load folding tables. Add an AVX512 stack folding test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280593
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Craig Topper [Sat, 3 Sep 2016 16:28:03 +0000 (16:28 +0000)]
[AVX-512] Mark EVEX encoded vpcmpeq as commutable just like its AVX and SSE equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280592
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Nicolai Haehnle [Sat, 3 Sep 2016 12:26:38 +0000 (12:26 +0000)]
AMDGPU: Reduce the duration of whole-quad-mode
Summary:
This contains two changes that reduce the time spent in WQM, with the
intention of reducing bandwidth required by VMEM loads:
1. Sampling instructions by themselves don't need to run in WQM, only their
coordinate inputs need it (unless of course there is a dependent sampling
instruction). The initial scanInstructions step is modified accordingly.
2. When switching back from WQM to Exact, switch back as soon as possible.
This affects the logic in processBlock.
This should always be a win or at best neutral.
There are also some cleanups (e.g. remove unused ExecExports) and some new
debugging output.
Reviewers: arsenm, tstellarAMD, mareko
Subscribers: arsenm, llvm-commits, kzhuravl
Differential Revision: http://reviews.llvm.org/D22092
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280590
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Nicolai Haehnle [Sat, 3 Sep 2016 12:26:32 +0000 (12:26 +0000)]
AMDGPU: Fix an interaction between WQM and polygon stippling
Summary:
This fixes a rare bug in polygon stippling with non-monolithic pixel shaders.
The underlying problem is as follows: the prolog part contains the polygon
stippling sequence, i.e. a kill. The main part then enables WQM based on the
_reduced_ exec mask, effectively undoing most of the polygon stippling.
Since we cannot know whether polygon stippling will be used, the main part
of a non-monolithic shader must always return to exact mode to fix this
problem.
Reviewers: arsenm, tstellarAMD, mareko
Subscribers: arsenm, llvm-commits, kzhuravl
Differential Revision: https://reviews.llvm.org/D23131
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280589
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Matt Arsenault [Sat, 3 Sep 2016 07:06:58 +0000 (07:06 +0000)]
AMDGPU: Do basic folding of class intrinsic
This allows more of the OCML builtin library to be
constant folded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280586
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Matt Arsenault [Sat, 3 Sep 2016 06:57:55 +0000 (06:57 +0000)]
AMDGPU: Fix spilling of m0
readlane/writelane do not support using m0 as the output/input.
Constrain the register class of spill vregs to try to avoid this,
but also handle spilling of the physreg when necessary by inserting
an additional copy to a normal SGPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280584
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Matt Arsenault [Sat, 3 Sep 2016 06:57:49 +0000 (06:57 +0000)]
Improve debug error message with register name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280583
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Craig Topper [Sat, 3 Sep 2016 04:37:50 +0000 (04:37 +0000)]
[AVX-512] Add EVEX encoded VPCMPEQ and VPCMPGT to the load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280581
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NAKAMURA Takumi [Sat, 3 Sep 2016 04:06:37 +0000 (04:06 +0000)]
Make lit/util.py py3-compatible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280579
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Nico Weber [Sat, 3 Sep 2016 03:18:49 +0000 (03:18 +0000)]
Revert r280549.
The test it added doesn't pass:
http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/15318/steps/ninja%20check%201/logs/FAIL%3A%20LLVM%3A%3Apdbdump-yaml-types.test
Command Output (stdout):
--
$ "D:/buildslave/clang-x64-ninja-win7/stage1/./bin\llvm-pdbdump.EXE" "pdb2yaml" "-tpi-stream" "D:\buildslave\clang-x64-ninja-win7\llvm\test\DebugInfo\PDB/Inputs/empty.pdb"
$ "D:/buildslave/clang-x64-ninja-win7/stage1/./bin\FileCheck.EXE" "-check-prefix=YAML" "D:\buildslave\clang-x64-ninja-win7\llvm\test\DebugInfo\PDB\pdbdump-yaml-types.test"
# command stderr:
D:\buildslave\clang-x64-ninja-win7\llvm\test\DebugInfo\PDB\pdbdump-yaml-types.test:36:7: error: expected string not found in input
YAML: Name: apartment
^
<stdin>:153:10: note: scanning from here
Value: 161
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280577
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Duncan P. N. Exon Smith [Sat, 3 Sep 2016 02:43:42 +0000 (02:43 +0000)]
ADT: Use std::list in SparseBitVector, NFC
The only intrusive thing about SparseBitVector's usage of ilist<> was
that new was usually called externally. There were no custom traits.
It seems like the reason to switch to ilist in r41855 was to avoid
pointer invalidation, but std::list<> has that feature too. Maybe
std::list<>::emplace makes this a little more obvious than it was then.
Switch over to std::list<> and simplify the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280573
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Hal Finkel [Sat, 3 Sep 2016 02:31:44 +0000 (02:31 +0000)]
[PowerPC] Support asm parsing for bc[l][a][+-] mnemonics
PowerPC assembly code in the wild, so it seems, has things like this:
bc+ 12, 28, .L9
This is a bit odd because the '+' here becomes part of the BO field, and the BO
field is otherwise the first operand. Nevertheless, the ISA specification does
clearly say that the +- hint syntax applies to all conditional-branch mnemonics
(that test either CTR or a condition register, although not the forms which
check both), both basic and extended, so this is supposed to be valid.
This introduces some asm-parser-only definitions which take only the upper
three bits from the specified BO value, and the lower two bits are implied by
the +- suffix (via some associated aliases).
Fixes PR23646.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280571
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Duncan P. N. Exon Smith [Sat, 3 Sep 2016 02:27:35 +0000 (02:27 +0000)]
ADT: Do not inherit from std::iterator in ilist_iterator
Inheriting from std::iterator uses more boiler-plate than manual
typedefs. Avoid that in both ilist_iterator and
MachineInstrBundleIterator.
This has the side effect of removing ilist_iterator from certain ADL
lookups in namespace std; calls to std::next need to be qualified by
"std::" that didn't have to before. The one case of this in-tree was
operating on a temporary, so I used the more compact operator++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280570
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Duncan P. N. Exon Smith [Sat, 3 Sep 2016 02:07:45 +0000 (02:07 +0000)]
ADT: Split out iplist_impl from iplist, NFC
Split out iplist_impl from iplist, and change SymbolTableList to inherit
directly from iplist_impl. This makes it more straightforward to add
new template paramaters to iplist [*]:
- iplist_impl takes a "base" list that provides the intrusive
functionality (usually simple_ilist<T>) and a traits class.
- iplist no longer takes a "Traits" template parameter. It only takes
the value_type, T, and instantiates iplist_impl with simple_ilist<T>
and ilist_traits<T>.
- SymbolTableList now inherits from iplist_impl, instead of iplist.
Note for out-of-tree code: if you have an iplist whose second template
parameter was *not* the default (i.e., not ilist_traits<YourT>), you
have three options:
- Stop using a custom traits class, and instead specialize
ilist_traits<YourT>. This is the usual thing to do.
- Specialize iplist<YourT> to pass your custom traits class into
iplist_impl.
- Create your own trivial list type that passes your custom traits class
into iplist_impl (see SymbolTableList<> for an example).
[*]: The eventual goal is to start tracking a sentinel bit on the
MachineInstr list even when LLVM_ENABLE_ABI_BREAKING_CHECKS is off,
which will enable MachineBasicBlock::reverse_iterator to have normal
list invalidation semantics that matching the new
iplist<>::reverse_iterator from r280032.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280569
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Wei Mi [Sat, 3 Sep 2016 01:43:28 +0000 (01:43 +0000)]
Fix buildbot error.
Add -mtriple=x86_64-unknown-linux-gnu for the test and move it to CodeGen/X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280568
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Duncan P. N. Exon Smith [Sat, 3 Sep 2016 01:42:40 +0000 (01:42 +0000)]
ADT: Rename NodeTy to T in iplist/ilist template parameters
And use other typedefs so that the next rename has a smaller diff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280567
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Duncan P. N. Exon Smith [Sat, 3 Sep 2016 01:22:56 +0000 (01:22 +0000)]
ADT: Remove external uses of ilist_iterator, NFC
Delete the dead code for Write(ilist_iterator) in the IR Verifier,
inline report(ilist_iterator) at its call sites in the MachineVerifier,
and use simple_ilist<>::iterator in SymbolTableListTraits.
The only remaining reference to ilist_iterator outside of the ilist
implementation is from MachineInstrBundleIterator. I'll get rid of that
in a follow-up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280565
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Duncan P. N. Exon Smith [Sat, 3 Sep 2016 01:06:08 +0000 (01:06 +0000)]
ADT: Fix up IListTest.privateNode and get it passing
This test was using the wrong type, and so not actually testing much.
ilist_iterator constructors weren't going through ilist_node_access, so
they didn't actually work with private inheritance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280564
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Hal Finkel [Fri, 2 Sep 2016 23:42:01 +0000 (23:42 +0000)]
[PowerPC] Add asm parser/disassembler support for hrfid,nap,slbmfev
These few book-III instructions are used by the Linux kernel.
Partially fixes PR24796.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280560
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Hal Finkel [Fri, 2 Sep 2016 23:41:54 +0000 (23:41 +0000)]
[PowerPC] Add support for the extended dcbf form and mnemonics
dcbf has an optional hint-like field, add support for the extended form and the
associated mnemonics (dcbfl and dcbflp).
Partially fixes PR24796.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280559
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Yunzhong Gao [Fri, 2 Sep 2016 23:15:29 +0000 (23:15 +0000)]
(LLVM part) Implement MASM-flavor intel syntax behavior for inline MS asm block:
1. 0xNN and NNh are accepted as valid hexadecimal numbers, but 0xNNh is not.
0xNN and NNh may come with optional U or L suffix.
2. NNb is accepted as a valid binary (base-2) number, but 0bNN is not.
NNb may come with optional U or L suffix.
Differential Revision: https://reviews.llvm.org/D22112
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280555
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Ron Lieberman [Fri, 2 Sep 2016 22:56:24 +0000 (22:56 +0000)]
Make sure to maintain register liveness when generating predicated instructions.
Author: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Differential Revision: https://reviews.llvm.org/D24209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280552
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Gor Nishanov [Fri, 2 Sep 2016 22:54:26 +0000 (22:54 +0000)]
gitignore: ignore VS Code editor files
Summary: VS code creates .vscode folder to keep its stuff that we really don't need in git.
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D24211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280551
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Ivan Krasin [Fri, 2 Sep 2016 22:31:24 +0000 (22:31 +0000)]
lit: print process output, if getting the list of google-tests failed.
Summary:
This is a follow up to r280455, where a check for the process exit code
was introduced. Some ASAN bots throw this error now, but it's impossible
to understand what's wrong with them, and the issue is not reproducible.
Reviewers: vitalybuka
Differential Revision: https://reviews.llvm.org/D24210
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280550
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Zachary Turner [Fri, 2 Sep 2016 22:19:01 +0000 (22:19 +0000)]
[codeview] Make FieldList records print as a yaml sequence.
Before we were kind of imitating the behavior of a Yaml sequence
by outputting each record one after the other. This makes it a
little cumbersome when we want to go the other direction -- from
Yaml to Pdb. So this treats FieldList records as no different than
any other list of records, by printing them as a Yaml sequence with
the exact same format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280549
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Xinliang David Li [Fri, 2 Sep 2016 22:03:40 +0000 (22:03 +0000)]
[Profile] handle select instruction in 'expect' lowering
Builtin expect lowering currently ignores select. This patch
fixes the issue
Differential Revision: http://reviews.llvm.org/D24166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280547
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Hal Finkel [Fri, 2 Sep 2016 21:37:07 +0000 (21:37 +0000)]
[PowerPC] For larger offsets, when possible, fold offset into addis toc@ha
When we have an offset into a global, etc. that is accessed relative to the TOC
base pointer, and the offset is larger than the minimum alignment of the global
itself and the TOC base pointer (which is 8-byte aligned), we can still fold
the @toc@ha into the memory access, but we must update the addis instruction's
symbol reference with the offset as the symbol addend. When there is only one
use of the addi to be folded and only one use of the addis that would need its
symbol's offset adjusted, then we can make the adjustment and fold the @toc@l
into the memory access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280545
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James Y Knight [Fri, 2 Sep 2016 20:29:11 +0000 (20:29 +0000)]
[Sparc] Mark i128 shift libcalls unavailable in 32-bit mode.
Recently, llvm wants to emit calls to these functions, while it didn't
seem to be an issue before. Not sure why. Nor do I know why only these
three are important to disable, out of all of the i128 libcalls.
Nevertheless, many other targets have this snippet of code, so, just
copying it to sparc as well, to unbreak things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280537
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Jan Vesely [Fri, 2 Sep 2016 20:13:19 +0000 (20:13 +0000)]
AMDGPU/R600: EXTRACT_VECT_ELT should only bypass BUILD_VECTOR if the vectors have the same number of elements.
Fixes R600 piglit regressions since r280298
Differential Revision: https://reviews.llvm.org/D24174
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280535
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Sjoerd Meijer [Fri, 2 Sep 2016 19:51:34 +0000 (19:51 +0000)]
Setting fp trapping mode and denormal type: this an improvement of
r280246 and calculates compatibility of functions attributes in
a better way.
Differential Revision: https://reviews.llvm.org/D24070
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280534
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Krzysztof Parzyszek [Fri, 2 Sep 2016 19:48:55 +0000 (19:48 +0000)]
Do not consider subreg defs as reads when computing subrange liveness
Subregister definitions are considered uses for the purpose of tracking
liveness of the whole register. At the same time, when calculating live
interval subranges, subregister defs should not be treated as uses.
Differential Revision: https://reviews.llvm.org/D24190
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280532
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Sanjay Patel [Fri, 2 Sep 2016 19:38:37 +0000 (19:38 +0000)]
[InstCombine] auto-generate assertions for tighter checking
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280531
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Chad Rosier [Fri, 2 Sep 2016 19:09:50 +0000 (19:09 +0000)]
[SLP] Don't pass a global CL option as an argument. NFC.
Differential Revision: https://reviews.llvm.org/D24199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280527
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Jan Vesely [Fri, 2 Sep 2016 19:07:06 +0000 (19:07 +0000)]
AMDGPU/R600: Expand unaligned writes to local and global AS
LOCAL and GLOBAL AS only
PRIVATE needs special treatment
Differential Revision: https://reviews.llvm.org/D23971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280526
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Jan Vesely [Fri, 2 Sep 2016 18:52:28 +0000 (18:52 +0000)]
AMDGPU: Reorganize store tests
Split by AS.
Merge with some prviously failing tests.
Differential Revision: https://reviews.llvm.org/D23969
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280523
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Reid Kleckner [Fri, 2 Sep 2016 18:43:27 +0000 (18:43 +0000)]
[codeview] Use the correct max CV record length of 0xFF00
Previously we were splitting our records at 0xFFFF bytes, which the
Microsoft tools don't like.
Should fix failure on the new Windows self-host buildbot.
This length appears in microsoft-pdb/PDB/dbi/dbiimpl.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280522
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Kyle Butt [Fri, 2 Sep 2016 18:29:28 +0000 (18:29 +0000)]
IfConversion: Add assertions that both sides of a diamond don't pred-clobber.
One side of a diamond may end with a predicate clobbering instruction.
That side of the diamond has to be if-converted second. Both sides can't
clobber the predicate or the ifconversion is invalid. This is checked
elsewhere, but add an assert as a safety check. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280518
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Kyle Butt [Fri, 2 Sep 2016 18:29:26 +0000 (18:29 +0000)]
IfConversion: Fix bug introduced by rescanning diamonds.
Passing the wrong values for predicate-clobbering. Simple to miss.
Added an assert to make this easier to catch in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280517
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Adam Nemet [Fri, 2 Sep 2016 17:20:32 +0000 (17:20 +0000)]
Fix up comment from r280442, noticed by Justin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280508
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Wei Mi [Fri, 2 Sep 2016 17:17:04 +0000 (17:17 +0000)]
Split the store of a wide value merged from an int-fp pair into multiple stores.
For the store of a wide value merged from a pair of values, especially int-fp pair,
sometimes it is more efficent to split it into separate narrow stores, which can
remove the bitwise instructions or sink them to colder places.
Now the feature is only enabled on x86 target, and only store of int-fp pair is
splitted. It is possible that the application scope gets extended with perf evidence
support in the future.
Differential Revision: https://reviews.llvm.org/D22840
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280505
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Sanjay Patel [Fri, 2 Sep 2016 17:05:43 +0000 (17:05 +0000)]
[InsttCombine] fold insertelement of constant into shuffle with constant operand (PR29126)
The motivating case occurs with SSE/AVX scalar intrinsics, so this is a first step towards
shrinking that to a single shufflevector.
Note that the transform is intentionally limited to shuffles that are equivalent to vector
selects to avoid creating arbitrary shuffle masks that may not lower well.
This should solve PR29126:
https://llvm.org/bugs/show_bug.cgi?id=29126
Differential Revision: https://reviews.llvm.org/D23886
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280504
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Davide Italiano [Fri, 2 Sep 2016 16:37:31 +0000 (16:37 +0000)]
[lib/LTO] Simplify. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280503
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Reid Kleckner [Fri, 2 Sep 2016 16:33:15 +0000 (16:33 +0000)]
Quick fix to make LIT_PRESERVES_TMP work again
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280502
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Reid Kleckner [Fri, 2 Sep 2016 16:29:24 +0000 (16:29 +0000)]
[lit] Clean up temporary files created by tests
Do this by creating a temp directory in the normal system temp
directory, and cleaning it up on exit.
It is still possible for this temp directory to leak if Python exits
abnormally, but this is probably good enough for now.
Fixes PR18335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280501
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Derek Schuff [Fri, 2 Sep 2016 16:26:24 +0000 (16:26 +0000)]
[WebAssembly] Update known test failures
Fixed an issue with the experimental C headers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280498
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Matthew Simpson [Fri, 2 Sep 2016 16:19:22 +0000 (16:19 +0000)]
[LV] Ensure reverse interleaved group GEPs remain uniform
For uniform instructions, we're only required to generate a scalar value for
the first vector lane of each unroll iteration. Thus, if we have a reverse
interleaved group, computing the member index off the scalar GEP corresponding
to the last vector lane of its pointer operand technically makes the GEP
non-uniform. We should compute the member index off the first scalar GEP
instead.
I've added the updated member index computation to the existing reverse
interleaved group test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280497
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Andrea Di Biagio [Fri, 2 Sep 2016 15:55:25 +0000 (15:55 +0000)]
Simplify code a bit. No functional change intended.
We don't need to call `GetCompareTy(LHS)' every single time true or false is
returned from function SimplifyFCmpInst as suggested by Sanjay in review D24142.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280491
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Sanjay Patel [Fri, 2 Sep 2016 15:43:25 +0000 (15:43 +0000)]
fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280489
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Andrea Di Biagio [Fri, 2 Sep 2016 14:47:43 +0000 (14:47 +0000)]
[instsimplify] Fix incorrect folding of an ordered fcmp with a vector of all NaN.
This patch fixes a crash caused by an incorrect folding of an ordered comparison
between a packed floating point vector and a splat vector of NaN.
An ordered comparison between a vector and a constant vector of NaN, should
always be folded into a constant vector where each element is i1 false.
Since revision 266175, SimplifyFCmpInst folds the ordered fcmp into a scalar
'false'. Later on, this would cause an assertion failure, since the value type
of the folded value doesn't match the expected value type of the uses of the
original instruction: "Assertion failed: New->getType() == getType() &&
"replaceAllUses of value with new value of different type!".
This patch fixes the issue and adds a test case to the already existing test
InstSimplify/floating-point-compares.ll.
Differential Revision: https://reviews.llvm.org/D24143
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280488
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Andrea Di Biagio [Fri, 2 Sep 2016 11:29:09 +0000 (11:29 +0000)]
[DAGcombiner] Fix incorrect sinking of a truncate into the operand of a shift.
This fixes a regression introduced by revision 268094.
Revision 268094 added the following dag combine rule:
// trunc (shl x, K) -> shl (trunc x), K => K < vt.size / 2
That rule converts a truncate of a shift-by-constant into a shift of a truncated
value. We do this only if the shift count is less than half the size in bits of
the truncated value (K < vt.size / 2).
The problem is that the constraint on the shift count is incorrect, so the rule
doesn't work well in some cases involving vector types. The combine rule should
have been written instead like this:
// trunc (shl x, K) -> shl (trunc x), K => K < vt.getScalarSizeInBits()
Basically, if K is smaller than the "scalar size in bits" of the truncated value
then we know that by "sinking" the truncate into the operand of the shift we
would never accidentally make the shift undefined.
This patch fixes the check on the shift count, and adds test cases to make sure
that we don't regress the behavior.
Differential Revision: https://reviews.llvm.org/D24154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280482
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Andrey Bokhanko [Fri, 2 Sep 2016 11:13:35 +0000 (11:13 +0000)]
Fixed a typo (LLVM/Support/CFG.h -> LLVM/IR/CFG.h)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280481
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Chandler Carruth [Fri, 2 Sep 2016 10:49:58 +0000 (10:49 +0000)]
[PM] Try to fix an MSVC2013 failure due to finding a template
constructor when trying to do copy construction by adding an explicit
move constructor.
Will watch the bots to discover if this is sufficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280479
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Alexey Bataev [Fri, 2 Sep 2016 09:00:53 +0000 (09:00 +0000)]
[InstCombine] Add test for insertelementinsts with constants.
Added a tests that shows that several insertelementinsts with constant
indexes/data are not folded into a single shuffleinst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280474
91177308-0d34-0410-b5e6-
96231b3b80d8