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Peter Maydell [Tue, 12 Sep 2023 14:04:27 +0000 (15:04 +0100)]
target/arm: New function allocation_tag_mem_probe()
For the FEAT_MOPS operations, the existing allocation_tag_mem()
function almost does what we want, but it will take a watchpoint
exception even for an ra == 0 probe request, and it requires that the
caller guarantee that the memory is accessible. For FEAT_MOPS we
want a function that will not take any kind of exception, and will
return NULL for the not-accessible case.
Rename allocation_tag_mem() to allocation_tag_mem_probe() and add an
extra 'probe' argument that lets us distinguish these cases;
allocation_tag_mem() is now a wrapper that always passes 'false'.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20230912140434.
1333369-6-peter.maydell@linaro.org
Peter Maydell [Tue, 12 Sep 2023 14:04:26 +0000 (15:04 +0100)]
target/arm: Define syndrome function for MOPS exceptions
The FEAT_MOPS memory operations can raise a Memory Copy or Memory Set
exception if a copy or set instruction is executed when the CPU
register state is not correct for that instruction. Define the
usual syn_* function that constructs the syndrome register value
for these exceptions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20230912140434.
1333369-5-peter.maydell@linaro.org
Peter Maydell [Tue, 12 Sep 2023 14:04:25 +0000 (15:04 +0100)]
target/arm: Pass unpriv bool to get_a64_user_mem_index()
In every place that we call the get_a64_user_mem_index() function
we do it like this:
memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s);
Refactor so the caller passes in the bool that says whether they
want the 'unpriv' or 'normal' mem_index rather than having to
do the ?: themselves.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20230912140434.
1333369-4-peter.maydell@linaro.org
Peter Maydell [Tue, 12 Sep 2023 14:04:24 +0000 (15:04 +0100)]
target/arm: Implement FEAT_MOPS enable bits
FEAT_MOPS defines a handful of new enable bits:
* HCRX_EL2.MSCEn, SCTLR_EL1.MSCEn, SCTLR_EL2.MSCen:
define whether the new insns should UNDEF or not
* HCRX_EL2.MCE2: defines whether memops exceptions from
EL1 should be taken to EL1 or EL2
Since we don't sanitise what bits can be written for the SCTLR
registers, we only need to handle the new bits in HCRX_EL2, and
define SCTLR_MSCEN for the new SCTLR bit value.
The precedence of "HCRX bits acts as 0 if SCR_EL3.HXEn is 0" versus
"bit acts as 1 if EL2 disabled" is not clear from the register
definition text, but it is clear in the CheckMOPSEnabled()
pseudocode(), so we follow that. We'll have to check whether other
bits we need to implement in future follow the same logic or not.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20230912140434.
1333369-3-peter.maydell@linaro.org
Peter Maydell [Tue, 12 Sep 2023 14:04:23 +0000 (15:04 +0100)]
target/arm: Don't skip MTE checks for LDRT/STRT at EL0
The LDRT/STRT "unprivileged load/store" instructions behave like
normal ones if executed at EL0. We handle this correctly for
the load/store semantics, but get the MTE checking wrong.
We always look at s->mte_active[is_unpriv] to see whether we should
be doing MTE checks, but in hflags.c when we set the TB flags that
will be used to fill the mte_active[] array we only set the
MTE0_ACTIVE bit if UNPRIV is true (i.e. we are not at EL0).
This means that a LDRT at EL0 will see s->mte_active[1] as 0,
and will not do MTE checks even when MTE is enabled.
To avoid the translate-time code having to do an explicit check on
s->unpriv to see if it is OK to index into the mte_active[] array,
duplicate MTE_ACTIVE into MTE0_ACTIVE when UNPRIV is false.
(This isn't a very serious bug because generally nobody executes
LDRT/STRT at EL0, because they have no use there.)
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20230912140434.
1333369-2-peter.maydell@linaro.org
Peter Maydell [Thu, 7 Sep 2023 16:03:27 +0000 (17:03 +0100)]
target/arm: Remove unused allocation_tag_mem() argument
The allocation_tag_mem() function takes an argument tag_size,
but it never uses it. Remove the argument. In mte_probe_int()
in particular this also lets us delete the code computing
the value we were passing in.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Peter Maydell [Fri, 15 Sep 2023 14:37:00 +0000 (15:37 +0100)]
target/arm: Implement FEAT_HBC
FEAT_HBC (Hinted conditional branches) provides a new instruction
BC.cond, which behaves exactly like the existing B.cond except
that it provides a hint to the branch predictor about the
likely behaviour of the branch.
Since QEMU does not implement branch prediction, we can treat
this identically to B.cond.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Peter Maydell [Fri, 15 Sep 2023 14:37:00 +0000 (15:37 +0100)]
target/arm: Update user-mode ID reg mask values
For user-only mode we reveal a subset of the AArch64 ID registers
to the guest, to emulate the kernel's trap-and-emulate-ID-regs
handling. Update the feature bit masks to match upstream kernel
commit
a48fa7efaf1161c1c.
None of these features are yet implemented by QEMU, so this
doesn't yet have a behavioural change, but implementation of
FEAT_MOPS and FEAT_HBC is imminent.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Peter Maydell [Fri, 15 Sep 2023 14:37:00 +0000 (15:37 +0100)]
target/arm: Update AArch64 ID register field definitions
Update our AArch64 ID register field definitions from the 2023-06
system register XML release:
https://developer.arm.com/documentation/ddi0601/2023-06/
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Peter Maydell [Fri, 15 Sep 2023 14:36:59 +0000 (15:36 +0100)]
linux-user/elfload.c: Report previously missing arm32 hwcaps
Add the code to report the arm32 hwcaps we were previously missing:
ss, ssbs, fphp, asimdhp, asimddp, asimdfhm, asimdbf16, i8mm
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Peter Maydell [Fri, 15 Sep 2023 14:36:59 +0000 (15:36 +0100)]
linux-user/elfload.c: Add missing arm and arm64 hwcap values
Our lists of Arm 32 and 64 bit hwcap values have lagged behind
the Linux kernel. Update them to include all the bits defined
as of upstream Linux git commit
a48fa7efaf1161c1 (in the middle
of the kernel 6.6 dev cycle).
For 64-bit, we don't yet implement any of the features reported via
these hwcap bits. For 32-bit we do in fact already implement them
all; we'll add the code to set them in a subsequent commit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Peter Maydell [Fri, 15 Sep 2023 14:36:59 +0000 (15:36 +0100)]
linux-user/elfload.c: Correct SME feature names reported in cpuinfo
Some of the names we use for CPU features in linux-user's dummy
/proc/cpuinfo don't match the strings in the real kernel in
arch/arm64/kernel/cpuinfo.c. Specifically, the SME related
features have an underscore in the HWCAP_FOO define name,
but (like the SVE ones) they do not have an underscore in the
string in cpuinfo. Correct the errors.
Fixes:
a55b9e7226708 ("linux-user: Emulate /proc/cpuinfo on aarch64 and arm")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Fabian Vogt [Fri, 15 Sep 2023 14:36:59 +0000 (15:36 +0100)]
hw/arm/boot: Set SCR_EL3.FGTEn when booting kernel
Just like
d7ef5e16a17c sets SCR_EL3.HXEn for FEAT_HCX, this commit
handles SCR_EL3.FGTEn for FEAT_FGT:
When we direct boot a kernel on a CPU which emulates EL3, we need to
set up the EL3 system registers as the Linux kernel documentation
specifies:
https://www.kernel.org/doc/Documentation/arm64/booting.rst
> For CPUs with the Fine Grained Traps (FEAT_FGT) extension present:
> - If EL3 is present and the kernel is entered at EL2:
> - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
Cc: qemu-stable@nongnu.org
Signed-off-by: Fabian Vogt <fvogt@suse.de>
Message-id:
4831384.GXAFRqVoOG@linux-e202.suse.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 15 Sep 2023 14:36:58 +0000 (15:36 +0100)]
docs/devel/loads-stores: Fix git grep regexes
The loads-and-stores documentation includes git grep regexes to find
occurrences of the various functions. Some of these regexes have
errors, typically failing to escape the '?', '(' and ')' when they
should be metacharacters (since these are POSIX basic REs). We also
weren't consistent about whether to have a ':' on the end of the
line introducing the list of regexes in each section.
Fix the errors.
The following shell rune will complain about any REs in the
file which don't have any matches in the codebase:
for re in $(sed -ne 's/ - ``\(\\<.*\)``/\1/p' docs/devel/loads-stores.rst); do git grep -q "$re" || echo "no matches for re $re"; done
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id:
20230904161703.
3996734-1-peter.maydell@linaro.org
Peter Maydell [Fri, 15 Sep 2023 14:36:58 +0000 (15:36 +0100)]
target/m68k: Add URL to semihosting spec
The spec for m68k semihosting is documented in the libgloss
sources. Add a comment with the URL for it, as we already
have for nios2 semihosting.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id:
20230801154451.
3505492-1-peter.maydell@linaro.org
Stefan Hajnoczi [Wed, 20 Sep 2023 17:56:18 +0000 (13:56 -0400)]
Merge tag 'pull-loongarch-
20230920' of https://gitlab.com/gaosong/qemu into staging
Add LASX instructions support.
# -----BEGIN PGP SIGNATURE-----
#
# iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZQqV7wAKCRBAov/yOSY+
# 35GTA/9rXGbr9pIUnlGstUnWzIJb0vs6f4kt9DaKRPF1zyxaF/59sgl3gqCNAjBA
# eAKfm5W4B8ABJ+PYR3ZVAg9AcAP9AOEi+qV6DgRwvYPPK3WbGqIpJL7i+7gNMMUs
# gppv+IfJEkri8YLXXa7GWffuGOebqdqyD6Pl1B2eiKS4KYSRGw==
# =fNr2
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 20 Sep 2023 02:49:19 EDT
# gpg: using RSA key
B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF
* tag 'pull-loongarch-
20230920' of https://gitlab.com/gaosong/qemu: (57 commits)
target/loongarch: CPUCFG support LASX
target/loongarch: Move simply DO_XX marcos togther
target/loongarch: Implement xvld xvst
target/loongarch: Implement xvshuf xvperm{i} xvshuf4i
target/loongarch: Implement xvpack xvpick xvilv{l/h}
target/loongarch: Implement xvreplve xvinsve0 xvpickve
target/loongarch: Implement xvinsgr2vr xvpickve2gr
target/loongarch: Implement xvbitsel xvset
target/loongarch: Implement xvfcmp
target/loongarch: Implement xvseq xvsle xvslt
target/loongarch: Implement LASX fpu fcvt instructions
target/loongarch: Implement LASX fpu arith instructions
target/loongarch: Implement xvfrstp
target/loongarch: Implement xvbitclr xvbitset xvbitrev
target/loongarch: Implement xvpcnt
target/loongarch: Implement xvclo xvclz
target/loongarch: Implement xvssrlrn xvssrarn
target/loongarch: Implement xvssrln xvssran
target/loongarch: Implement xvsrlrn xvsrarn
target/loongarch: Implement xvsrln xvsran
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Wed, 20 Sep 2023 17:56:01 +0000 (13:56 -0400)]
Merge tag 'hppa-btlb-pull-request' of https://github.com/hdeller/qemu-hppa into staging
Block-TLB support and linux-user fixes for hppa target
All 32-bit hppa CPUs allow a fixed number of TLB entries to have a
different page size than the default 4k.
Those are called "Block-TLBs" and are created at startup by the
operating system and managed by the firmware of hppa machines
through the firmware PDC_BLOCK_TLB call.
This patchset adds the necessary glue to SeaBIOS-hppa and
qemu to allow up to 16 BTLB entries in the emulation.
Two patches from Mikulas Patocka fix signal delivery issues
in linux-user on hppa.
# -----BEGIN PGP SIGNATURE-----
#
# iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZQnz0wAKCRD3ErUQojoP
# X6NDAP9F1Huhceot8peohGodRDOhnXWfDcjQZSDvadieKv/rJQEA60Z5QV5VlQgw
# SyUT4AcoiB7N4nvS+iDa+6dKfRH/YQM=
# =kqqt
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 19 Sep 2023 15:17:39 EDT
# gpg: using EDDSA key
BCE9123E1AD29F07C049BBDEF712B510A23A0F5F
# gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown]
# gpg: aka "Helge Deller <deller@kernel.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603
# Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F
* tag 'hppa-btlb-pull-request' of https://github.com/hdeller/qemu-hppa:
linux-user/hppa: lock both words of function descriptor
linux-user/hppa: clear the PSW 'N' bit when delivering signals
target/hppa: Wire up diag instruction to support BTLB
target/hppa: Extract diagnose immediate value
target/hppa: Add BTLB support to hppa TLB functions
target/hppa: Report and clear BTLBs via fw_cfg at startup
target/hppa: Allow up to 16 BTLB entries
target/hppa: Update to SeaBIOS-hppa version 9
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Song Gao [Thu, 14 Sep 2023 02:26:45 +0000 (10:26 +0800)]
target/loongarch: CPUCFG support LASX
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-58-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:44 +0000 (10:26 +0800)]
target/loongarch: Move simply DO_XX marcos togther
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-57-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:43 +0000 (10:26 +0800)]
target/loongarch: Implement xvld xvst
This patch includes:
- XVLD[X], XVST[X];
- XVLDREPL.{B/H/W/D};
- XVSTELM.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-56-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:42 +0000 (10:26 +0800)]
target/loongarch: Implement xvshuf xvperm{i} xvshuf4i
This patch includes:
- XVSHUF.{B/H/W/D};
- XVPERM.W;
- XVSHUF4i.{B/H/W/D};
- XVPERMI.{W/D/Q};
- XVEXTRINS.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-55-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:41 +0000 (10:26 +0800)]
target/loongarch: Implement xvpack xvpick xvilv{l/h}
This patch includes:
- XVPACK{EV/OD}.{B/H/W/D};
- XVPICK{EV/OD}.{B/H/W/D};
- XVILV{L/H}.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-54-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:40 +0000 (10:26 +0800)]
target/loongarch: Implement xvreplve xvinsve0 xvpickve
This patch includes:
- XVREPLVE.{B/H/W/D};
- XVREPL128VEI.{B/H/W/D};
- XVREPLVE0.{B/H/W/D/Q};
- XVINSVE0.{W/D};
- XVPICKVE.{W/D};
- XVBSLL.V, XVBSRL.V.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-53-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:39 +0000 (10:26 +0800)]
target/loongarch: Implement xvinsgr2vr xvpickve2gr
This patch includes:
- XVINSGR2VR.{W/D};
- XVPICKVE2GR.{W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-52-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:38 +0000 (10:26 +0800)]
target/loongarch: Implement xvbitsel xvset
This patch includes:
- XVBITSEL.V;
- XVBITSELI.B;
- XVSET{EQZ/NEZ}.V;
- XVSETANYEQZ.{B/H/W/D};
- XVSETALLNEZ.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-51-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:37 +0000 (10:26 +0800)]
target/loongarch: Implement xvfcmp
This patch includes:
- XVFCMP.cond.{S/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-50-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:36 +0000 (10:26 +0800)]
target/loongarch: Implement xvseq xvsle xvslt
This patch includes:
- XVSEQ[I].{B/H/W/D};
- XVSLE[I].{B/H/W/D}[U];
- XVSLT[I].{B/H/W/D/}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-49-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:35 +0000 (10:26 +0800)]
target/loongarch: Implement LASX fpu fcvt instructions
This patch includes:
- XVFCVT{L/H}.{S.H/D.S};
- XVFCVT.{H.S/S.D};
- XVFRINT[{RNE/RZ/RP/RM}].{S/D};
- XVFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- XVFTINT[RZ].{WU.S/LU.D};
- XVFTINT[{RNE/RZ/RP/RM}].W.D;
- XVFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- XVFFINT.{S.W/D.L}[U];
- X[CVFFINT.S.L, VFFINT{L/H}.D.W.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-48-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:34 +0000 (10:26 +0800)]
target/loongarch: Implement LASX fpu arith instructions
This patch includes:
- XVF{ADD/SUB/MUL/DIV}.{S/D};
- XVF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- XVF{MAX/MIN}.{S/D};
- XVF{MAXA/MINA}.{S/D};
- XVFLOGB.{S/D};
- XVFCLASS.{S/D};
- XVF{SQRT/RECIP/RSQRT}.{S/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-47-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:33 +0000 (10:26 +0800)]
target/loongarch: Implement xvfrstp
This patch includes:
- XVFRSTP[I].{B/H}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-46-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:32 +0000 (10:26 +0800)]
target/loongarch: Implement xvbitclr xvbitset xvbitrev
This patch includes:
- XVBITCLR[I].{B/H/W/D};
- XVBITSET[I].{B/H/W/D};
- XVBITREV[I].{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-45-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:31 +0000 (10:26 +0800)]
target/loongarch: Implement xvpcnt
This patch includes:
- VPCNT.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-44-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:30 +0000 (10:26 +0800)]
target/loongarch: Implement xvclo xvclz
This patch includes:
- XVCLO.{B/H/W/D};
- XVCLZ.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-43-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:29 +0000 (10:26 +0800)]
target/loongarch: Implement xvssrlrn xvssrarn
This patch includes:
- XVSSRLRN.{B.H/H.W/W.D};
- XVSSRARN.{B.H/H.W/W.D};
- XVSSRLRN.{BU.H/HU.W/WU.D};
- XVSSRARN.{BU.H/HU.W/WU.D};
- XVSSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSSRARNI.{B.H/H.W/W.D/D.Q};
- XVSSRLRNI.{BU.H/HU.W/WU.D/DU.Q};
- XVSSRARNI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-42-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:28 +0000 (10:26 +0800)]
target/loongarch: Implement xvssrln xvssran
This patch includes:
- XVSSRLN.{B.H/H.W/W.D};
- XVSSRAN.{B.H/H.W/W.D};
- XVSSRLN.{BU.H/HU.W/WU.D};
- XVSSRAN.{BU.H/HU.W/WU.D};
- XVSSRLNI.{B.H/H.W/W.D/D.Q};
- XVSSRANI.{B.H/H.W/W.D/D.Q};
- XVSSRLNI.{BU.H/HU.W/WU.D/DU.Q};
- XVSSRANI.{BU.H/HU.W/WU.D/DU.Q}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-41-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:27 +0000 (10:26 +0800)]
target/loongarch: Implement xvsrlrn xvsrarn
This patch includes:
- XVSRLRN.{B.H/H.W/W.D};
- XVSRARN.{B.H/H.W/W.D};
- XVSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSRARNI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-40-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:26 +0000 (10:26 +0800)]
target/loongarch: Implement xvsrln xvsran
This patch includes:
- XVSRLN.{B.H/H.W/W.D};
- XVSRAN.{B.H/H.W/W.D};
- XVSRLNI.{B.H/H.W/W.D/D.Q};
- XVSRANI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-39-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:25 +0000 (10:26 +0800)]
target/loongarch: Implement xvsrlr xvsrar
This patch includes:
- XVSRLR[I].{B/H/W/D};
- XVSRAR[I].{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-38-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:24 +0000 (10:26 +0800)]
target/loongarch: Implement xvsllwil xvextl
This patch includes:
- XVSLLWIL.{H.B/W.H/D.W};
- XVSLLWIL.{HU.BU/WU.HU/DU.WU};
- XVEXTL.Q.D, VEXTL.QU.DU.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-37-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:23 +0000 (10:26 +0800)]
target/loongarch: Implement xvsll xvsrl xvsra xvrotr
This patch includes:
- XVSLL[I].{B/H/W/D};
- XVSRL[I].{B/H/W/D};
- XVSRA[I].{B/H/W/D};
- XVROTR[I].{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-36-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:22 +0000 (10:26 +0800)]
target/loongarch: Implement LASX logic instructions
This patch includes:
- XV{AND/OR/XOR/NOR/ANDN/ORN}.V;
- XV{AND/OR/XOR/NOR}I.B.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-35-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:21 +0000 (10:26 +0800)]
target/loongarch: Implement xvldi
This patch includes:
- XVLDI.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-34-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:20 +0000 (10:26 +0800)]
target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz
This patch includes:
- XVMSKLTZ.{B/H/W/D};
- XVMSKGEZ.B;
- XVMSKNZ.B.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-33-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:19 +0000 (10:26 +0800)]
target/loongarch: Implement xvsigncov
This patch includes:
- XVSIGNCOV.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-32-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:18 +0000 (10:26 +0800)]
target/loongarch: Implement vext2xv
This patch includes:
- VEXT2XV.{H/W/D}.B, VEXT2XV.{HU/WU/DU}.BU;
- VEXT2XV.{W/D}.B, VEXT2XV.{WU/DU}.HU;
- VEXT2XV.D.W, VEXT2XV.DU.WU.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-31-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:17 +0000 (10:26 +0800)]
target/loongarch: Implement xvexth
This patch includes:
- XVEXTH.{H.B/W.H/D.W/Q.D};
- XVEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-30-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:16 +0000 (10:26 +0800)]
target/loongarch: Implement xvsat
This patch includes:
- XVSAT.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-29-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:15 +0000 (10:26 +0800)]
target/loongarch; Implement xvdiv/xvmod
This patch includes:
- XVDIV.{B/H/W/D}[U];
- XVMOD.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-28-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:14 +0000 (10:26 +0800)]
target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}
This patch includes:
- XVMADD.{B/H/W/D};
- XVMSUB.{B/H/W/D};
- XVMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-27-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:13 +0000 (10:26 +0800)]
target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}
This patch includes:
- XVMUL.{B/H/W/D};
- XVMUH.{B/H/W/D}[U];
- XVMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-26-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:12 +0000 (10:26 +0800)]
target/loongarch: Implement xvmax/xvmin
This patch includes:
- XVMAX[I].{B/H/W/D}[U];
- XVMIN[I].{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-25-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:11 +0000 (10:26 +0800)]
target/loongarch: Implement xvadda
This patch includes:
- XVADDA.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-24-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:10 +0000 (10:26 +0800)]
target/loongarch: Implement xvabsd
This patch includes:
- XVABSD.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-23-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:09 +0000 (10:26 +0800)]
target/loongarch: Implement xavg/xvagr
This patch includes:
- XVAVG.{B/H/W/D/}[U];
- XVAVGR.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-22-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:08 +0000 (10:26 +0800)]
target/loongarch: Implement xvaddw/xvsubw
This patch includes:
- XVADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-21-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:07 +0000 (10:26 +0800)]
target/loongarch: Implement xvhaddw/xvhsubw
This patch includes:
- XVHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU};
- XVHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-20-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:06 +0000 (10:26 +0800)]
target/loongarch: Implement xvsadd/xvssub
This patch includes:
- XVSADD.{B/H/W/D}[U];
- XVSSUB.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-19-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:05 +0000 (10:26 +0800)]
target/loongarch: Implement xvneg
This patch includes:
- XVNEG.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-18-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:04 +0000 (10:26 +0800)]
target/loongarch: Implement xvaddi/xvsubi
This patch includes:
- XVADDI.{B/H/W/D}U;
- XVSUBI.{B/H/W/D}U.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-17-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:03 +0000 (10:26 +0800)]
target/loongarch: Implement xvreplgr2vr
This patch includes:
- XVREPLGR2VR.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-16-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:02 +0000 (10:26 +0800)]
target/loongarch: Implement xvadd/xvsub
This patch includes:
- XVADD.{B/H/W/D/Q};
- XVSUB.{B/H/W/D/Q}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-15-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:01 +0000 (10:26 +0800)]
target/loongarch: Add avail_LASX to check LASX instructions
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-14-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:26:00 +0000 (10:26 +0800)]
target/loongarch: check_vec support check LASX instructions
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <
20230914022645.
1151356-13-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:25:59 +0000 (10:25 +0800)]
target/loongarch: Add LASX data support
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-12-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:25:58 +0000 (10:25 +0800)]
target/loongarch: Replace CHECK_SXE to check_vec(ctx, 16)
Introduce a new function check_vec to replace CHECK_SXE
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-11-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:25:57 +0000 (10:25 +0800)]
target/loongarch: Use gen_helper_gvec_2i for 2OP + imm vector instructions
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-10-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:25:56 +0000 (10:25 +0800)]
target/loongarch: Use gen_helper_gvec_2 for 2OP vector instructions
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-9-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:25:55 +0000 (10:25 +0800)]
target/loongarch: Use gen_helper_gvec_2_ptr for 2OP + env vector instructions
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-8-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:25:54 +0000 (10:25 +0800)]
target/loongarch: Use gen_helper_gvec_3 for 3OP vector instructions
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-7-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:25:53 +0000 (10:25 +0800)]
target/loongarch: Use gen_helper_gvec_3_ptr for 3OP + env vector instructions
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-6-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:25:52 +0000 (10:25 +0800)]
target/loongarch: Use gen_helper_gvec_4 for 4OP vector instructions
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-5-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:25:51 +0000 (10:25 +0800)]
target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector instructions
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-4-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:25:50 +0000 (10:25 +0800)]
target/loongarch: Implement gvec_*_vl functions
Create gvec_*_vl functions in order to hide oprsz.
This is used by gvec_v* functions for oprsz 16,
and will be used by gvec_x* functions for oprsz 32.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-3-gaosong@loongson.cn>
Song Gao [Thu, 14 Sep 2023 02:25:49 +0000 (10:25 +0800)]
target/loongarch: Renamed lsx*.c to vec* .c
Renamed lsx_helper.c to vec_helper.c and trans_lsx.c.inc to trans_vec.c.inc
So LASX can used them.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20230914022645.
1151356-2-gaosong@loongson.cn>
Mikulas Patocka [Sat, 16 Sep 2023 16:32:45 +0000 (18:32 +0200)]
linux-user/hppa: lock both words of function descriptor
The code in setup_rt_frame reads two words at haddr, but locks only one.
This patch fixes it to lock both.
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Acked-by: Helge Deller <deller@gmx.de>
Cc: qemu-stable@nongnu.org
Signed-off-by: Helge Deller <deller@gmx.de>
Mikulas Patocka [Sat, 16 Sep 2023 13:49:42 +0000 (15:49 +0200)]
linux-user/hppa: clear the PSW 'N' bit when delivering signals
qemu-hppa may crash when delivering a signal. It can be demonstrated with
this program. Compile the program with "hppa-linux-gnu-gcc -O2 signal.c"
and run it with "qemu-hppa -one-insn-per-tb a.out". It reports that the
address of the flag is 0xb4 and it crashes when attempting to touch it.
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <signal.h>
sig_atomic_t flag;
void sig(int n)
{
printf("&flag: %p\n", &flag);
flag = 1;
}
int main(void)
{
struct sigaction sa;
struct itimerval it;
sa.sa_handler = sig;
sigemptyset(&sa.sa_mask);
sa.sa_flags = SA_RESTART;
if (sigaction(SIGALRM, &sa, NULL)) perror("sigaction"), exit(1);
it.it_interval.tv_sec = 0;
it.it_interval.tv_usec = 100;
it.it_value.tv_sec = it.it_interval.tv_sec;
it.it_value.tv_usec = it.it_interval.tv_usec;
if (setitimer(ITIMER_REAL, &it, NULL)) perror("setitimer"), exit(1);
while (1) {
}
}
The reason for the crash is that the signal handling routine doesn't clear
the 'N' flag in the PSW. If the signal interrupts a thread when the 'N'
flag is set, the flag remains set at the beginning of the signal handler
and the first instruction of the signal handler is skipped.
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
Acked-by: Helge Deller <deller@gmx.de>
Cc: qemu-stable@nongnu.org
Signed-off-by: Helge Deller <deller@gmx.de>
Helge Deller [Wed, 13 Sep 2023 09:25:09 +0000 (11:25 +0200)]
target/hppa: Wire up diag instruction to support BTLB
Wire up the hppa diag instruction to support Block-TLBs
when called with the 0x100 value.
The diag_btlb() helper function does all necessary steps
to emulate the PDC BTLB firmware function, which includes
providing BTLB info, adding a new BTLB, deleting a BTLB
and removing all BTLBs.
Signed-off-by: Helge Deller <deller@gmx.de>
Stefan Hajnoczi [Tue, 19 Sep 2023 17:22:18 +0000 (13:22 -0400)]
Merge tag 'mem-2023-09-19' of https://github.com/davidhildenbrand/qemu into staging
Hi,
"Host Memory Backends" and "Memory devices" queue ("mem"):
- Support and document VM templating with R/O files using a new "rom"
parameter for memory-backend-file
- Some cleanups and fixes around NVDIMMs and R/O file handling for guest
RAM
- Optimize ioeventfd updates by skipping address spaces that are not
applicable
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 19 Sep 2023 06:25:45 EDT
# gpg: using RSA key
1BD9CAAD735C4C3A460DFCCA4DDE10F700FF835A
# gpg: issuer "david@redhat.com"
# gpg: Good signature from "David Hildenbrand <david@redhat.com>" [unknown]
# gpg: aka "David Hildenbrand <davidhildenbrand@gmail.com>" [full]
# gpg: aka "David Hildenbrand <hildenbr@in.tum.de>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 1BD9 CAAD 735C 4C3A 460D FCCA 4DDE 10F7 00FF 835A
* tag 'mem-2023-09-19' of https://github.com/davidhildenbrand/qemu:
memory: avoid updating ioeventfds for some address_space
machine: Improve error message when using default RAM backend id
softmmu/physmem: Hint that "readonly=on,rom=off" exists when opening file R/W for private mapping fails
docs: Start documenting VM templating
docs: Don't mention "-mem-path" in multi-process.rst
softmmu/physmem: Never return directories from file_ram_open()
softmmu/physmem: Fail creation of new files in file_ram_open() with readonly=true
softmmu/physmem: Bail out early in ram_block_discard_range() with readonly files
softmmu/physmem: Remap with proper protection in qemu_ram_remap()
backends/hostmem-file: Add "rom" property to support VM templating with R/O files
softmmu/physmem: Distinguish between file access mode and mmap protection
nvdimm: Reject writing label data to ROM instead of crashing QEMU
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Tue, 19 Sep 2023 17:22:10 +0000 (13:22 -0400)]
Merge tag 'firmware/edk2-
20230918-pull-request' of https://gitlab.com/kraxel/qemu into staging
edk2: update to edk2-stable202308
v2: include acpi test data updates
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# gpg: Signature made Mon 18 Sep 2023 09:32:53 EDT
# gpg: using RSA key
A0328CFFB93A17A79901FE7D4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* tag 'firmware/edk2-
20230918-pull-request' of https://gitlab.com/kraxel/qemu:
tests/acpi: disallow virt/SSDT.memhp updates
tests/acpi: update virt/SSDT.memhp
edk2: update binaries to edk2-stable202308
edk2: update submodule to edk2-stable202308
edk2: workaround edk-stable202308 bug
edk2: update build config
edk2: update build script
tests/acpi: allow virt/SSDT.memhp updates
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Tue, 19 Sep 2023 17:22:02 +0000 (13:22 -0400)]
Merge tag 'pull-ppc-
20230918' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2023-09-18:
In this short queue we're making two important changes:
- Nicholas Piggin is now the qemu-ppc maintainer. Cédric Le Goater and
Daniel Barboza will act as backup during Nick's transition to this new
role.
- Support for NVIDIA V100 GPU with NVLink2 is dropped from qemu-ppc.
Linux removed the same support back in 5.13, we're following suit now.
A xive Coverity fix is also included.
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# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 18 Sep 2023 09:24:44 EDT
# gpg: using EDDSA key
17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164
* tag 'pull-ppc-
20230918' of https://gitlab.com/danielhb/qemu:
spapr: Remove support for NVIDIA V100 GPU with NVLink2
ppc/xive: Fix uint32_t overflow
MAINTAINERS: Nick Piggin PPC maintainer, other PPC changes
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Tue, 19 Sep 2023 17:21:49 +0000 (13:21 -0400)]
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging
# -----BEGIN PGP SIGNATURE-----
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# gpg: Signature made Mon 18 Sep 2023 02:56:11 EDT
# gpg: using RSA key
EF04965B398D6211
# gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [full]
# Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211
* tag 'net-pull-request' of https://github.com/jasowang/qemu:
net/tap: Avoid variable-length array
net/dump: Avoid variable length array
hw/net/rocker: Avoid variable length array
hw/net/fsl_etsec/rings.c: Avoid variable length array
net: add initial support for AF_XDP network backend
tests: bump libvirt-ci for libasan and libxdp
e1000e: rename e1000e_ba_state and e1000e_write_hdr_to_rx_buffers
igb: packet-split descriptors support
igb: add IPv6 extended headers traffic detection
igb: RX payload guest writting refactoring
igb: RX descriptors guest writting refactoring
igb: rename E1000E_RingInfo_st
igb: remove TCP ACK detection
virtio-net: Add support for USO features
virtio-net: Add USO flags to vhost support.
tap: Add check for USO features
tap: Add USO support to tap device.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Tue, 19 Sep 2023 17:20:54 +0000 (13:20 -0400)]
Merge tag 'pull-tcg-
20230915-2' of https://gitlab.com/rth7680/qemu into staging
*: Delete checks for old host definitions
tcg/loongarch64: Generate LSX instructions
fpu: Add conversions between bfloat16 and [u]int8
fpu: Handle m68k extended precision denormals properly
accel/tcg: Improve cputlb i/o organization
accel/tcg: Simplify tlb_plugin_lookup
accel/tcg: Remove false-negative halted assertion
tcg: Add gvec compare with immediate and scalar operand
tcg/aarch64: Emit BTI insns at jump landing pads
[Resolved conflict between CPUINFO_PMULL and CPUINFO_BTI.
--Stefan]
* tag 'pull-tcg-
20230915-2' of https://gitlab.com/rth7680/qemu: (39 commits)
tcg: Map code_gen_buffer with PROT_BTI
tcg/aarch64: Emit BTI insns at jump landing pads
util/cpuinfo-aarch64: Add CPUINFO_BTI
tcg: Add tcg_out_tb_start backend hook
fpu: Handle m68k extended precision denormals properly
fpu: Add conversions between bfloat16 and [u]int8
accel/tcg: Introduce do_st16_mmio_leN
accel/tcg: Introduce do_ld16_mmio_beN
accel/tcg: Merge io_writex into do_st_mmio_leN
accel/tcg: Merge io_readx into do_ld_mmio_beN
accel/tcg: Replace direct use of io_readx/io_writex in do_{ld,st}_1
accel/tcg: Merge cpu_transaction_failed into io_failed
plugin: Simplify struct qemu_plugin_hwaddr
accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed
accel/tcg: Split out io_prepare and io_failed
accel/tcg: Simplify tlb_plugin_lookup
target/arm: Use tcg_gen_gvec_cmpi for compare vs 0
tcg: Add gvec compare with immediate and scalar operand
tcg/loongarch64: Implement 128-bit load & store
tcg/loongarch64: Lower rotli_vec to vrotri
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
hongmianquan [Wed, 30 Aug 2023 03:29:06 +0000 (11:29 +0800)]
memory: avoid updating ioeventfds for some address_space
When updating ioeventfds, we need to iterate all address spaces,
but some address spaces do not register eventfd_add|del call when
memory_listener_register() and they do nothing when updating ioeventfds.
So we can skip these AS in address_space_update_ioeventfds().
The overhead of memory_region_transaction_commit() can be significantly
reduced. For example, a VM with 8 vhost net devices and each one has
64 vectors, can reduce the time spent on memory_region_transaction_commit by 20%.
Message-ID: <
20230830032906.12488-1-hongmianquan@bytedance.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: hongmianquan <hongmianquan@bytedance.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 6 Sep 2023 12:05:03 +0000 (14:05 +0200)]
machine: Improve error message when using default RAM backend id
For migration purposes, users might want to reuse the default RAM
backend id, but specify a different memory backend.
For example, to reuse "pc.ram" on q35, one has to set
-machine q35,memory-backend=pc.ram
Only then, can a memory backend with the id "pc.ram" be created
manually.
Let's improve the error message by improving the hint. Use
error_append_hint() -- which in turn requires ERRP_GUARD().
Message-ID: <
20230906120503.359863-12-david@redhat.com>
Suggested-by: ThinerLogoer <logoerthiner1@163.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Mario Casquero <mcasquer@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 6 Sep 2023 12:05:02 +0000 (14:05 +0200)]
softmmu/physmem: Hint that "readonly=on,rom=off" exists when opening file R/W for private mapping fails
It's easy to miss that memory-backend-file with "share=off" (default)
will always try opening the file R/W as default, and fail if we don't
have write permissions to the file.
In that case, the user has to explicit specify "readonly=on,rom=off" to
get usable RAM, for example, for VM templating.
Let's hint that '-object memory-backend-file,readonly=on,rom=off,...'
exists to consume R/O files in a private mapping to create writable RAM,
but only if we have permissions to open the file read-only.
Message-ID: <
20230906120503.359863-11-david@redhat.com>
Suggested-by: ThinerLogoer <logoerthiner1@163.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 6 Sep 2023 12:05:01 +0000 (14:05 +0200)]
docs: Start documenting VM templating
Let's add some details about VM templating, focusing on the VM memory
configuration only.
There is much more to VM templating (VM state? block devices?), but I leave
that as future work.
Message-ID: <
20230906120503.359863-10-david@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 6 Sep 2023 12:05:00 +0000 (14:05 +0200)]
docs: Don't mention "-mem-path" in multi-process.rst
"-mem-path" corresponds to "memory-backend-file,share=off" and,
therefore, creates a private COW mapping of the file. For multi-proces
QEMU, we need proper shared file-backed memory.
Let's make that clearer.
Message-ID: <
20230906120503.359863-9-david@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 6 Sep 2023 12:04:59 +0000 (14:04 +0200)]
softmmu/physmem: Never return directories from file_ram_open()
open() does not fail on directories when opening them readonly (O_RDONLY).
Currently, we succeed opening such directories and fail later during
mmap(), resulting in a misleading error message.
$ ./qemu-system-x86_64 \
-object memory-backend-file,id=ram0,mem-path=tmp,readonly=true,size=1g
qemu-system-x86_64: unable to map backing store for guest RAM: No such device
To identify directories and handle them accordingly in file_ram_open()
also when readonly=true was specified, detect if we just opened a directory
using fstat() instead. Then, fail file_ram_open() right away, similarly
to how we now fail if the file does not exist and we want to open the
file readonly.
With this change, we get a nicer error message:
qemu-system-x86_64: can't open backing store tmp for guest RAM: Is a directory
Note that the only memory-backend-file will end up calling
memory_region_init_ram_from_file() -> qemu_ram_alloc_from_file() ->
file_ram_open().
Message-ID: <
20230906120503.359863-8-david@redhat.com>
Reported-by: Thiner Logoer <logoerthiner1@163.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Tested-by: Mario Casquero <mcasquer@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 6 Sep 2023 12:04:58 +0000 (14:04 +0200)]
softmmu/physmem: Fail creation of new files in file_ram_open() with readonly=true
Currently, if a file does not exist yet, file_ram_open() will create new
empty file and open it writable. However, it even does that when
readonly=true was specified.
Specifying O_RDONLY instead to create a new readonly file would
theoretically work, however, ftruncate() will refuse to resize the new
empty file and we'll get a warning:
ftruncate: Invalid argument
And later eventually more problems when actually mmap'ing that file and
accessing it.
If someone intends to let QEMU open+mmap a file read-only, better
create+resize+fill that file ahead of time outside of QEMU context.
We'll now fail with:
./qemu-system-x86_64 \
-object memory-backend-file,id=ram0,mem-path=tmp,readonly=true,size=1g
qemu-system-x86_64: can't open backing store tmp for guest RAM: No such file or directory
All use cases of readonly files (R/O NVDIMMs, VM templating) work on
existing files, so silently creating new files might just hide user
errors when accidentally specifying a non-existent file.
Note that the only memory-backend-file will end up calling
memory_region_init_ram_from_file() -> qemu_ram_alloc_from_file() ->
file_ram_open().
Move error reporting to the single caller.
Message-ID: <
20230906120503.359863-7-david@redhat.com>
Acked-by: Peter Xu <peterx@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 6 Sep 2023 12:04:57 +0000 (14:04 +0200)]
softmmu/physmem: Bail out early in ram_block_discard_range() with readonly files
fallocate() will fail, let's print a nicer error message.
Message-ID: <
20230906120503.359863-6-david@redhat.com>
Suggested-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 6 Sep 2023 12:04:56 +0000 (14:04 +0200)]
softmmu/physmem: Remap with proper protection in qemu_ram_remap()
Let's remap with the proper protection that we can derive from
RAM_READONLY.
Message-ID: <
20230906120503.359863-5-david@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 6 Sep 2023 12:04:55 +0000 (14:04 +0200)]
backends/hostmem-file: Add "rom" property to support VM templating with R/O files
For now, "share=off,readonly=on" would always result in us opening the
file R/O and mmap'ing the opened file MAP_PRIVATE R/O -- effectively
turning it into ROM.
Especially for VM templating, "share=off" is a common use case. However,
that use case is impossible with files that lack write permissions,
because "share=off,readonly=on" will not give us writable RAM.
The sole user of ROM via memory-backend-file are R/O NVDIMMs, but as we
have users (Kata Containers) that rely on the existing behavior --
malicious VMs should not be able to consume COW memory for R/O NVDIMMs --
we cannot change the semantics of "share=off,readonly=on"
So let's add a new "rom" property with on/off/auto values. "auto" is
the default and what most people will use: for historical reasons, to not
change the old semantics, it defaults to the value of the "readonly"
property.
For VM templating, one can now use:
-object memory-backend-file,share=off,readonly=on,rom=off,...
But we'll disallow:
-object memory-backend-file,share=on,readonly=on,rom=off,...
because we would otherwise get an error when trying to mmap the R/O file
shared and writable. An explicit error message is cleaner.
We will also disallow for now:
-object memory-backend-file,share=off,readonly=off,rom=on,...
-object memory-backend-file,share=on,readonly=off,rom=on,...
It's not harmful, but also not really required for now.
Alternatives that were abandoned:
* Make "unarmed=on" for the NVDIMM set the memory region container
readonly. We would still see a change of ROM->RAM and possibly run
into memslot limits with vhost-user. Further, there might be use cases
for "unarmed=on" that should still allow writing to that memory
(temporary files, system RAM, ...).
* Add a new "readonly=on/off/auto" parameter for NVDIMMs. Similar issues
as with "unarmed=on".
* Make "readonly" consume "on/off/file" instead of being a 'bool' type.
This would slightly changes the behavior of the "readonly" parameter:
values like true/false (as accepted by a 'bool'type) would no longer be
accepted.
Message-ID: <
20230906120503.359863-4-david@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 6 Sep 2023 12:04:54 +0000 (14:04 +0200)]
softmmu/physmem: Distinguish between file access mode and mmap protection
There is a difference between how we open a file and how we mmap it,
and we want to support writable private mappings of readonly files. Let's
define RAM_READONLY and RAM_READONLY_FD flags, to replace the single
"readonly" parameter for file-related functions.
In memory_region_init_ram_from_fd() and memory_region_init_ram_from_file(),
initialize mr->readonly based on the new RAM_READONLY flag.
While at it, add some RAM_* flags we missed to add to the list of accepted
flags in the documentation of some functions.
No change in functionality intended. We'll make use of both flags next
and start setting them independently for memory-backend-file.
Message-ID: <
20230906120503.359863-3-david@redhat.com>
Acked-by: Peter Xu <peterx@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
David Hildenbrand [Wed, 6 Sep 2023 12:04:53 +0000 (14:04 +0200)]
nvdimm: Reject writing label data to ROM instead of crashing QEMU
Currently, when using a true R/O NVDIMM (ROM memory backend) with a label
area, the VM can easily crash QEMU by trying to write to the label area,
because the ROM memory is mmap'ed without PROT_WRITE.
[root@vm-0 ~]# ndctl disable-region region0
disabled 1 region
[root@vm-0 ~]# ndctl zero-labels nmem0
-> QEMU segfaults
Let's remember whether we have a ROM memory backend and properly
reject the write request:
[root@vm-0 ~]# ndctl disable-region region0
disabled 1 region
[root@vm-0 ~]# ndctl zero-labels nmem0
zeroed 0 nmem
In comparison, on a system with a R/W NVDIMM:
[root@vm-0 ~]# ndctl disable-region region0
disabled 1 region
[root@vm-0 ~]# ndctl zero-labels nmem0
zeroed 1 nmem
For ACPI, just return "unsupported", like if no label exists. For spapr,
return "H_P2", similar to when no label area exists.
Could we rely on the "unarmed" property? Maybe, but it looks cleaner to
only disallow what certainly cannot work.
After all "unarmed=on" primarily means: cannot accept persistent writes. In
theory, there might be setups where devices with "unarmed=on" set could
be used to host non-persistent data (temporary files, system RAM, ...); for
example, in Linux, admins can overwrite the "readonly" setting and still
write to the device -- which will work as long as we're not using ROM.
Allowing writing label data in such configurations can make sense.
Message-ID: <
20230906120503.359863-2-david@redhat.com>
Fixes:
dbd730e85987 ("nvdimm: check -object memory-backend-file, readonly=on option")
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
Stefan Hajnoczi [Mon, 18 Sep 2023 15:04:21 +0000 (11:04 -0400)]
Merge tag 'pull-crypto-
20230915' of https://gitlab.com/rth7680/qemu into staging
Unify implementation of carry-less multiply.
Accelerate carry-less multiply for 64x64->128.
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# jqzAtg==
# =8nnk
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 15 Sep 2023 12:40:26 EDT
# gpg: using RSA key
7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-crypto-
20230915' of https://gitlab.com/rth7680/qemu:
host/include/aarch64: Implement clmul.h
host/include/i386: Implement clmul.h
target/ppc: Use clmul_64
target/s390x: Use clmul_64
target/i386: Use clmul_64
target/arm: Use clmul_64
crypto: Add generic 64-bit carry-less multiply routine
target/ppc: Use clmul_32* routines
target/s390x: Use clmul_32* routines
target/arm: Use clmul_32* routines
crypto: Add generic 32-bit carry-less multiply routines
target/ppc: Use clmul_16* routines
target/s390x: Use clmul_16* routines
target/arm: Use clmul_16* routines
crypto: Add generic 16-bit carry-less multiply routines
target/ppc: Use clmul_8* routines
target/s390x: Use clmul_8* routines
target/arm: Use clmul_8* routines
crypto: Add generic 8-bit carry-less multiply routines
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Gerd Hoffmann [Mon, 18 Sep 2023 13:00:24 +0000 (15:00 +0200)]
tests/acpi: disallow virt/SSDT.memhp updates
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Gerd Hoffmann [Mon, 18 Sep 2023 12:15:51 +0000 (14:15 +0200)]
tests/acpi: update virt/SSDT.memhp
The edk2 update caused an address change:
DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001)
{
Scope (\_SB)
{
Device (NVDR)
{
Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Hardware ID
[ ... ]
}
}
- Name (MEMA, 0x43D10000)
+ Name (MEMA, 0x43C90000)
}
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Gerd Hoffmann [Mon, 11 Sep 2023 19:09:54 +0000 (21:09 +0200)]
edk2: update binaries to edk2-stable202308
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Gerd Hoffmann [Mon, 11 Sep 2023 15:39:23 +0000 (17:39 +0200)]
edk2: update submodule to edk2-stable202308
New stable release was tagged in August 2023,
update the edk2 submodule to it.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Gerd Hoffmann [Mon, 11 Sep 2023 18:20:15 +0000 (20:20 +0200)]
edk2: workaround edk-stable202308 bug
Set PCD to workaround two fixes missing the release.
https://github.com/tianocore/edk2/commit/
8b66f9df1bb0fd5ebb743944d41cb33178cf2fdd
https://github.com/tianocore/edk2/commit/
020cc9e2e7053bb62247b0babbbe80cb855592e5
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>