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Bas Nieuwenhuizen [Thu, 28 Dec 2017 01:33:00 +0000 (02:33 +0100)]
radv: Enable DCC with transfers.
Before this DCC was in practice disabled for most games. This
enables practical DCC use. Expect a 5-10% perf increase on a
bunch of games on vega @ 4k.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Bas Nieuwenhuizen [Fri, 29 Dec 2017 00:57:17 +0000 (01:57 +0100)]
radv: Decompress copy destination if formats are incompatible.
If both source and destination are DCC compressed, and their formats
are not compatible, we need to decompress one of them to make
sure we can do reinterpretation (which needs src format == dst format)
.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Bas Nieuwenhuizen [Thu, 28 Dec 2017 01:54:10 +0000 (02:54 +0100)]
radv: Disable DCC for GENERAL layout and compute transfer dest.
Apps can use this for render feedback loops, where things are
defined if they render each pixel only once. However, DCC fails
here, as the level of coherence is a block not a pixel, so disable it.
This is also going to help implementing other stuff.
Even if we optimize this later to only happen if there actually is
a loop (if possible at all ...), then the machinery is still useful
to exclude images accessible by the SDMA queue when that is implemented.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Bas Nieuwenhuizen [Fri, 29 Dec 2017 00:28:48 +0000 (01:28 +0100)]
radv: Don't init DCC metadata during FS resolve.
It should already be valid there + the RB will update it during
rendering.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Bas Nieuwenhuizen [Fri, 29 Dec 2017 00:25:07 +0000 (01:25 +0100)]
radv: Make color meta operations layout aware.
For fast clear eliminate and decompressions, we always use the most compressed
format.
For clears, the code already creates a renderpass on demand with the exact same
layout as specified.
Otherwise we start distinguishing between GENERAL and TRANSFER_DST_OPTIMAL.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Bas Nieuwenhuizen [Sat, 23 Dec 2017 12:17:52 +0000 (13:17 +0100)]
radv: Add compute DCC decompress.
We do an in place copy where we read compressed and write decompressed.
By doing this in sizes that cover entire DCC blocks and waiting for all
reads in the block before starting to write we avoid corruption.
In the end we clear the DCC metadata to 0xffffffff.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Bas Nieuwenhuizen [Sat, 23 Dec 2017 11:37:13 +0000 (12:37 +0100)]
radv: Use the meta fast clear destructor on construction failure.
Simplifies failure paths. The caller already calls
radv_device_finish_meta_fast_clear_flush_state on failure.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Bas Nieuwenhuizen [Sat, 23 Dec 2017 11:18:29 +0000 (12:18 +0100)]
radv: Add GFX DCC decompress.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Bas Nieuwenhuizen [Sat, 23 Dec 2017 10:42:18 +0000 (11:42 +0100)]
radv: Don't enable DCC / TC compat HTILE for storage images.
We don't get a layout when binding to a descriptor set, but can
assume that the LAYOUT is GENERAL.
For DCC stores with the DCC bits set will result in a hang, so
better be safe than sorry.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Bas Nieuwenhuizen [Fri, 29 Dec 2017 09:59:27 +0000 (10:59 +0100)]
Revert "radv/gfx9: fix block compression texture views."
This reverts commit
59515780433837ad3975f8ed20b93cf2fe6870e5.
The mentioned commit causes a hang in DoW3 on Vega.
Fixes:
59515780433 "radv/gfx9: fix block compression texture views."
Acked-by: Dave Airlie <airlied@redhat.com>
Brian Paul [Thu, 28 Dec 2017 17:07:59 +0000 (10:07 -0700)]
svga: update SVGA_NEW_ flags for updating sampler state
The SVGA_NEW_FS flag is needed since we now examine the fragment
shader's fs_shadow_compare_units flags. The SVGA_NEW_TEXTURE_FLAGS
flag is not needed since it's only for pre-VGPU10.
No piglit changes. This doesn't fix any known issues but it could
pop up somewhere. Suggested by Charmaine.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Thu, 28 Dec 2017 17:38:29 +0000 (10:38 -0700)]
svga: whitespace, formatting fixes in svga_state_tss.c
Dave Airlie [Fri, 29 Dec 2017 01:32:36 +0000 (11:32 +1000)]
radv/gfx9: use correct swizzle parameter to work out border swizzle.
This should fix:
dEQP-VK.pipeline.sampler.view_type.*.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black
and a few others in that area.
Fixes:
b11c4a5546 (radv: add texture descriptor/fmask/cmask support for GFX9)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 29 Dec 2017 01:00:34 +0000 (11:00 +1000)]
radv/gfx9: use a bigger hammer to flush cb/db caches.
amdvlk is probably more subtle than this but it never uses
the inv cb/db variants, we fail some CTS tests without this.
Fixes:
dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*.
Fixes:
c2fbeb7ca05 (radv: add GFX9 cache flushing support.)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (for now :-)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 29 Dec 2017 00:30:39 +0000 (10:30 +1000)]
radv/gfx9: fix block compression texture views.
This ports a fix from amdvlk, to fix the sizing for mip levels
when block compressed images are viewed using uncompressed views.
Fixes:
dEQP-VK.image.texel_view_compatible.graphic.extended*bc*
Fixes:
e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 28 Dec 2017 23:20:21 +0000 (09:20 +1000)]
radv/gfx9: fix buffer to image for 3d images on compute queues
This fixes some of the broken:
dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests.
Fixes:
e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 28 Dec 2017 22:52:07 +0000 (08:52 +1000)]
radv/gfx9: fix 3d image clears on compute queues
This fixes some of the broken:
dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests.
Fixes:
e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 28 Dec 2017 07:10:35 +0000 (17:10 +1000)]
radv/gfx9: fix 3d image to image transfers on compute queues.
This fixes some of the broken:
dEQP-VK.synchronization.op.multi_queue.*64x64x8* tests.
Fixes:
e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Wed, 27 Dec 2017 16:41:30 +0000 (08:41 -0800)]
anv/device: Mark all state buffers as needing capture
Previously, we were flagging the instruction state buffer for capture
but not surface state or dynamic state. We want those captured too.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 27 Dec 2017 16:40:30 +0000 (08:40 -0800)]
intel/aubinator: Gracefully handle dynamic state not being available
Some older versions of the Vulkan driver didn't properly tag dynamic
state as needing to be captured. Also, this prevents crashes when
looking at dumps on older kernels.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 27 Dec 2017 16:39:10 +0000 (08:39 -0800)]
intel/aubinator: Free section data last
We were walking the sections, printing the batches, and then freeing
them in one pass. If the batch happens to reference any earlier
sections (which it almost certainly will since it's at the end), we will
access freed memory.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Eero Tamminen [Tue, 26 Dec 2017 15:21:21 +0000 (07:21 -0800)]
spirv: consider bitsize when handling OpSwitch cases
This reverts commit
7665383a33f9ce9256aa121cbe4d3bd948dff145 and is
squashed together with https://patchwork.freedesktop.org/patch/194610/
(spirv: avoid infinite loop / freeze in vtn_cfg_walk_blocks()) which
fixes https://bugs.freedesktop.org/show_bug.cgi?id=104359 properly.
Fixes:
9702fac68e (spirv: consider bitsize when handling OpSwitch cases)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104359
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Brian Paul [Thu, 28 Dec 2017 16:16:44 +0000 (09:16 -0700)]
svga: check for null fs pointer in update_samplers()
This can happen when there's no active fragment shader, such as
when using transform feedback. This wasn't hit by any Piglit test
but is hit by Daniel Rákos' Nature demo. VMware bug
2026189.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Wed, 27 Dec 2017 20:36:30 +0000 (13:36 -0700)]
st/mesa: increase size of glsl_base_type bitfields
Change
59f458cd8703b97b31b8 added more enums to glsl_base_type. We
have to bump up the size of the bitfields for fields of this type
for MSVC. Also, add another assertion to catch another place where
this enum bitfield is used.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Dave Airlie [Thu, 28 Dec 2017 06:31:48 +0000 (16:31 +1000)]
radv: fix pipeline statistics end query on compute queue
It's legal to a pipeline stat query on a compute queue,
but we'd emit the wrong packet here. This should fix it to emit
the correct packet.
Noticed while inspecting the mpv hang.
Fixes:
ad61eac250 (radv: factor out eop event writing code. (v2))
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 28 Dec 2017 06:26:18 +0000 (16:26 +1000)]
radv: fix events on compute queues.
The event emission wasn't sending the correct packet for gfx8 compute
queues, which explains why it works on vega fine.
This fixes the mpv vulkan hang.
Fixes:
ad61eac250 (radv: factor out eop event writing code. (v2))
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 27 Dec 2017 23:49:32 +0000 (09:49 +1000)]
radv: move local bos usage to a perftest flag.
These seem mildly unstable on vega, crashing CTS in various fun ways,
and looks like leaking memory.
Disable for now, but leave the option to enable them.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 27 Dec 2017 23:45:07 +0000 (09:45 +1000)]
vulkan/wsi: free cmd pools
We destroy the pools but don't free the container.
This fixes:
dEQP-VK.wsi.xlib.swapchain.simulate_oom*
Fixes:
d50937f137 (vulkan/wsi: Implement prime in a completely generic way)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 23 Dec 2017 10:43:49 +0000 (11:43 +0100)]
radv: Always use fragment resolve if dest uses DCC.
HW resolve does not support it either.
Fixes:
2a04f5481df "radv/meta: select resolve paths"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Wed, 27 Dec 2017 23:19:28 +0000 (00:19 +0100)]
radv: Use correct framebuffer size for partial FS resolves.
Framebuffer is from 0,0, not (dst.x, dst.y).
Fixes:
69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 26 Dec 2017 15:11:35 +0000 (16:11 +0100)]
radv: Fix fragment resolve destination offset.
The position start at (dst.x, dst.y), so if we want the source to
start at (src.x, src.y), we have to offset by (src.x-dst.x,src.y-dst.y).
Haven't tested that this fixed anything yet, but found by inspection.
Fixes:
69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Mon, 25 Dec 2017 13:30:50 +0000 (14:30 +0100)]
radv: Don't handle DCC in compute resolve.
If the destination has DCC, we will use the FS resolve.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Mon, 25 Dec 2017 13:27:28 +0000 (14:27 +0100)]
radv: Flush caches before subpass resolve.
Fixes:
f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Mon, 25 Dec 2017 12:15:06 +0000 (13:15 +0100)]
radv: Invert condition for all samples identical during resolve.
the samples_identical instruction returns 0 if they are differet, so
we have to do the extra work if the result is 0, not if it is != 0.
Fixes:
f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Eric Engestrom [Wed, 20 Dec 2017 15:53:10 +0000 (15:53 +0000)]
egl: don't try the software path twice
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reported-by: Brendan King <Brendan.King@imgtec.com>
Eric Engestrom [Wed, 20 Dec 2017 15:53:09 +0000 (15:53 +0000)]
egl: rename LIBGL_ALWAYS_SOFTWARE variable from UseFallback to ForceSoftware
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Wed, 20 Dec 2017 15:53:08 +0000 (15:53 +0000)]
egl: let each platform decided how to handle LIBGL_ALWAYS_SOFTWARE
My refactor in
47273d7312cb5b5b6b0b9 missed this early return; because
of it, setting UseFallback one layer above actually prevented the
software path from being used.
Remove this early return and let each platform's dri2_initialize_*()
decide what it can do with the LIBGL_ALWAYS_SOFTWARE restriction.
platform_{surfaceless,x11,wayland} were already handling it themselves.
Fixes:
47273d7312cb5b5b6b0b9 "egl: set UseFallback if LIBGL_ALWAYS_SOFTWARE is set"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reported-by: Brendan King <Brendan.King@imgtec.com>
Brendan King [Mon, 18 Dec 2017 16:33:18 +0000 (16:33 +0000)]
egl: link libEGL against the dynamic version of libglapi
Note: the following happens only when using slibtool.
Since this is a very serious breakage, we will keep the workaround until
a better solution is available.
DRI modules store the address of the dispatch table in a TLS variable,
_glapi_tls_Dispatch.
Changes to the way libEGL is built in
d884d8d0077c16d459b1 resulted in
it being statically linked against libglapi, and thus containing its own
copy of _glapi_tls_Dispatch. The result was that some applications would
fail to work (e.g. deqp-egl, which dynamically loads libEGL), due to the
DRI module storing the dispatch table address in one copy of
_glapi_tls_Dispatch, and libEGL obtaining the address from another copy
of the variable.
Fixes:
d884d8d0077c16d459b1 "egl/dri: link directly to libglapi.so"
Signed-off-by: Brendan King <Brendan.King@imgtec.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Dave Airlie [Wed, 27 Dec 2017 07:00:29 +0000 (17:00 +1000)]
radv: don't do format replacement on tc compat htile surfaces.
For copies the texture unit needs to know the depth format so
it can read the htile data properly.
This fixes:
dEQP-VK.renderpass.suballocation.formats.d32_sfloat_s8_uint.load.clear
Fixes:
ad3d98da9f (radv: enable tc compatible htile for d32s8 also.)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 27 Dec 2017 01:22:58 +0000 (11:22 +1000)]
radv/gfx9: use correct stencil format for tc compat htile.
This needs to correspond to the bit depth of the Z plane.
noticed in passing reading amdvlk.
Fixes:
fc6c77e162df3 (radv: fix TC-compat HTILE with VK_FORMAT_D32_SFLOAT_S8_UINT on Vega)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Brian Paul [Wed, 27 Dec 2017 18:05:52 +0000 (11:05 -0700)]
svga: move variant->fs_shadow_compare_units assignment
Fixes a crash since the variant object isn't allocated until later
in the function. Not sure how this got through.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:07 +0000 (20:56 +0100)]
amd/common: rework set_userdata_location() and rename to set_loc()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:06 +0000 (20:56 +0100)]
amd/common: rename set_userdata_location_shader() to set_loc_shader()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:05 +0000 (20:56 +0100)]
amd/common: replace set_userdata_location_indirect() by set_loc_desc()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:04 +0000 (20:56 +0100)]
amd/common: rename radv_define_vs_user_sgprs_phase2()
... to set_vs_specific_input_locs().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:03 +0000 (20:56 +0100)]
amd/common: rename radv_define_common_user_sgprs_phase2()
... to set_global_input_locs().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:02 +0000 (20:56 +0100)]
amd/common: rename add_user_sgpr_array_argument() to add_array_arg()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:01 +0000 (20:56 +0100)]
amd/common: replace add_sgpr_argument() by add_arg()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:00 +0000 (20:56 +0100)]
amd/common: replace add_user_sgpr_argument() by add_arg()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:55:59 +0000 (20:55 +0100)]
amd/common: replace add_vgpr_argument() by add_arg()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:55:58 +0000 (20:55 +0100)]
amd/common: add new add_arg() helper for SGPRs/VGPRs arguments
The idea is to clean up the add arguments logic.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:55:57 +0000 (20:55 +0100)]
amd/common: rename radv_define_common_user_sgprs_phase1()
... to declare_global_input_sgprs().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:55:56 +0000 (20:55 +0100)]
amd/common: rename radv_define_vs_user_sgprs_phase1()
... to declare_vs_specific_inputs_sgprs().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:55:55 +0000 (20:55 +0100)]
amd/common: do not try to declare input VS SGPRs for GS
It's a no-op anyway but it looked strange to me, remove it.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:55:54 +0000 (20:55 +0100)]
amd/common: add declare_vs_input_vgprs() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:55:53 +0000 (20:55 +0100)]
amd/common: add declare_tes_input_vgprs() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:55:52 +0000 (20:55 +0100)]
amd/common: remove unnecessary num_user_sgprs_used
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:55:51 +0000 (20:55 +0100)]
amd/common: remove unnecessary user_sgpr_count
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 13 Dec 2017 12:59:12 +0000 (13:59 +0100)]
radeonsi: make use of ac_init_exec_full_mask()
Similar to si_init_exec_full_mask().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Sun, 24 Dec 2017 22:38:01 +0000 (15:38 -0700)]
svga: use tgsi_util_get_shadow_ref_src_index() in a couple place
No piglit changes.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Sun, 24 Dec 2017 22:37:09 +0000 (15:37 -0700)]
tgsi: improve comment on tgsi_util_get_shadow_ref_src_index()
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Sun, 24 Dec 2017 05:11:47 +0000 (22:11 -0700)]
svga: fix TGSI_TEXTURE_SHADOW1D coordinate selection
Fixes about 24 Piglit tex-miplevel-selection tests.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Sat, 23 Dec 2017 21:16:52 +0000 (14:16 -0700)]
svga: fix shadow comparison failures
In some cases, We do shadow comparison cases in the fragment shader
instead of with texture sampler state. But when we do so, we must
disable the shadow comparison test in the sampler state. As it
was, we were doing the comparison twice, which resulted in nonsense.
Also, we had the texcoord and texel value swapped in the comparison
instruction.
Fixes about 38 Piglit tex-miplevel-selection tests.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Sun, 24 Dec 2017 05:12:52 +0000 (22:12 -0700)]
util: add trivial comment on u_upload_create()
Dave Airlie [Wed, 27 Dec 2017 01:56:20 +0000 (01:56 +0000)]
r600: fix atomic counter index mode getting emitted on pre-cayman
This is a regression since I added cayman atomic support, not sure
it fixes anything, but the shader dumps look better.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Dec 2017 22:16:53 +0000 (08:16 +1000)]
radv: set some dcc parameters depending on if texture will be sampled
This is ported from amdvlk which sets the independent 64b blocks
only for image which will sample dcc.
I'm not sure how to port this to radeonsi.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Dec 2017 22:02:30 +0000 (08:02 +1000)]
radv/radeonsi: set dcc min uncompressed properly for APUs.
This is ported from amdvlk.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Dec 2017 21:56:12 +0000 (07:56 +1000)]
amd/common/radv/radeonsi: use register defines for dcc block sizes.
These are just taken from amdvlk, we probably knew these already,
but may as well port them now.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Wed, 13 Dec 2017 23:14:34 +0000 (10:14 +1100)]
st/glsl_to_nir: add patch support to st_nir_assign_var_locations()
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Thu, 14 Dec 2017 03:48:49 +0000 (14:48 +1100)]
st/glsl_to_nir: call post opt functions after opts have finished
We need to move this to a separate loop because
nir_compact_varyings() can alter the IR of a previous stage.
Fixes:
6648bd68fd27 "st/glsl_to_nir: enable NIR link time opts"
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Thu, 14 Dec 2017 05:02:45 +0000 (16:02 +1100)]
st/st_glsl_to_nir: call nir_lower_64bit_pack
Fixes 56 crashes in the radeonsi nir backend.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Wed, 27 Dec 2017 00:07:25 +0000 (00:07 +0000)]
docs/features: show es3.1 compat done on r600.
This was already being reported, just missed the docs.
Reported-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Miklós Máté [Sat, 2 Dec 2017 22:35:25 +0000 (23:35 +0100)]
mesa: always compare optype with symbolic name in ATI_fs
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Miklós Máté [Sat, 2 Dec 2017 22:35:24 +0000 (23:35 +0100)]
mesa: document ati_fragment_shader::cur_pass and swizzlerq
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Miklós Máté [Sat, 2 Dec 2017 22:35:23 +0000 (23:35 +0100)]
mesa: move ATI_fs state compile changes after the error checks
Both in setup and arithmetic instructions. Also, remove the useless
new_*_inst() functions, and refactor check_arith_arg(), because it did
two completely different things.
Piglit: spec/ati_fragment_shader/error04-endshader
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Miklós Máté [Sat, 2 Dec 2017 22:35:22 +0000 (23:35 +0100)]
tnl: fix not having texture coords in ATI_fs in swrast
ATI_fs in swrast only had access to texture coordinates if there was a
valid texture bound and texturing was enabled.
Piglit: spec/ati_fragment_shader/render-sources and render-notexture
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Miklós Máté [Sat, 2 Dec 2017 22:35:21 +0000 (23:35 +0100)]
mesa: fix not having secondary color in ATI_fs in swrast
ATI_fs in swrast only had secondary color if GL_COLOR_SUM was enabled.
This patch probably fixes the same issue in r200.
Piglit: spec/ati_fragment_shader/render-sources and render-precedence
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Miklós Máté [Sat, 2 Dec 2017 22:35:20 +0000 (23:35 +0100)]
mesa: fix validate for secondary interpolator
This patch fixes multiple problems:
- the interpolator check was duplicated
- both had arg instead of argRep
- I split it into color and alpha for better readability and error msg
- the DOT4 check only applies to color instruction according to the spec
- made the DOT4 check fatal, and improved the error msg
Piglit: spec/ati_fragment_shader/error08-secondary
v2: fixed formatting, added spec quotations
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Miklós Máté [Sat, 2 Dec 2017 22:35:19 +0000 (23:35 +0100)]
mesa: fix typo in ATI_fs dstMod error checking
Piglit: spec/ati_fragment_shader/error14-invalidmod
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Miklós Máté [Sat, 2 Dec 2017 22:35:18 +0000 (23:35 +0100)]
mesa: fix crash when an ATI_fs pass begins with an alpha inst
This fixes crash when:
- first pass begins with alpha inst
- first pass ends with color inst, second pass begins with alpha inst
Also, use the symbolic name instead of a number.
Piglit: spec/ati_fragment_shader/api-alphafirst
v2: fixed formatting
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Miklós Máté [Sat, 2 Dec 2017 22:35:17 +0000 (23:35 +0100)]
mesa: add fallback texture for SampleMapATI if there is nothing
This fixes crash in the state tracker.
Piglit: spec/ati_fragment_shader/render-notexture
v2: fixed formatting, moved stuff inside the loop,
moved the fallback later to fix more cases
Signed-off-by: Miklós Máté <mtmkls@gmail.com>
Marek Olšák [Tue, 12 Dec 2017 23:40:19 +0000 (00:40 +0100)]
radeonsi: don't use fast color clear for small images even on APUs
Increase the limit and handle non-square images better.
This makes glxgears 20% faster on APUs, and a little more on dGPUs.
We all use and love glxgears.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Mon, 11 Dec 2017 18:28:01 +0000 (19:28 +0100)]
radeonsi: set PNT_SPRITE_ENA = point_quad_rasterization
This is based on how nvc0 translates the state.
Marek Olšák [Mon, 11 Dec 2017 18:27:39 +0000 (19:27 +0100)]
gallium/util: add util_num_layers helper
Bas Nieuwenhuizen [Sat, 23 Dec 2017 00:40:03 +0000 (01:40 +0100)]
radv: Fix DCC compatible formats.
DCC was disabled when the image format is !!supported, which is one ! too many.
Ironically the commit that introduced it was supposed to lead to more DCC use ...
Fixes:
969537d9358 "radv: Add support for more DCC compression with VK_KHR_image_format_list."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Anuj Phogat [Fri, 22 Dec 2017 21:54:08 +0000 (13:54 -0800)]
Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+"
This reverts commit
9cd60fce9c22737000a8f8dc711141f8a523fe75.
Above commit caused 2000+ piglit tests to assert fail. Disabling
the align1 mode on gen10 for now to avoid failures.
Cc: Matt Turner <mattst88@gmail.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Andres Gomez [Fri, 22 Dec 2017 22:59:22 +0000 (00:59 +0200)]
docs: update calendar, add news item and link release notes for 17.2.8
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Fri, 22 Dec 2017 22:54:11 +0000 (00:54 +0200)]
docs: add sha256 checksums for 17.2.8
Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit
3281775ab9993d700a0a01a2823b6e7c72fce150)
Andres Gomez [Fri, 22 Dec 2017 20:39:47 +0000 (22:39 +0200)]
docs: add release notes for 17.2.8
Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit
3482790712e92d660706952f9ff282d904415941)
Ilia Mirkin [Fri, 22 Dec 2017 05:27:50 +0000 (00:27 -0500)]
freedreno: set missing internal_format when importing texture
Fixes running piglits without -fbo. Probably lots of other stuff too.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Samuel Pitoiset [Thu, 21 Dec 2017 16:53:15 +0000 (17:53 +0100)]
amd/common: add ac_export_mrt_z() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 21 Dec 2017 16:53:14 +0000 (17:53 +0100)]
amd/common: pass the family to ac_llvm_context_init()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 21 Dec 2017 16:45:23 +0000 (17:45 +0100)]
radv: reduce the number of small surfaces that need CMASK or DCC
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Ilia Mirkin [Wed, 20 Dec 2017 04:37:25 +0000 (23:37 -0500)]
gm107/ir: use lane 0 for manual textureGrad handling
This is parallel to the pre-SM50 change which does this. Adjusts the
shuffles / quadops to make the values correct relative to lane 0, and
then splat the results to all lanes for the final move into the target
register.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-By: Karol Herbst <kherbst@redhat.com>
Dave Airlie [Thu, 21 Dec 2017 06:52:24 +0000 (16:52 +1000)]
radv/meta: fix blit paths for depth/stencil (v2.1)
This fixes the layout issue for the blit path as well.
This fixes:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint*
v2: use compatible render passes.
v2.1: use enum
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 21 Dec 2017 06:23:30 +0000 (16:23 +1000)]
radv: handle depth/stencil image copy with layouts better. (v3.1)
If we are doing a general->general transfer with HIZ enabled,
we want to hit the tile surface disable bits in radv_emit_fb_ds_state,
however we never get the current layout to know we are in general
and meta hardcoded the transfer layout which is always tile enabled.
This fixes:
dEQP-VK.api.copy_and_blit.core.image_to_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint.optimal_general
dEQP-VK.api.copy_and_blit.core.image_to_image.all_formats.depth_stencil.d32_sfloat_s8_uint_d32_sfloat_s8_uint.general_general
v2: refactor some shared helpers for blit patches
v3: we only need multiple render passes as they should be compatible.
v3.1: use enum (Bas)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 20 Dec 2017 23:00:43 +0000 (09:00 +1000)]
radv: refactor blit2d pipeline creation
This just refactors the gfx9 blit2d pipeline creation
to be less lines of code.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 19 Dec 2017 05:42:10 +0000 (15:42 +1000)]
radv/gfx9: add support for 3d images to blit 2d paths
This add support for a 3D image reading path to the blit 2d paths,
like I did for the clear paths.
Fixes:
e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 19 Dec 2017 03:55:18 +0000 (13:55 +1000)]
radv/gfx9: add 3d sampler image->buffer copy shader. (v3)
On GFX9 we must access 3D textures with 3D samplers AFAICS.
This fixes:
dEQP-VK.api.image_clearing.core.clear_color_image.3d.single_layer
on GFX9 for me.
v1.1: fix tex->sampler_dim to dim
v2: send layer in from outside
v3: don't regress on pre-gfx9
Fixes:
e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 19 Dec 2017 05:41:42 +0000 (15:41 +1000)]
radv: fix surface max layer count (v2)
looking at traces I noticed we'd set slice_max too large sometimes.
This should fix it.
v2: fix missing - 1
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>