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Ilia Mirkin [Fri, 4 Dec 2015 20:21:11 +0000 (15:21 -0500)]
nv50/ir: propagate indirect loads into instructions
This way $r1 = $r0 + 4; c1[$r1] becomes c1[$r0+4].
On SM35:
total instructions in shared programs :
6206257 ->
6185058 (-0.34%)
total gprs used in shared programs : 911045 -> 910722 (-0.04%)
total local used in shared programs : 39072 -> 39072 (0.00%)
local gpr inst bytes
helped 0 417 4195 4195
hurt 0 280 0 0
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 4 Dec 2015 21:05:56 +0000 (16:05 -0500)]
nv50/ir: flip shl(add, imm) into add(shl, imm)
This works when the add also has an immediate. This often happens in
address calculations. These addresses can then be inlined as well.
On code targeted to SM35:
total instructions in shared programs :
6223346 ->
6206257 (-0.27%)
total gprs used in shared programs : 911075 -> 911045 (-0.00%)
total local used in shared programs : 39072 -> 39072 (0.00%)
local gpr inst bytes
helped 0 119 3664 3664
hurt 0 74 15 15
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Eric Anholt [Fri, 4 Dec 2015 21:41:50 +0000 (13:41 -0800)]
vc4: Fix accidental scissoring when scissor is disabled.
Even if the rasterizer has scissor disabled, we'll have whatever
vc4->scissor bounds were last set when someone set up a scissor, so we
shouldn't clip to them in that case.
Fixes piglit fbo-blit-rect, and a lot of MSAA tests once they're enabled.
Eric Anholt [Fri, 4 Dec 2015 21:15:01 +0000 (13:15 -0800)]
vc4: Disable RCL blitting when scissors are enabled.
We could potentially handle scissored blits when they're tile aligned, but
it doesn't seem worth it. If you're doing a scissored blit, you're
probably a testcase.
Fixes piglit's fbo-scissor-blit fbo
Eric Anholt [Sat, 5 Dec 2015 20:25:25 +0000 (12:25 -0800)]
vc4: Bring over cleanups from submitting to the kernel.
Samuel Pitoiset [Wed, 2 Dec 2015 22:52:07 +0000 (23:52 +0100)]
nvc0: expose a group of performance metrics for SM30 (Kepler)
This allows to monitor these performance metrics through
GL_AMD_performance_monitor.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 2 Dec 2015 15:56:23 +0000 (16:56 +0100)]
nvc0: re-introduce performance metrics for SM30 (Kepler)
This implements more performance metrics than the previous support,
but some other metrics still need to be figured out.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 2 Dec 2015 15:33:22 +0000 (16:33 +0100)]
nvc0: remove useless counting operations for MP counters
Those bits were related to old performance metrics support.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 2 Dec 2015 15:30:20 +0000 (16:30 +0100)]
nvc0: remove old performance metrics support on Kepler
These performance metrics will be re-introduced in an upcoming
patch that will follow the same design as Fermi.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 28 Oct 2015 13:34:43 +0000 (14:34 +0100)]
nvc0: remove wrong inst_issued HW SM perf counter on Kepler
inst_issued is performance metric not a hardware event on Kepler (SM30).
It will be re-introduced in an upcoming patch.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Mon, 19 Oct 2015 21:01:07 +0000 (23:01 +0200)]
nvc0: add missing HW SM perf counters for SM30 (Kepler)
SM30 is the compute capability version for GK104/GK106/GK107.
This also introduces a new signal group selection called UNK0F.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 2 Dec 2015 15:19:50 +0000 (16:19 +0100)]
nvc0: fix the comment that describe MP counters storage on Kepler
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Rob Clark [Sat, 5 Dec 2015 13:46:40 +0000 (08:46 -0500)]
freedreno/ir3: nir shader prints with 'disasm' debug option
Move these to 'disasm' instead of the more verbose 'optmsgs' since, like
the tgsi dumps, it is useful without the more verbose compiler logging
enabled.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Fri, 4 Dec 2015 20:08:23 +0000 (15:08 -0500)]
gallium/util: fix pipe_debug_message macro to allow 0 args
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Brian Paul <brianp@vmware.com>
Eric Anholt [Sun, 9 Aug 2015 21:16:30 +0000 (14:16 -0700)]
vc4: Add debug dumping of MSAA surfaces.
Eric Anholt [Tue, 23 Jun 2015 00:41:08 +0000 (17:41 -0700)]
vc4: Add support for laying out MSAA resources.
For MSAA, we store full resolution tile buffer contents, which have their
own tiling format. Since they're full resolution buffers, we have to
align their size to full tiles.
Eric Anholt [Sat, 21 Nov 2015 01:18:03 +0000 (17:18 -0800)]
vc4: Add support for storing sample mask.
From the API perspective, writing 1 bits can't turn on pixels that were
off, so we AND it with the sample mask from the payload.
Eric Anholt [Sun, 22 Nov 2015 03:26:54 +0000 (19:26 -0800)]
vc4: Fix up tile alignment checks for blitting using just an RCL.
We were checking that the blit started at 0 and was 1:1, but not that it
went to the full width of the surface, or that the width was aligned to a
tile. We then told it to blit to the full width/height of the surface,
causing contents to be stomped in a bunch of MSAA tests that happen to
include half-screen-width blits to 0,0.
Eric Anholt [Sat, 21 Nov 2015 01:11:18 +0000 (17:11 -0800)]
vc4: Add support for loading sample mask.
Rob Clark [Mon, 30 Nov 2015 20:52:26 +0000 (15:52 -0500)]
freedreno/ir3: convert scheduler back to recursive algo
I've played with a few different approaches to tweak instruction
priority according to how much they increase/decrease register pressure,
etc. But nothing seems to change the fact that compared to original
(pre-multiple-block-support) scheduler, in some edge cases we are
generating shaders w/ 5-6x higher register usage.
The problem is that the priority queue approach completely looses the
dependency between instructions, and ends up scheduling all paths at the
same time.
Original reason for switching was that recursive approach relied on
starting from the shader outputs array. But we can achieve more or less
the same thing by starting from the depth-sorted list.
shader-db results:
total instructions in shared programs: 113350 -> 105183 (-7.21%)
total dwords in shared programs: 219328 -> 211168 (-3.72%)
total full registers used in shared programs: 7911 -> 7383 (-6.67%)
total half registers used in shader programs: 109 -> 109 (0.00%)
total const registers used in shared programs: 21294 -> 21294 (0.00%)
half full const instr dwords
helped 0 322 0 711 215
hurt 0 163 0 38 4
The shaders hurt tend to gain a register or two. While there are also a
lot of helped shaders that only loose a register or two, the more
complex ones tend to loose significanly more registers used. In some
more extreme cases, like glsl-fs-convolution-1.shader_test it is more
like 7 vs 34 registers!
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 3 Dec 2015 16:49:51 +0000 (11:49 -0500)]
freedreno/ir3: don't reuse a0.x across blocks
It causes confusion in sched if we need to split_addr() since otherwise
we wouldn't easily know which block the new addr instr will be scheduled
in. So just side-step the whole situation.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 3 Dec 2015 15:21:32 +0000 (10:21 -0500)]
freedreno/ir3: rename ir3_block::bd
We'll need to add similar for ir3_instruction, but following the pattern
to use 'id' seems confusing. Let's just go w/ generic 'data' as the
name.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Giuseppe Bilotta [Fri, 4 Dec 2015 14:03:24 +0000 (14:03 +0000)]
util: fix comment typo
Undefining the NDEBUG is relevant for release build, as they are the
ones that set it.
[Emil Velikov: split from previous patch]
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Giuseppe Bilotta [Sun, 29 Nov 2015 17:19:35 +0000 (18:19 +0100)]
xvmc: force assertion in XvMC tests
This follows the src/util/u_atomic_test.c model of undefining NDEBUG
unconditionally throughouth the XvMC tests, to force asserts regardless
of debug mode.
The comment on u_atomic_test.c is also fixed (read 'debug' where it
should have been 'release').
v2: s/debug/release/ in relevant comments
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
[Emil Velikov: keep the src/util/ hunk as separate patch]
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Giuseppe Bilotta [Sat, 28 Nov 2015 15:43:56 +0000 (16:43 +0100)]
radeon: const correctness
Add missing `const` specifier for pointer pointing to a const struct.
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Giuseppe Bilotta [Sat, 28 Nov 2015 15:43:55 +0000 (16:43 +0100)]
radeon: whitespace cleanup
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 3 Dec 2015 22:01:31 +0000 (22:01 +0000)]
mesa/tests: add KHR_debug GLES glGetPointervKHR entry points
Should have been part of commit
f53f9eb8d49 "glapi: add GetPointervKHR
to the ES dispatch".
v2: comment out the ES1.1 symbol and use the same description (pattern)
as elsewhere (Matt)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93235
Fixes:
f53f9eb8d49 "glapi: add GetPointervKHR to the ES dispatch".
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Vinson Lee <vlee@freedesktop.org> (v1)
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Jason Ekstrand [Thu, 26 Nov 2015 08:05:32 +0000 (00:05 -0800)]
i965/vec4: Stop pretending to support indirect output stores
Since we're using nir_lower_outputs_to_temporaries to shadow all our
outputs, it's impossible to actually get an indirect store. The code we
had to "handle" this was pretty bogus as it created a register with a
reladdr and then stuffed it in a fixed varying slot without so much as a
MOV. Not only does this not do the MOV, it also puts the indirect on the
wrong side of the transaction. Let's just delete the broken dead code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Wed, 25 Nov 2015 22:01:00 +0000 (14:01 -0800)]
i965/vec4: Get rid of the nir_inputs array
It's not really buying us anything at this point. It's just a way of
remapping one offset namespace onto another. We can just use the location
namespace the whole way through.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Wed, 25 Nov 2015 20:33:38 +0000 (12:33 -0800)]
nir/lower_io: Pass the builder and type_size into get_io_offset
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Fri, 4 Dec 2015 04:43:44 +0000 (23:43 -0500)]
nv50/ir: replace zeros in movs as well
The original change to put zeroes directly into instructions created
conditional mov's with the zero immediate. However that can't be
emitted, so make sure to replace the zero with r63.
Fixes:
52a800a68 (nv50/ir: allow immediate 0 to be loaded anywhere)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Thu, 3 Dec 2015 02:02:12 +0000 (21:02 -0500)]
nv50/ir: fold fma/mad when all 3 args are immediates
This happens pretty rarely, but might as well do it when it does.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 4 Dec 2015 03:37:22 +0000 (22:37 -0500)]
nv50/ir: avoid looking at uninitialized srcMods entries
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Thu, 3 Dec 2015 19:04:06 +0000 (14:04 -0500)]
nv50/ir: fix DCE to not generate 96-bit loads
A situation where there's a 128-bit load where the last component gets
DCE'd causes a 96-bit load to be generated, which no GPU can actually
emit. Avoid generating such instructions by scaling back to 64-bit on
the first load when splitting.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Roland Scheidegger [Fri, 4 Dec 2015 02:42:02 +0000 (03:42 +0100)]
draw: fix clipping of layer/vp index outputs
This was just plain broken. It used always the value from v0 (for vp_index)
but would pass the value from the provoking vertex to later stages - but only
if there was a corresponding fs input, otherwise the layer/vp index would get
lost completely (as it would try to interpolate the (unsigned) values as
floats).
So, make it obey provoking vertex rules (drivers relying on draw will need to
do the same). And make sure that the default interpolation mode (when no
corresponding fs input is found) for them is constant.
Also, change the code a bit so constant inputs aren't interpolated then
copied over later.
Fixes the new piglit test gl-layer-render-clipped.
v2: more consistent whitespaces fixes for function defs, and more tab killing
(overall still not quite right however).
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Thu, 3 Dec 2015 00:19:52 +0000 (01:19 +0100)]
softpipe: use provoking vertex for layer
Same as for llvmpipe, albeit softpipe only really handles multiple layers,
not multiple viewports/scissors.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Thu, 3 Dec 2015 00:18:14 +0000 (01:18 +0100)]
llvmpipe: use provoking vertex for layer/viewport
d3d10 actually requires using provoking (first) vertex. GL is happy with
any vertex (as long as we say it's undefined in the corresponding queries).
Up to now we actually used vertex 0 for viewport index, and vertex 1 for
layer (for tris), which really didn't make sense (probably a typo). Also,$
since we reorder vertices of clockwise triangle, that actually meant we used
a different vertex depending if the traingle was cw or ccw (still ok by gl).
However, it should be consistent with what draw (clip) does, and using
provoking vertex seems like the sensible choice (draw clip will be fixed
next as it is totally broken there).
While here, also use the correct viewport always even when not needed
in setup (we pass it down to jit fragment shader it might be needed there
for getting correct near/far depth values).
No piglit changes.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Eric Anholt [Sun, 22 Nov 2015 03:10:02 +0000 (19:10 -0800)]
vc4: Add the RCL to CL debug dumping when in simulator mode.
We can't dump it in the real driver, since the kernel doesn't give us a
handle to it (except after a GPU hang, using a root ioctl). In the
simulator we can.
Marek Olšák [Thu, 3 Dec 2015 22:50:00 +0000 (23:50 +0100)]
radeonsi: fix Fiji for LLVM <= 3.7
Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Tue, 27 Oct 2015 22:10:51 +0000 (23:10 +0100)]
radeonsi: fix occlusion queries on Fiji
Tested.
Marek Olšák [Tue, 24 Nov 2015 22:00:00 +0000 (23:00 +0100)]
radeonsi: dump init_config IBs
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Mon, 23 Nov 2015 12:30:23 +0000 (13:30 +0100)]
radeonsi: print framebuffer info into ddebug logs
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sat, 21 Nov 2015 23:02:53 +0000 (00:02 +0100)]
gallium/radeon: print more info about HTILE
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sat, 21 Nov 2015 22:54:27 +0000 (23:54 +0100)]
gallium/radeon: print more info about CMASK
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sat, 21 Nov 2015 22:46:01 +0000 (23:46 +0100)]
gallium/radeon: rename fmask::pitch -> pitch_in_pixels
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sat, 21 Nov 2015 22:43:41 +0000 (23:43 +0100)]
gallium/radeon: print more information about textures
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Wed, 2 Dec 2015 19:20:57 +0000 (20:20 +0100)]
gallium/radeon: move printing texture info into a separate function
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sat, 21 Nov 2015 22:03:52 +0000 (23:03 +0100)]
gallium/radeon: remove unused r600_texture::pitch_override
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sat, 21 Nov 2015 21:35:04 +0000 (22:35 +0100)]
gallium/radeon: remove DBG_TEXMIP
we don't need 2 flags for dumping texture info
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Edward O'Callaghan [Thu, 3 Dec 2015 09:44:16 +0000 (20:44 +1100)]
gallium/aux/util: Trivial, we already have format use it
No need to dereference again, fixup for clarity.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Jose Fonseca [Wed, 2 Dec 2015 17:56:13 +0000 (17:56 +0000)]
automake: Fix typo in MSVC2008 compat flags.
It should be MSVC2008_COMPAT_CFLAGS and not MSVC2008_COMPAT_CXXFLAGS.
This is why the recent util_blitter breakage went unnoticed on autotools
builds.
Trivial.
Jose Fonseca [Wed, 2 Dec 2015 17:54:45 +0000 (17:54 +0000)]
ttn: Whitelist from -Werror=declaration-after-statement.
nir is the exception among gallium/auxiliary -- we don't need to compile
it with MSVC2008 yet. And this enables us to use
-Werror=declaration-after-statement in the next commit as we should,
without complicated fixes to tgsi_to_nir module.
Trvial. Tested with GCC and Clang.
Emil Velikov [Thu, 26 Nov 2015 00:36:17 +0000 (00:36 +0000)]
mesa: rework the meaning of gl_debug_message::length
Currently it stores strlen(buf) whenever the user originally provided a
negative value for length.
Although I've not seen any explicit text in the spec, CTS requires that
the very same length (be that negative value or not) is returned back on
Pop.
So let's push down the length < 0 checks, tweak the meaning of
gl_debug_message::length and fix GetDebugMessageLog to add and count the
null terminators, as required by the spec.
v2: return correct total length in GetDebugMessageLog
v3: rebase (drop _mesa_shader_debug hunk).
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Emil Velikov [Thu, 26 Nov 2015 00:36:16 +0000 (00:36 +0000)]
mesa: errors: validate the length of null terminated string
We're about to rework the meaning of gl_debug_message::length to only
store the user provided data. Thus we should add an explicit validation
for null terminated strings.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Emil Velikov [Thu, 26 Nov 2015 00:36:15 +0000 (00:36 +0000)]
mesa: accept TYPE_PUSH/POP_GROUP with glDebugMessageInsert
These new (relative to ARB_debug_output) tokens, have been explicitly
separated from the existing ones in the spec text. With the reference
to glDebugMessageInsert was dropped.
At the same time, further down the spec says:
"The value of <type> must be one of the values from Table 5.4"
... and these two are listed in Table 5.4.
The GL 4.3 and GLES 3.2 do not give any hints on the former
'definition', plus CTS requires that the tokens are valid values for
glDebugMessageInsert.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Emil Velikov [Thu, 26 Nov 2015 00:36:14 +0000 (00:36 +0000)]
mesa: add SEVERITY_NOTIFICATION to default state
As per the spec quote:
"All messages are initially enabled unless their assigned severity
is DEBUG_SEVERITY_LOW"
We already had MEDIUM and HIGH set, let's toggle NOTIFICATION as well.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Emil Velikov [Thu, 26 Nov 2015 00:36:13 +0000 (00:36 +0000)]
mesa: return the correct value for GroupStackDepth
We already have one group (the default) as specified in the spec. So
lets return its size, rather than the index of the current group.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Emil Velikov [Thu, 26 Nov 2015 00:36:12 +0000 (00:36 +0000)]
mesa: rename GroupStackDepth to CurrentGroup
The variable is used as the actual index, rather than the size of the
group stack - rename it to reflect that.
Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Emil Velikov [Thu, 26 Nov 2015 00:36:11 +0000 (00:36 +0000)]
mesa: do not enable KHR_debug for ES 1.0
The extension requires (cough implements) GetPointervKHR (alias of
GetPointerv) which in itself is available for ES 1.1 enabled mesa.
Anyone willing to fish around and implement it for ES 1.0 is more than
welcome to revert this commit. Until then lets restrict things.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93048
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Emil Velikov [Thu, 26 Nov 2015 00:36:10 +0000 (00:36 +0000)]
glapi: add GetPointervKHR to the ES dispatch
The KHR_debug extension implements this.
Strictly speaking it could be used with ES 1.0, although as the original
function is available on ES 1.1, I'm inclined to lift the KHR_debug
requirement to ES 1.1.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93048
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Nanley Chery [Tue, 1 Dec 2015 18:42:21 +0000 (10:42 -0800)]
mesa/version: Update gl_extensions::Version during version override
Commit
a16ffb743ced9fde80b2485dfc2d86ae74e86f25, which introduced
gl_extensions::Version, updates the field when the context version
is computed and when entering/exiting meta. Update this field when
the version is overridden as well.
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>
Brian Paul [Thu, 3 Dec 2015 16:40:38 +0000 (09:40 -0700)]
mesa: print enum names rather than hexadecimal values in error messages
Trivial.
Brian Paul [Thu, 3 Dec 2015 16:32:53 +0000 (09:32 -0700)]
st/wgl: add new stw_ext_rendertexture.c file
This should have been included in the previous commit.
Signed-off-by: Brian Paul <brianp@vmware.com>
Brian Paul [Thu, 3 Dec 2015 16:12:20 +0000 (09:12 -0700)]
st/wgl: add support for WGL_ARB_render_texture
There are a few legacy OpenGL apps on Windows which need this extension.
We basically use glCopyTex[Sub]Image to implement wglBindTexImageARB (see
the implementation notes for details).
v2: refactor code to use st_copy_framebuffer_to_texture() helper function.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Thu, 3 Dec 2015 00:29:27 +0000 (17:29 -0700)]
st/mesa: add new st_copy_framebuffer_to_texture() function
This helper is used by the WGL state tracker to implement the
wglBindTexImageARB() function.
This is basically a new "meta" function. However, we're not putting
it in the src/mesa/drivers/common/ directory because that code is not
linked with gallium-based drivers.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Juha-Pekka Heikkila [Wed, 2 Dec 2015 09:48:46 +0000 (11:48 +0200)]
glsl: remove useless null checks and make match_explicit_outputs_to_inputs() static
match_explicit_outputs_to_inputs() cannot get null inputs and if it ever did
triggering first null check would later in the function cause segfault.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
CC: timothy.arceri@collabora.com
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Tapani Pälli [Wed, 2 Dec 2015 11:21:37 +0000 (13:21 +0200)]
i965: use _Shader to get fragment program when updating surface state
Atomic counters and Images were using ctx::Shader that does not take in
to account program pipeline changes, ctx::_Shader must be used for SSO to
work. Commit
c0347705 already changed ubo's to use this.
Fixes failures seen with following Piglit test:
arb_separate_shader_object-atomic-counter
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Thu, 26 Nov 2015 04:36:23 +0000 (23:36 -0500)]
nv50/ir: fix moves to/from flags
Noticed this when looking at a trace that caused flags to spill to/from
registers. The flags source/destination wasn't encoded correctly
according to both envydis and nvdisasm.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Thu, 3 Dec 2015 01:02:12 +0000 (20:02 -0500)]
nv50/ir: don't forget to mark flagsDef on cvt in txb lowering
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Thu, 3 Dec 2015 01:24:33 +0000 (20:24 -0500)]
nv50/ir: fix instruction permutation logic
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Thu, 3 Dec 2015 01:10:54 +0000 (20:10 -0500)]
nv50/ir: the mad source might not have a defining instruction
For example if it's $r63 (aka 0), there won't be a definition.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Wed, 2 Dec 2015 05:38:22 +0000 (00:38 -0500)]
nv50/ir: make sure entire graph is reachable
The algorithm expects the entire CFG to be reachable, so make sure that
we hit every node. Otherwise we will end up with uninitialized data,
memory corruption, etc.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Wed, 2 Dec 2015 05:38:21 +0000 (00:38 -0500)]
nv50/ir: deal with loops with no breaks
For example if there are only returns, the break bb will not end up part
of the CFG. However there will have been a prebreak already emitted for
it, and when hitting the RET that comes after, we will try to insert the
current (i.e. break) BB into the graph even though it will be
unreachable. This makes the SSA code sad.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Wed, 2 Dec 2015 01:35:19 +0000 (20:35 -0500)]
nvc0/ir: fold postfactor into immediate
SM20-SM50 can't emit a post-factor in the presence of a long immediate.
Make sure to fold it in.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Tue, 1 Dec 2015 20:01:11 +0000 (15:01 -0500)]
nv50/ir: allow immediate 0 to be loaded anywhere
There's a post-RA fixup to replace 0's with $r63 (or $r127 if too many
regs are used), so just as nvc0, let an immediate 0 be loaded anywhere.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Wed, 2 Dec 2015 05:27:38 +0000 (21:27 -0800)]
i965: Add INTEL_DEBUG=perf information for GS recompiles.
Surprisingly, this didn't exist at all.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Wed, 2 Dec 2015 05:09:40 +0000 (21:09 -0800)]
i965: De-duplicate key_debug() function.
This appeared in brw_vs.c and brw_wm.c, should have appeared in
brw_gs.c, and was soon going to have to be in brw_tcs.c and brw_tes.c as
well.
So, instead, move it to a central location (which has to know about both
struct brw_context and perf_debug()).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Samuel Pitoiset [Wed, 2 Dec 2015 21:05:17 +0000 (22:05 +0100)]
nv50/ir/gk110: add memory barriers support for GK110
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sun, 29 Nov 2015 14:50:09 +0000 (15:50 +0100)]
nv50/ir: do not call textureMask() for surface ops
That texture mask thing doesn't seem to be needed for surface ops, so
just as nve4+, let do that only for texture ops.
This fixes a segfault with 'test_surface_st' from
gallium/tests/trivial/compute.c on Fermi because this test uses sustp.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Jose Fonseca [Thu, 26 Nov 2015 10:39:41 +0000 (10:39 +0000)]
appveyor: Initial integration.
AppVeyor doesn't require an appveyor.yml in the repos (in fact it has
some limitations as noted in comments below), but doing so has two great
advantages over the web UI:
- appveyor.yml can be revisioned together with the code, so instructions
should always be in synch with the code
- appveyor.yml can be reused for people's private repositories (be on
fdo or GitHub, etc.)
Acked-by: Roland Scheidegger <sroland@vmware.com>
Jose Fonseca [Wed, 2 Dec 2015 17:48:29 +0000 (17:48 +0000)]
util/blitter: Fix "SO C90 forbids mixed declarations and code".
Trivial.
Brian Paul [Tue, 1 Dec 2015 21:35:14 +0000 (14:35 -0700)]
mesa: print enum string in compressed_subtexture_error_check() error msg
Trivial.
Edward O'Callaghan [Thu, 26 Nov 2015 05:55:01 +0000 (16:55 +1100)]
gallium/util: Fix util_blitter_clear_depth_stencil() for num_layers>1
Previously util_blitter_clear_depth_stencil() could not clear more
than the first layer. We need to generalise this as we did for
util_blitter_clear_render_target().
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Thu, 26 Nov 2015 05:55:00 +0000 (16:55 +1100)]
gallium/util: Fix util_blitter_clear_render_target() for num_layers>1
Previously util_blitter_clear_render_target() could not clear more
than the first layer. We need to generalise this so that
ARB_clear_texture can pass the 3d piglit test.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Roland Scheidegger [Tue, 1 Dec 2015 19:06:59 +0000 (20:06 +0100)]
mesa: fix VIEWPORT_INDEX_PROVOKING_VERTEX and LAYER_PROVOKING_VERTEX queries
These are implementation-dependent queries, but so far we just returned the
value of whatever the current provoking vertex convention was set to, which
was clearly wrong.
Just make this a variable in the context constants like for other things
which are implementation dependent (I assume all drivers will want to set
this to the same value for both queries), and set it to GL_UNDEFINED_VERTEX
which is correct for everybody (and drivers can override it).
Reviewed-by: Brian Paul <brianp@vmware.com>
CC: <mesa-stable@lists.freedesktop.org>
Jose Fonseca [Tue, 1 Dec 2015 23:07:08 +0000 (23:07 +0000)]
Remove Sun CC specific code.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Jose Fonseca [Tue, 1 Dec 2015 22:43:46 +0000 (22:43 +0000)]
configure.ac: Refuse to build with Sun C compiler.
https://bugs.freedesktop.org/show_bug.cgi?id=93189
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>
Acked-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Eric Anholt [Tue, 1 Dec 2015 19:57:49 +0000 (11:57 -0800)]
travis: Add a test build with scons.
Since I just broke the scons build, I figured I'd make Travis test that I
don't break it again in the future. The script runs the builds in
parallel across VMs, so it still takes just 5 minutes to turn around
results.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Kenneth Graunke [Mon, 30 Nov 2015 09:54:42 +0000 (01:54 -0800)]
i965: Increase BRW_MAX_UBO to 14.
The NVIDIA binary driver and Intel's closed source driver both expose
14 here, rather than the GL minimum of 12. Let's follow suit.
Without this, Shadow of Mordor fails to render correctly and triggers
OpenGL errors:
Mesa: User error: GL_INVALID_VALUE in glBindBufferBase(index=68)
Mesa: User error: GL_INVALID_VALUE in glUniformBlockBinding(block binding 68 >= 60)
There are 5 stages (VS, TCS, TES, GS, FS), and 12 * 5 = 60 is too small.
14 * 5 = 70 will work just fine.
Tapani believes this will also help Alien Isolation.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Matt Turner [Mon, 30 Nov 2015 17:25:19 +0000 (09:25 -0800)]
i965: Do dead-code elimination in a single pass.
The first pass marked dead instructions as opcode = NOP, and a second
pass deleted those instructions so that the live ranges used in the
first pass wouldn't change.
But since we're walking the instructions in reverse order, we can just
do everything in one pass. The only thing we have to do is walk the
blocks in reverse as well.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Matt Turner [Mon, 30 Nov 2015 17:24:23 +0000 (09:24 -0800)]
glsl: Rename safe_reverse -> reverse_safe.
To match existing foreach_in_list_reverse_safe.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Matt Turner [Thu, 26 Nov 2015 00:19:06 +0000 (16:19 -0800)]
i965: Don't mark dead instructions' sources live.
Removes dead code from glsl-mat-from-int-ctor-03.shader_test.
Reported-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Dave Airlie [Tue, 24 Feb 2015 06:07:23 +0000 (16:07 +1000)]
r600: set mega fetch count to 16 for gs copy shader
Seems like MFC should be set for this shader.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 24 Feb 2015 05:58:33 +0000 (15:58 +1000)]
r600: increment ring index after emit vertex not before.
The docs say we should send the emit after the ring writes,
so lets do that and not have an ALU in between.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 24 Feb 2015 05:57:49 +0000 (15:57 +1000)]
r600: add alu + cf nop to copy shader on r600
SB suggests we do this for r600, so lets do it,
for the copy shader.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 24 Feb 2015 04:10:20 +0000 (14:10 +1000)]
r600: SMX returns CONTEXT_DONE early workaround
streamout, gs rings bug on certain r600s, requires a wait idle
before each surface sync.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 23 Feb 2015 20:14:31 +0000 (20:14 +0000)]
r600: do SQ flush ES ring rolling workaround
Need to insert a SQ_NON_EVENT when ever geometry
shaders are enabled.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Samuel Pitoiset [Tue, 1 Dec 2015 21:40:45 +0000 (22:40 +0100)]
nv50,nvc0: allow to create resources other than buffers
For the compute support, we might stick buffers as surfaces. This fixes
an assertion when executing src/gallium/tests/trivial/compute.
To avoid using these "restricted" surfaces as render targets, these
assertions have been moved. Note that it's already handled for the
framebuffer thing on nvc0.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Brian Paul [Tue, 1 Dec 2015 20:02:05 +0000 (13:02 -0700)]
glapi: work-around MSVC 65K string length limitation for enums.c
String literals cannot exceed 65535 characters for MSVC. Instead of
emiting a string, emit an array of characters.
v2: fix indentation and add comment in the gl_enums.py file about this
ugliness.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Tue, 1 Dec 2015 20:01:53 +0000 (12:01 -0800)]
mapi: Fix enums.c build with other build systems.
Tested with scons (by both myself and Mark Janes), Android is just copy
and paste.