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Alex Deucher [Tue, 2 May 2017 20:15:06 +0000 (16:15 -0400)]
drm/amdgpu/gfx9: derive tile pipes from golden settings
rather than hardcoding it.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 2 May 2017 19:49:36 +0000 (15:49 -0400)]
drm/amdgpu/gfx: drop max_gs_waves_per_vgt
We already have this info: max_gs_threads. Drop the duplicate.
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 4 May 2017 03:07:02 +0000 (11:07 +0800)]
drm/amd/powerplay: disable engine spread spectrum feature on Vega10.
Vega10 atomfirmware do not have ASIC_InternalSS_Info table
so disable this feature by default in driver.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Ken Wang <Qingqing.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 3 May 2017 04:48:52 +0000 (12:48 +0800)]
drm/amd/powerplay: clean up code in vega10_smumgr.c
1. fix typo in print message info.
2. fix block comments's coding style.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 1 May 2017 08:15:31 +0000 (16:15 +0800)]
drm/amdgpu:fix waiting on dirty fence
if bo->shadow is NULL (race issue:BO shadow was just released
and gpu-reset kick in but BO hasn't yet) recover_vram_from_shadow
won't set @next, so the following "fence=next"
will wrongly use a fence pointer which may already dirty.
fixing it by set next to NULL prior to recover_vram_from_shadow
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Chunming Zhou<david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Thu, 27 Apr 2017 09:14:57 +0000 (17:14 +0800)]
drm/amdgpu:PTE flag should be 64 bit width
otherwise we'll lost the high 32 bit for pte, which lead
to incorrect MTYPE for vega10.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 28 Apr 2017 05:49:50 +0000 (13:49 +0800)]
drm/amd/powerplay: correct LoadLineResistance value in pptable.
this value is used by avfs to adjust inversion voltage.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 2 May 2017 06:30:39 +0000 (14:30 +0800)]
drm/amd/powerplay: Allow duplicate enteries in pptable.
This is a valid configuration.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 2 May 2017 09:11:29 +0000 (17:11 +0800)]
drm/amd/powerplay: set fan target temperature by msg on vega10.
SMU not support FanTargetTemperature in pptable,
so send msg instand.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 2 May 2017 08:51:49 +0000 (16:51 +0800)]
drm/amd/powerplay: set soc floor voltage on boot on vega10.
Send the VBIOS bootup VDDC as a SOC floor voltage to SMU
before populating the PPTABLE. After DPM is enabled, This
floor voltage will be removed. This will prevent SMC from
going to Vmin upon receiving PPTable causing a violation.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 2 May 2017 08:01:00 +0000 (16:01 +0800)]
drm/amd/powerplay: refine code in vega10_smumgr.c
1. return error code instand of -1.
2. print msg info if send msg failed
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shaoyun Liu [Fri, 28 Apr 2017 20:14:59 +0000 (16:14 -0400)]
drm/amdgpu: Reserve 0-2 invalidation reg sets for none-amdgpu usages
Firmware used reg set 2 for tlb invalidation. AMDGPU can start from reg
set 3 to avoid the conflict. AMDKFD will use the reg set 0 or 1 when
necesary.
Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewws-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 17 Apr 2017 21:34:42 +0000 (17:34 -0400)]
drm/amdgpu/gfx9: add additional MQD initialization
Need to properly set the ROQ space setting.
Reviewed-by: monk liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 17 Apr 2017 21:30:27 +0000 (17:30 -0400)]
drm/amdgpu/gfx9: fix typo in mpd init
Using the wrong macro for soc15 register access.
Reviewed-by: monk liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 1 May 2017 20:20:42 +0000 (16:20 -0400)]
drm/amdgpu/gfx9: use actual gpu num se setting for ngg allocation
Rather than using a hardcoded value.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 18 Apr 2017 15:32:15 +0000 (11:32 -0400)]
drm/amdgpu: update revision id settings for BR/ST
Add new RIDs.
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Xie <AlexBin.Xie@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Fri, 28 Apr 2017 20:32:43 +0000 (16:32 -0400)]
Revert "drm/amdgpu: Refactor flip into prepare submit and submit. (v3)"
This reverts commit
cb341a319f7e66f879d69af929c3dadfc1a8f31e.
The purpose of the refactor was for amdgpu_crtc_prepare/submit_flip to
be used by the DC code, but that's no longer the case.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Fri, 28 Apr 2017 08:28:14 +0000 (17:28 +0900)]
drm/amdgpu: Make amdgpu_bo_reserve use uninterruptible waits for cleanup
Some of these paths probably cannot be interrupted by a signal anyway.
Those that can would fail to clean up things if they actually got
interrupted.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 27 Apr 2017 07:48:56 +0000 (15:48 +0800)]
drm/amd/powerplay: implement stop dpm task for vega10.
Add functions to disable dpm for S3/S4.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 28 Apr 2017 04:54:26 +0000 (12:54 +0800)]
drm/amd/powerplay: complete disable_smc_firmware_ctf_tasks.
Disable ctf in eventmgr to fix S3/S4 support.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 27 Apr 2017 07:46:35 +0000 (15:46 +0800)]
drm/amd/powerplay: add disable_smc_ctf callback in hwmgr.
export disablesmcctf to eventmgr.
need to disable temperature alert when s3/s4.
otherwise, when resume back,enable temperature
alert will fail.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 27 Apr 2017 07:13:52 +0000 (15:13 +0800)]
drm/amdgpu: fix deadlock of reservation between cs and gpu reset v2
the case could happen when gpu reset:
1. when gpu reset, cs can be continue until sw queue is full, then push job will wait with holding pd reservation.
2. gpu_reset routine will also need pd reservation to restore page table from their shadow.
3. cs is waiting for gpu_reset complete, but gpu reset is waiting for cs releases reservation.
v2: handle amdgpu_cs_submit error path.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Junwei Zhang [Thu, 27 Apr 2017 08:27:43 +0000 (16:27 +0800)]
drm/amdgpu: bump version for exporting gpu info for gfx9
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Junwei Zhang [Thu, 27 Apr 2017 03:12:07 +0000 (11:12 +0800)]
drm/amdgpu: export more gpu info for gfx9
v2: 64-bit aligned for gpu info
v3: squash in wave_front_fix
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Qiang Yu <Qiang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 27 Apr 2017 15:13:39 +0000 (17:13 +0200)]
drm/amdgpu: remove unused and mostly unimplemented CGS functions v2
Those functions are all unused and some not even implemented.
v2: keep cgs_get_pci_resource, it is used by the ACP driver.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 21 Apr 2017 10:52:12 +0000 (18:52 +0800)]
drm/amd/powerplay: refine set pcie dpm default table on vega10.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 21 Apr 2017 10:33:05 +0000 (18:33 +0800)]
drm/amd/powerplay: disable cks by default on vega10.
run gpu test auto reboot when enable cks right now.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 21 Apr 2017 09:26:07 +0000 (17:26 +0800)]
drm/amd/powerplay: correct UlvOffsetVid on Vega10.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Tue, 25 Apr 2017 21:09:24 +0000 (17:09 -0400)]
drm/amdgpu: Fix use of interruptible waiting
There is no good mechanism to handle the corresponding error.
When signal interrupt happens, unpin is not called.
As a result, inside AMDGPU, the statistic of pin size will be wrong.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Wed, 26 Apr 2017 17:31:01 +0000 (13:31 -0400)]
drm/amdgpu: Fix use of interruptible waiting
Either in cgs functions or for callers of cgs functions:
1. The signal interrupt can affect the expected behaviour
2. There is no good mechanism to handle the corresponding error
3. There is no chance of deadlock in these single BO waiting
4. There is no clear benefit for interruptible waiting
5. Future caller of these functions might have same issue.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Mon, 24 Apr 2017 09:39:00 +0000 (17:39 +0800)]
drm/amdgpu: fix NULL pointer error
[ 141.420491] BUG: unable to handle kernel NULL pointer dereference at
0000000000000030
[ 141.420532] IP: [<
ffffffff81579ee1>] fence_remove_callback+0x11/0x60
[ 141.420563] PGD
20a030067
[ 141.420575] PUD
2088ca067
[ 141.420587] PMD 0
[ 141.420599] Oops: 0000 [#1] SMP
[ 141.420612] Modules linked in: amdgpu(OE) ttm(OE) drm_kms_helper(E) drm(E) i2c_algo_bit(E) fb_sys_fops(E) syscopyarea(E) sysfillrect(E) sysimgblt(E) rpcsec_gss_krb5(E) nfsv4(E) nfs(E) fscache(E) eeepc_wmi(E) asus_wmi(E) sparse_keymap(E) snd_hda_codec_realtek(E) video(E) snd_hda_codec_generic(E) snd_hda_codec_hdmi(E) snd_hda_intel(E) joydev(E) snd_hda_codec(E) snd_seq_midi(E) snd_seq_midi_event(E) snd_hda_core(E) snd_hwdep(E) snd_rawmidi(E) snd_pcm(E) kvm(E) irqbypass(E) crct10dif_pclmul(E) snd_seq(E) crc32_pclmul(E) ghash_clmulni_intel(E) snd_seq_device(E) snd_timer(E) aesni_intel(E) aes_x86_64(E) lrw(E) gf128mul(E) glue_helper(E) ablk_helper(E) cryptd(E) snd(E) soundcore(E) serio_raw(E) shpchp(E) i2c_piix4(E) i2c_designware_platform(E) 8250_dw(E) i2c_designware_core(E) mac_hid(E) binfmt_misc(E)
[ 141.420948] nfsd(E) auth_rpcgss(E) nfs_acl(E) lockd(E) grace(E) sunrpc(E) parport_pc(E) ppdev(E) lp(E) parport(E) autofs4(E) hid_generic(E) usbhid(E) hid(E) psmouse(E) r8169(E) ahci(E) mii(E) libahci(E) wmi(E)
[ 141.421042] CPU: 14 PID: 223 Comm: kworker/14:2 Tainted: G OE 4.9.0-custom #4
[ 141.421074] Hardware name: System manufacturer System Product Name/PRIME B350-PLUS, BIOS 0606 04/06/2017
[ 141.421146] Workqueue: events amd_sched_job_timedout [amdgpu]
[ 141.421169] task:
ffff88020b03ba80 task.stack:
ffffc900016f4000
[ 141.421193] RIP: 0010:[<
ffffffff81579ee1>] [<
ffffffff81579ee1>] fence_remove_callback+0x11/0x60
[ 141.421229] RSP: 0018:
ffffc900016f7d30 EFLAGS:
00010202
[ 141.421250] RAX:
ffff8801c049fc00 RBX:
ffff8801d4d8dc00 RCX:
0000000000000000
[ 141.421278] RDX:
0000000000000001 RSI:
ffff8801c049fcc0 RDI:
0000000000000000
[ 141.421307] RBP:
ffffc900016f7d48 R08:
0000000000000000 R09:
0000000000000000
[ 141.421334] R10:
00000020ed512a30 R11:
0000000000000001 R12:
0000000000000000
[ 141.421362] R13:
ffff880209ba4ba0 R14:
ffff880209ba4c58 R15:
ffff8801c055cc60
[ 141.421390] FS:
0000000000000000(0000) GS:
ffff88021ef80000(0000) knlGS:
0000000000000000
[ 141.421421] CS: 0010 DS: 0000 ES: 0000 CR0:
0000000080050033
[ 141.421443] CR2:
0000000000000030 CR3:
000000020b554000 CR4:
00000000003406e0
[ 141.421471] Stack:
[ 141.421480]
ffff8801d4d8dc00 ffff880209ba4c48 ffff880209ba4ba0 ffffc900016f7d78
[ 141.421513]
ffffffffa0697920 ffff880209ba0000 0000000000000000 ffff880209ba2770
[ 141.421549]
ffff880209ba4b08 ffffc900016f7df0 ffffffffa05ce2ae ffffffffa0509eb7
[ 141.421583] Call Trace:
[ 141.421628] [<
ffffffffa0697920>] amd_sched_hw_job_reset+0x50/0xb0 [amdgpu]
[ 141.421676] [<
ffffffffa05ce2ae>] amdgpu_gpu_reset+0x8e/0x690 [amdgpu]
[ 141.421712] [<
ffffffffa0509eb7>] ? drm_printk+0x97/0xa0 [drm]
[ 141.421770] [<
ffffffffa0698156>] amdgpu_job_timedout+0x46/0x50 [amdgpu]
[ 141.421829] [<
ffffffffa0696a07>] amd_sched_job_timedout+0x17/0x20 [amdgpu]
[ 141.421859] [<
ffffffff81095493>] process_one_work+0x153/0x3f0
[ 141.421884] [<
ffffffff81095c5b>] worker_thread+0x12b/0x4b0
[ 141.421907] [<
ffffffff81095b30>] ? rescuer_thread+0x350/0x350
[ 141.421931] [<
ffffffff8109b423>] kthread+0xd3/0xf0
[ 141.421951] [<
ffffffff8109b350>] ? kthread_park+0x60/0x60
[ 141.421975] [<
ffffffff817e1ee5>] ret_from_fork+0x25/0x30
[ 141.421996] Code: ac 81 e8 a3 1f b0 ff 48 c7 c0 ea ff ff ff e9 48 ff ff ff 0f 1f 80 00 00 00 00 0f 1f 44 00 00 55 48 89 e5 41 55 41 54 49 89 fc 53 <48> 8b 7f 30 48 89 f3 e8 73 7c 26 00 48 8b 13 48 39 d3 41 0f 95
[ 141.422156] RIP [<
ffffffff81579ee1>] fence_remove_callback+0x11/0x60
[ 141.422183] RSP <
ffffc900016f7d30>
[ 141.422197] CR2:
0000000000000030
[ 141.433483] ---[ end trace
bc0949bf7ddd6d4b ]---
if the job is reset twice, then the parent could be NULL.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roger.He [Fri, 21 Apr 2017 05:08:43 +0000 (13:08 +0800)]
drm/amdgpu: validate shadow before restoring from it
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Roger.He <Hongbo.He@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Mon, 24 Apr 2017 19:33:16 +0000 (15:33 -0400)]
drm/amdgpu: Fix use of interruptible waiting
1. The signal interrupt can affect the expected behaviour.
2. There is no good mechanism to handle the corresponding error.
When signal interrupt happens, unpin is not called.
As a result, inside AMDGPU, the statistic of pin size will be wrong.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Mon, 24 Apr 2017 19:26:57 +0000 (15:26 -0400)]
drm/amdgpu: Real return value can be over-written when clean up
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Mon, 24 Apr 2017 18:27:00 +0000 (14:27 -0400)]
drm/amdgpu: Fix use of interruptible waiting
1. The signal interrupt can affect the expected behaviour.
2. There is no good mechanism to handle the corresponding error.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Mon, 24 Apr 2017 17:53:04 +0000 (13:53 -0400)]
drm/amdgpu: Fix use of interruptible waiting
1. The signal interrupt can affect the expected behaviour.
2. There is no good mechanism to handle the corresponding error.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Mon, 24 Apr 2017 17:52:41 +0000 (13:52 -0400)]
drm/amdgpu: Fix use of interruptible waiting
1. The signal interrupt can affect the expected behaviour.
2. There is no mechanism to handle the corresponding error.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Mon, 24 Apr 2017 17:30:43 +0000 (13:30 -0400)]
drm/amdgpu: Fix use of interruptible waiting
If amdgpu_bo_reserve function is interrupted by signal,
amdgpu_bo_kunmap function is not called.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Sun, 23 Apr 2017 23:33:09 +0000 (01:33 +0200)]
drm/radeon: Make display watermark calculations more accurate
Avoid big roundoff errors in scanline/hactive durations for
high pixel clocks, especially for >= 500 Mhz, and thereby
program more accurate display fifo watermarks.
This is a port of the corresponding amdgpu patch.
Implemented for DCE 4,6,8.
Tested on Evergreen/DCE-4 with Radeon HD-5770.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Sun, 23 Apr 2017 23:33:08 +0000 (01:33 +0200)]
drm/radeon: Avoid overflows/divide-by-zero in latency_watermark calculations.
At dot clocks > approx. 250 Mhz, some of these calcs will overflow and
cause miscalculation of latency watermarks, and for some overflows also
divide-by-zero driver crash. Make calcs more overflow resistant.
This is a direct port of the corresponding patch from amdgpu-kms,
copy-paste for cik from dce-8 and si from dce-6, with a slightly
simpler variant for evergreen dce-4/5.
Only tested on DCE-4 evergreen with a Radeon HD-5770.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Sun, 23 Apr 2017 23:02:46 +0000 (01:02 +0200)]
drm/amdgpu: Add missing lb_vblank_lead_lines setup to DCE-6 path.
This apparently got lost when implementing the new DCE-6 support
and would cause failures in pageflip scheduling and timestamping.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Pan Bian [Mon, 24 Apr 2017 08:45:51 +0000 (16:45 +0800)]
drm/radeon: check return value of radeon_fence_emit
Function radeon_fence_emit() returns -ENOMEM if there is no enough
memory. And in this case, function radeon_ring_unlock_undo() rather than
function radeon_ring_unlock_commit() should be called. However, in
function radeon_test_create_and_emit_fence(), the return value of
radeon_fence_emit() is ignored. This patch adds the check.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Pan Bian <bianpan2016@163.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Pan Bian [Mon, 24 Apr 2017 08:38:05 +0000 (16:38 +0800)]
drm/radeon: check return value of radeon_ring_lock
Function radeon_ring_lock() returns an errno on failure, and its return
value should be validated. However, in functions r420_cp_errata_init()
and r420_cp_errata_fini(), its return value is not checked. This patch
adds the checks.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Pan Bian <bianpan2016@163.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Mon, 17 Apr 2017 03:19:45 +0000 (11:19 +0800)]
drm/amdgpu/soc15: enable UVD code path for sriov
Enable UVD block for SRIOV.
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Mon, 17 Apr 2017 03:51:44 +0000 (11:51 +0800)]
drm/amdgpu/uvd7: add UVD hw init sequences for sriov
Add UVD hw init.
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Mon, 17 Apr 2017 03:45:35 +0000 (11:45 +0800)]
drm/amdgpu/uvd7: add uvd doorbell initialization for sriov
Add UVD doorbell for SRIOV.
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Mon, 17 Apr 2017 03:28:12 +0000 (11:28 +0800)]
drm/amdgpu/uvd7: add sriov uvd initialization sequences
Add UVD initialization for SRIOV.
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Fri, 21 Apr 2017 08:21:41 +0000 (16:21 +0800)]
drm/amdgpu/vce4: replaced with virt_alloc_mm_table
Used virt_alloc_mm_table function to allocate MM table memory.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Fri, 21 Apr 2017 07:40:25 +0000 (15:40 +0800)]
drm/amdgpu/virt: add two functions for MM table
Add two functions to allocate & free MM table memory.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Sun, 16 Apr 2017 05:37:07 +0000 (13:37 +0800)]
drm/amdgpu/vce4: move mm table constructions functions into mmsch header file
Move mm table construction functions into mmsch header file so that
UVD can reuse it.
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Daniel Wang [Wed, 19 Apr 2017 08:09:08 +0000 (16:09 +0800)]
drm/amdgpu/vce4: fix a PSP loading VCE issue
Fixed PSP loading issue for sriov.
Signed-off-by: Daniel Wang <Daniel.Wang2@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Daniel Wang [Thu, 20 Apr 2017 03:45:09 +0000 (11:45 +0800)]
drm/amdgpu/psp: skip loading SDMA/RLCG under SRIOV VF
Now GPU hypervisor will load SDMA and RLCG ucode, so skip it
in guest.
Signed-off-by: Daniel Wang <Daniel.Wang2@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Mon, 24 Apr 2017 09:09:15 +0000 (17:09 +0800)]
drm/amdgpu: fix gpu reset crash
[ 413.687439] BUG: unable to handle kernel NULL pointer dereference at
0000000000000548
[ 413.687479] IP: [<
ffffffff8109b175>] to_live_kthread+0x5/0x60
[ 413.687507] PGD
1efd12067
[ 413.687519] PUD
1efd11067
[ 413.687531] PMD 0
[ 413.687543] Oops: 0000 [#1] SMP
[ 413.687557] Modules linked in: amdgpu(OE) ttm(OE) drm_kms_helper(E) drm(E) i2c_algo_bit(E) fb_sys_fops(E) syscopyarea(E) sysfillrect(E) sysimgblt(E) rpcsec_gss_krb5(E) nfsv4(E) nfs(E) fscache(E) snd_hda_codec_realtek(E) snd_hda_codec_generic(E) snd_hda_codec_hdmi(E) snd_hda_intel(E) eeepc_wmi(E) snd_hda_codec(E) asus_wmi(E) snd_hda_core(E) sparse_keymap(E) snd_hwdep(E) video(E) snd_pcm(E) snd_seq_midi(E) joydev(E) snd_seq_midi_event(E) snd_rawmidi(E) snd_seq(E) snd_seq_device(E) snd_timer(E) kvm(E) irqbypass(E) crct10dif_pclmul(E) snd(E) crc32_pclmul(E) ghash_clmulni_intel(E) soundcore(E) aesni_intel(E) aes_x86_64(E) lrw(E) gf128mul(E) glue_helper(E) ablk_helper(E) cryptd(E) shpchp(E) serio_raw(E) i2c_piix4(E) 8250_dw(E) i2c_designware_platform(E) i2c_designware_core(E) mac_hid(E) binfmt_misc(E)
[ 413.687894] parport_pc(E) ppdev(E) lp(E) parport(E) nfsd(E) auth_rpcgss(E) nfs_acl(E) lockd(E) grace(E) sunrpc(E) autofs4(E) hid_generic(E) usbhid(E) hid(E) psmouse(E) ahci(E) r8169(E) mii(E) libahci(E) wmi(E)
[ 413.687989] CPU: 13 PID: 1134 Comm: kworker/13:2 Tainted: G OE 4.9.0-custom #4
[ 413.688019] Hardware name: System manufacturer System Product Name/PRIME B350-PLUS, BIOS 0606 04/06/2017
[ 413.688089] Workqueue: events amd_sched_job_timedout [amdgpu]
[ 413.688116] task:
ffff88020f9657c0 task.stack:
ffffc90001a88000
[ 413.688139] RIP: 0010:[<
ffffffff8109b175>] [<
ffffffff8109b175>] to_live_kthread+0x5/0x60
[ 413.688171] RSP: 0018:
ffffc90001a8bd60 EFLAGS:
00010282
[ 413.688191] RAX:
ffff88020f0073f8 RBX:
ffff88020f000000 RCX:
0000000000000000
[ 413.688217] RDX:
0000000000000001 RSI:
ffff88020f9670c0 RDI:
0000000000000000
[ 413.688243] RBP:
ffffc90001a8bd78 R08:
0000000000000000 R09:
0000000000001000
[ 413.688269] R10:
0000006051b11a82 R11:
0000000000000001 R12:
0000000000000000
[ 413.688295] R13:
ffff88020f002770 R14:
ffff88020f004838 R15:
ffff8801b23c2c60
[ 413.688321] FS:
0000000000000000(0000) GS:
ffff88021ef40000(0000) knlGS:
0000000000000000
[ 413.688352] CS: 0010 DS: 0000 ES: 0000 CR0:
0000000080050033
[ 413.688373] CR2:
0000000000000548 CR3:
00000001efd0f000 CR4:
00000000003406e0
[ 413.688399] Stack:
[ 413.688407]
ffffffff8109b304 ffff88020f000000 0000000000000070 ffffc90001a8bdf0
[ 413.688439]
ffffffffa05ce29d ffffffffa052feb7 ffffffffa07b5820 ffffc90001a8bda0
[ 413.688470]
ffffffff00000018 ffff8801bb88f060 0000000001a8bdb8 ffff88021ef59280
[ 413.688502] Call Trace:
[ 413.688514] [<
ffffffff8109b304>] ? kthread_park+0x14/0x60
[ 413.688555] [<
ffffffffa05ce29d>] amdgpu_gpu_reset+0x7d/0x670 [amdgpu]
[ 413.688589] [<
ffffffffa052feb7>] ? drm_printk+0x97/0xa0 [drm]
[ 413.688643] [<
ffffffffa0698136>] amdgpu_job_timedout+0x46/0x50 [amdgpu]
[ 413.688700] [<
ffffffffa06969e7>] amd_sched_job_timedout+0x17/0x20 [amdgpu]
[ 413.688727] [<
ffffffff81095493>] process_one_work+0x153/0x3f0
[ 413.688751] [<
ffffffff81095c5b>] worker_thread+0x12b/0x4b0
[ 413.688773] [<
ffffffff8100392e>] ? do_syscall_64+0x6e/0x180
[ 413.688795] [<
ffffffff81095b30>] ? rescuer_thread+0x350/0x350
[ 413.688818] [<
ffffffff8100392e>] ? do_syscall_64+0x6e/0x180
[ 413.688839] [<
ffffffff8109b423>] kthread+0xd3/0xf0
[ 413.688858] [<
ffffffff8109b350>] ? kthread_park+0x60/0x60
[ 413.688881] [<
ffffffff817e1ee5>] ret_from_fork+0x25/0x30
[ 413.688901] Code: 25 40 d3 00 00 48 8b 80 48 05 00 00 48 89 e5 5d 48 8b 40 c8 48 c1 e8 02 83 e0 01 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 <48> 8b b7 48 05 00 00 55 48 89 e5 48 85 f6 74 31 8b 97 f8 18 00
[ 413.689045] RIP [<
ffffffff8109b175>] to_live_kthread+0x5/0x60
[ 413.689064] RSP <
ffffc90001a8bd60>
[ 413.689076] CR2:
0000000000000548
[ 413.697985] ---[ end trace
0a314a64821f84e9 ]---
The root cause is some ring doesn't have scheduler, like KIQ ring
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Fri, 21 Apr 2017 09:58:42 +0000 (17:58 +0800)]
drm/amdgpu: fix no-vmid job
[ 132.036658] amdgpu 0000:22:00.0: VM IB without ID
[ 132.036709] [drm:amdgpu_job_run [amdgpu]] *ERROR* Error scheduling IBs (-22)
[ 132.036755] [drm:amd_sched_main [amdgpu]] *ERROR* Failed to run job!
root cause is fence is signaled during sync transfer.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roger.He [Fri, 21 Apr 2017 06:24:26 +0000 (14:24 +0800)]
drm/amdgpu: fix indent
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Roger.He <Hongbo.He@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Fri, 21 Apr 2017 08:40:00 +0000 (16:40 +0800)]
drm/amdgpu: increase gtt size to 3GB by default v2
v2: address Alex's comment, add AMDGPU_DEFAULT_GTT_SIZE_MB.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 21 Apr 2017 08:05:56 +0000 (10:05 +0200)]
drm/amdgpu: fix VM clearing in amdgpu_gem_object_close
We need to check if the VM is swapped out before trying to update it.
Fixes:
23e0563e48f7 ("drm/amdgpu: clear freed mappings immediately when BO may be freed")
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chunming Zhou [Thu, 13 Apr 2017 08:16:51 +0000 (16:16 +0800)]
drm/amdgpu: add gtt print like vram when dump mm table V2
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 20 Apr 2017 10:11:47 +0000 (12:11 +0200)]
drm/amdgpu: fix amdgpu_ttm_bo_eviction_valuable
BOs not mapped into the GART are always valuable for an eviction. Otherwise we
don't correctly swap them out on VRAM evictions during memory pressure.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 20 Apr 2017 08:33:23 +0000 (16:33 +0800)]
drm/amd/powerplay: Fix AVFS param.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 19 Apr 2017 08:00:21 +0000 (16:00 +0800)]
drm/amd/powerplay: enable clock stretch feature on Vega10.
Correctly calculate CKSVidOffset
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 20 Apr 2017 08:38:36 +0000 (16:38 +0800)]
drm/amd/powerplay: enable pcie dpm on Vega10.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 12 Apr 2017 09:52:07 +0000 (17:52 +0800)]
drm/amd/powerplay: allocate fb for avfs fuse table on vega10.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 12 Apr 2017 09:32:35 +0000 (17:32 +0800)]
drm/amd/powerplay: enable AGM logging while dpm disabled.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 20 Apr 2017 07:25:39 +0000 (15:25 +0800)]
drm/amd/powerplay: add error message to remind user updating firmware
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 24 Apr 2017 17:51:52 +0000 (13:51 -0400)]
Revert "drm/amd/amdgpu: Set VCE/UVD off during late init"
This leads to hangs on init.
This reverts commit
d1aff8ec49c3ece05cee9b6e63d44e96a420b068.
Zhang, Jerry [Wed, 19 Apr 2017 01:53:29 +0000 (09:53 +0800)]
drm/amdgpu: PRT support for gfx9 (v3)
Fix PRT handling on gfx9
v2: unify PRT bit for all ASICs
v3: move PRT flag checking in amdgpu_vm_bo_split_mapping()
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Acked-by: David Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 19 Apr 2017 12:41:19 +0000 (14:41 +0200)]
drm/amdgpu: fix amdgpu_vm_clear_freed v2
Use amdgpu_vm_bo_update_mapping() instead of amdgpu_vm_bo_split_mapping() here.
We don't want any flags set in the cleared areas and splitting
shouldn't be necessary.
v2: fix typo in commit message
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Trigger Huang [Mon, 17 Apr 2017 12:50:18 +0000 (08:50 -0400)]
drm/amdgpu: Destroy psp ring in hw_fini
Fix issue that PSP initialization will fail if reload amdgpu module.
That's because the PSP ring must be destroyed to be ready for the
next time PSP initialization.
Changes in v2:
- Move psp_ring_destroy before all BOs free (suggested by
Ray Huang).
Changes in v3:
- Check firmware load type, if it is not PSP, we should do
nothing in fw_fini(), and of course will not destroy
PSP ring too (suggested by Ray Huang).
Signed-off-by: Trigger Huang <trigger.huang@amd.com>
Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 12 Apr 2017 09:34:26 +0000 (17:34 +0800)]
drm/amdgpu: update smu9 driver interface
Updated interface between the driver and the SMU controller.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 19 Apr 2017 15:03:04 +0000 (11:03 -0400)]
drm/amd/amdgpu: Print out ring name in dev_info
So it's more obvious which rings are using which INV engines.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 19 Apr 2017 13:02:41 +0000 (09:02 -0400)]
drm/amd/amdgpu: Change comp GFXv9 ring name to remove space
umr expects the ring name to be a complete word. This also
makes it consistent with GFXv7/8.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 19 Apr 2017 13:01:42 +0000 (09:01 -0400)]
drm/amd/amdgpu: Change comp GFXv6 ring name to remove space
umr expects the ring name to be a complete word. This also
makes it consistent with GFXv7/8.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Trigger Huang [Mon, 17 Apr 2017 14:56:02 +0000 (10:56 -0400)]
drm/amdgpu: Fix module unload hang by KIQ on Vega10
Apply commit
4e683cb2644f ("drm/amdgpu: Fix module unload hang by
KIQ IRQ set")to vega10
V2:
delete reduant kiq irq funcs type check (suggested by Rex.Zhu)
Signed-off-by: Trigger Huang <trigger.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 18 Apr 2017 11:21:44 +0000 (19:21 +0800)]
drm/amdgpu: fix memory clock can't switch on CI.
if we set only lowest mclk level enabled,
when we enable uvd dpm during boot time,
mclk will be fixed in the lowest level.
the mclk switch will fail if try to enable
other level of mclk at this time.
so set all mclk levels enabled.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Fri, 14 Apr 2017 09:43:02 +0000 (17:43 +0800)]
drm/amdgpu/gfx9: bypass clockgating setting
For SRIOV doesn't need clockgating, bypass it.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Fri, 14 Apr 2017 09:40:57 +0000 (17:40 +0800)]
drm/amdgpu/mmhub_v1: bypass clockgating setting
For SRIOV doesn't need CG, so bypass it.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 6 Mar 2017 12:34:57 +0000 (13:34 +0100)]
drm/amdgpu: fix coding style and printing in amdgpu_doorbell_init
Based on commit "drm/radeon: remove useless and potentially wrong message".
The size of the info printing is incorrect and the PCI subsystems prints
the same info on boot anyway.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Pixel Ding [Thu, 23 Feb 2017 03:10:33 +0000 (11:10 +0800)]
drm/amdgpu/virt: don't check VALID bit for FLR completion message
The interrupt after FLR is missed sometimes due to hardware reason, so
guest driver get the notification of FLR completion via polling
message. Then host doesn't write VALID bit to avoid sending interrupt,
otherwise the completion will be handled twice.
So there's a valid message without VALID bit for FLR completion,
driver should handle it without checking.
Signed-off-by: Pixel Ding <Pixel.Ding@amd.com>
Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Junwei Zhang [Thu, 23 Feb 2017 03:01:40 +0000 (11:01 +0800)]
drm/amdgpu: fix double_offchip_lds_buf for gfx v6
Was incorrect for SI.
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Rex Zhu [Mon, 17 Apr 2017 12:46:29 +0000 (20:46 +0800)]
drm/amd/powerplay: delete dead functions in vega10.
Vega10 does not support AVFS BTC, remove function.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 17 Apr 2017 11:44:23 +0000 (19:44 +0800)]
drm/amd/amdgpu: coding style refine in sdma_v4_0.c
Replace 8 spaces with tabs.
correct {} braces, etc.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 17 Apr 2017 10:46:57 +0000 (18:46 +0800)]
drm/amdgpu: Remove redundant itermediate return val in sdma_v4_0.c
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Mon, 17 Apr 2017 07:32:52 +0000 (15:32 +0800)]
drm/ttm: cleanup unuse ret value
The ret must be 0 here, otherwise, the function will return after init_mem_type.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 14 Apr 2017 02:50:03 +0000 (10:50 +0800)]
drm/amdgpu: fix to print incorrect wptr address
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 13 Apr 2017 08:12:26 +0000 (16:12 +0800)]
drm/amdgpu: fix dead lock if any ip block resume failed in s3
Driver must free the console lock whether driver resuming successful
or not. Otherwise, fb_console will be always waiting for the lock and
then cause system stuck.
[ 244.405541] INFO: task kworker/0:0:4 blocked for more than 120 seconds.
[ 244.405543] Tainted: G OE 4.9.0-custom #1
[ 244.405544] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[ 244.405541] INFO: task kworker/0:0:4 blocked for more than 120 seconds.
[ 244.405543] Tainted: G OE 4.9.0-custom #1
[ 244.405544] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[ 244.405550] kworker/0:0 D 0 4 2 0x00080000
[ 244.405559] Workqueue: events console_callback
[ 244.405564]
ffff88045a2cfc00 0000000000000000 ffff880462b75940 ffffffff81c0e500
[ 244.405568]
ffff880476419280 ffffc900018f7c90 ffffffff817dcf62 000000000000003c
[ 244.405572]
0000000100000000 0000000000000002 ffff880462b75940 ffff880462b75940
[ 244.405573] Call Trace:
[ 244.405580] [<
ffffffff817dcf62>] ? __schedule+0x222/0x6a0
[ 244.405584] [<
ffffffff817dd416>] schedule+0x36/0x80
[ 244.405588] [<
ffffffff817e041c>] schedule_timeout+0x1fc/0x390
[ 244.405592] [<
ffffffff817df1b4>] __down_common+0xa5/0xf8
[ 244.405598] [<
ffffffff810b2ca8>] ? put_prev_entity+0x48/0x710
[ 244.405601] [<
ffffffff817df224>] __down+0x1d/0x1f
[ 244.405606] [<
ffffffff810c71a1>] down+0x41/0x50
[ 244.405611] [<
ffffffff810d380a>] console_lock+0x1a/0x40
[ 244.405614] [<
ffffffff814e3c03>] console_callback+0x13/0x160
[ 244.405617] [<
ffffffff817dcf6a>] ? __schedule+0x22a/0x6a0
[ 244.405623] [<
ffffffff810954e3>] process_one_work+0x153/0x3f0
[ 244.405628] [<
ffffffff81095cab>] worker_thread+0x12b/0x4b0
[ 244.405633] [<
ffffffff81095b80>] ? rescuer_thread+0x350/0x350
[ 244.405637] [<
ffffffff8109b473>] kthread+0xd3/0xf0
[ 244.405641] [<
ffffffff8109b3a0>] ? kthread_park+0x60/0x60
[ 244.405645] [<
ffffffff8109b3a0>] ? kthread_park+0x60/0x60
[ 244.405649] [<
ffffffff817e1ee5>] ret_from_fork+0x25/0x30
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 11 Apr 2017 17:20:20 +0000 (19:20 +0200)]
drm/radeon: force the UVD DPB into VRAM as well
Seems to be mandatory for WMV playback.
Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=100510
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 10 Apr 2017 19:36:32 +0000 (15:36 -0400)]
drm/amdgpu: bump version number to note race fix and new fence functionality
fixed in: "drm/amdgpu:fix race condition"
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 10 Apr 2017 19:32:43 +0000 (15:32 -0400)]
drm/amdgpu: fix spelling in header comment
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 7 Apr 2017 15:43:19 +0000 (17:43 +0200)]
drm/amdgpu: trace vm hub during flush as well v2
Trace on which hub we are doing the flush.
v2: fix typo in commit message
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 7 Apr 2017 13:31:13 +0000 (15:31 +0200)]
drm/amdgpu: trace the vmhub in grab_id as well
Trace on which VMHUB we assigned an VMID.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 30 Mar 2017 14:56:20 +0000 (16:56 +0200)]
drm/amdgpu: allow concurrent VM flushes
Enable concurrent VM flushes for Vega10.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 31 Mar 2017 09:03:50 +0000 (11:03 +0200)]
drm/amdgpu: assign VM invalidation engine manually v2
For Vega10 we have 18 VM invalidation engines for each VMHUB.
Start to assign them manually to the rings.
v2: add a BUG_ON if we use to many engines
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 30 Mar 2017 14:50:47 +0000 (16:50 +0200)]
drm/amdgpu: invalidate only the currently needed VMHUB v2
Drop invalidating both hubs from each engine.
v2: don't use hardcoded values
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 6 Apr 2017 15:52:39 +0000 (17:52 +0200)]
drm/amdgpu: split VMID management by VMHUB
This way GFX and MM won't fight for VMIDs any more.
Initially disabled since we need to stop flushing all HUBS
at the same time as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 6 Apr 2017 13:18:21 +0000 (15:18 +0200)]
drm/amdgpu: drop VMID per ring tracking
David suggested this a long time ago, instead of checking
each ring just walk over all the VMIDs in reverse LRU order.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 30 Mar 2017 12:49:50 +0000 (14:49 +0200)]
drm/amdgpu: add VMHUB to ring association
Add the info which ring belonging to which VMHUB.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Thu, 6 Apr 2017 06:46:50 +0000 (14:46 +0800)]
drm/amdgpu/vce4: enable ring & ib test for sriov
Now VCE block can work for SRIOV, enable ring & ib test.
Signed-off-by: Frank Min <Frank.Min@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiangliang Yu [Thu, 6 Apr 2017 06:43:48 +0000 (14:43 +0800)]
drm/amdgpu/vce4: workaround VCE ring test slow issue
Add VCE ring test slow workaround for SRIOV.
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Fri, 7 Apr 2017 02:38:52 +0000 (10:38 +0800)]
drm/amdgpu/vce4: update VCE initialization sequence for SRIOV
Update the initialization sequence of VCE to make VCE work.
Signed-off-by: Frank Min <Frank.Min@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>