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Ian Romanick [Thu, 28 Feb 2019 04:15:32 +0000 (20:15 -0800)]
nir/algebraic: Add missing 16-bit extract_[iu]8 patterns
No shader-db changes on any Intel platform.
v2: Use a loop to generate patterns. Suggested by Jason.
v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would
replace an extract_i8 with and extract_u8. This broke ~180 tests. This
bug was introduced in v2.
Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> [v2]
Acked-by: Jason Ekstrand <jason@jlekstrand.net> [v2]
Ian Romanick [Thu, 28 Feb 2019 04:12:46 +0000 (20:12 -0800)]
nir/algebraic: Add missing 64-bit extract_[iu]8 patterns
No shader-db changes on any Intel platform.
v2: Use a loop to generate patterns. Suggested by Jason.
v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would
replace an extract_i8 with and extract_u8. This broke ~180 tests. This
bug was introduced in v2.
Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> [v2]
Acked-by: Jason Ekstrand <jason@jlekstrand.net> [v2]
Ian Romanick [Thu, 28 Feb 2019 04:08:38 +0000 (20:08 -0800)]
nir/algebraic: Remove redundant extract_[iu]8 patterns
No shader-db changes on any Intel platform.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Ian Romanick [Thu, 28 Feb 2019 03:52:12 +0000 (19:52 -0800)]
nir/algebraic: Fix up extract_[iu]8 after loop unrolling
Skylake, Broadwell, and Haswell had similar results. (Skylake shown)
total instructions in shared programs:
15256840 ->
15256837 (<.01%)
instructions in affected programs: 4713 -> 4710 (-0.06%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.06% max: 0.08% x̄: 0.06% x̃: 0.06%
total cycles in shared programs:
372286583 ->
372286583 (0.00%)
cycles in affected programs: 198516 -> 198516 (0.00%)
helped: 1
HURT: 1
helped stats (abs) min: 10 max: 10 x̄: 10.00 x̃: 10
helped stats (rel) min: <.01% max: <.01% x̄: <.01% x̃: <.01%
HURT stats (abs) min: 10 max: 10 x̄: 10.00 x̃: 10
HURT stats (rel) min: 0.01% max: 0.01% x̄: 0.01% x̃: 0.01%
No changes on any other Intel platform.
v2: Use a loop to generate patterns. Suggested by Jason.
v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would
replace an extract_i8 with and extract_u8. This broke ~180 tests. This
bug was introduced in v2.
Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> [v2]
Acked-by: Jason Ekstrand <jason@jlekstrand.net> [v2]
Dave Airlie [Fri, 8 Mar 2019 03:09:05 +0000 (13:09 +1000)]
nir/deref: fix struct wrapper casts. (v3)
llvm/spir-v spits out some struct a { struct b {} }, but it
doesn't deref, it casts (struct a) to (struct b), reconstruct
struct derefs instead of casts for these.
v2: use ssa_def_rewrite uses, rework the type restrictions (Jason)
v3: squish more stuff into one function, drop unused temp (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rafael Antognolli [Fri, 15 Feb 2019 23:43:12 +0000 (15:43 -0800)]
i965/blorp: Remove unused parameter from blorp_surf_for_miptree.
It seems pretty useless nowadays.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Anuj Phogat [Tue, 26 Mar 2019 22:46:24 +0000 (15:46 -0700)]
iris/icl: Add WA_2204188704 to disable pixel shader panic dispatch
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Tue, 26 Mar 2019 22:45:29 +0000 (15:45 -0700)]
iris/icl: Set Enabled Texel Offset Precision Fix bit
h/w specification requires this bit to be always set.
See Mesa commit
5eb173304bd.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rob Clark [Thu, 28 Mar 2019 17:33:30 +0000 (13:33 -0400)]
freedreno/ir3: align const size to vec4
This is no longer true since PIPE_CAP_PACKED_UNIFORMS was enabled.
Fixes:
3c8779af325 freedreno/ir3: Enable PIPE_CAP_PACKED_UNIFORMS
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 26 Mar 2019 19:21:12 +0000 (15:21 -0400)]
freedreno/ir3: reads/writes to unrelated arrays are not dependent
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 24 Mar 2019 15:16:12 +0000 (11:16 -0400)]
freedreno/ir3: sched fix
Not sure why new-style frag inputs start triggering this. But we
probably shouldn't consider src's from other blocks.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 26 Mar 2019 14:00:12 +0000 (10:00 -0400)]
freedreno/a6xx: small cleanup
Signed-off-by: Rob Clark <robdclark@gmail.com>
Kenneth Graunke [Tue, 19 Mar 2019 21:00:50 +0000 (14:00 -0700)]
iris: Fix blits with S8_UINT destination
For depth and stencil blits, we always want the main mask to be Z, and
the secondary pass mask to be S. If asked to blit Z+S to S, we should
handle the blit in the second pass which properly gets the stencil
resources.
Before, we were trying to handle S as the main mask, and accidentally
blitting a Z source to a S destination, which doesn't work out well.
Fixes Piglit's "framebuffer-blit-levels {draw,read} stencil" tests.
Kenneth Graunke [Mon, 11 Mar 2019 22:03:13 +0000 (15:03 -0700)]
st/mesa: Fix blitting from GL_DEPTH_STENCIL to GL_STENCIL_INDEX
Fixes assertion failures in Piglit's "framebuffer-blit-levels
{draw,read} stencil" tests on iris. Also fixes assert failures in
frameretrace, which tries to ReadPixels the stencil values (only)
from a Z24S8 depth/stencil attachment.
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Wed, 27 Mar 2019 22:31:49 +0000 (15:31 -0700)]
freedreno/ir3: Add workaround for VS samgq
This instruction needs a workaround when used from vertex shaders.
Fixes:
dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler2dshadow_vertex
dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler3d_fixed_vertex
dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler3d_float_vertex
dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler2dshadow_vertex
dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler3d_fixed_vertex
dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler3d_float_vertex
dEQP-GLES3.functional.shaders.texture_functions.textureprojgrad.sampler2dshadow_vertex
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Kristian H. Kristensen [Thu, 28 Mar 2019 06:05:01 +0000 (23:05 -0700)]
freedreno/ir3: Don't access beyond available regs
emit_cat5() needs to check if the last optional reg is there before it
accesses it.
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Eric Engestrom [Tue, 19 Mar 2019 14:36:30 +0000 (14:36 +0000)]
util/disk_cache: close fd in the fallback path
There are multiple `goto path_fail` with an open fd, but none that go to
`fail:` without going through `path_fail:` first, so let's just move the
`close(fd)` there.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Samuel Pitoiset [Thu, 28 Mar 2019 11:23:24 +0000 (12:23 +0100)]
radv: skip updating depth/color metadata for conditional rendering
I don't think we should update metadata when conditional rendering
is enabled. For some reasons, some CTS breaks only on SI.
This fixes the following CTS on SI:
dEQP-VK.conditional_rendering.draw_clear.clear.depth.*
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Thu, 28 Mar 2019 06:09:11 +0000 (23:09 -0700)]
st/nir: Free the GLSL IR after linking.
i965 does this, and st's tgsi path does this. st/nir did not.
Cuts 138MB of memory from a DiRT Rally trace, which is about 44%
of the total GLSL IR memory.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Thu, 21 Mar 2019 09:24:11 +0000 (10:24 +0100)]
radv: enable VK_AMD_gpu_shader_int16
This extension allows 16-bit support to Frexp/FrexpStruct.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 22 Mar 2019 13:48:38 +0000 (14:48 +0100)]
radv: do not lower frexp_exp and frexp_sig
Hardware has two instructions.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 22 Mar 2019 10:59:32 +0000 (11:59 +0100)]
ac: add ac_build_frex_exp() helper ans 16-bit/32-bit support
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 21 Mar 2019 14:47:04 +0000 (15:47 +0100)]
ac: add ac_build_frexp_mant() helper and 16-bit/32-bit support
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Tue, 26 Mar 2019 07:25:31 +0000 (00:25 -0700)]
iris: Actually advertise some modifiers
I neglected to fill out this driver function, causing us to advertise
0 modifiers. Now we advertise the various tilings and let the driver
pick them. I've verified that X tiling works with Weston (by hacking
the list to skip Y tiling).
Y+CCS doesn't work yet because it's multiplane and the Gallium dri
state tracker isn't really prepared for that. Leave it off for now.
Toni Lönnberg [Wed, 16 Jan 2019 11:55:25 +0000 (13:55 +0200)]
intel/genxml: Media instructions and structures for gen11
v2: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
- fix missing type
- fix *_FQM_*/*_QM_* commands
- shorten some media structs using groups
- factor out memory attributes
- switch MI_FLUSH_DW fields to bool
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Toni Lönnberg [Wed, 16 Jan 2019 11:55:08 +0000 (13:55 +0200)]
intel/genxml: Media instructions and structures for gen10
v2: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
- fix missing type
- fix *_FQM_*/*_QM_* commands
- shorten some media structs using groups
- factor out memory attributes
- switch MI_FLUSH_DW fields to bool
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Toni Lönnberg [Wed, 16 Jan 2019 11:54:46 +0000 (13:54 +0200)]
intel/genxml: Media instructions and structures for gen9
v2: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
- fix missing type
- fix *_FQM_*/*_QM_* commands
- shorten some media structs using groups
- factor out memory attributes
- switch MI_FLUSH_DW fields to bool
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Toni Lönnberg [Wed, 16 Jan 2019 11:54:25 +0000 (13:54 +0200)]
intel/genxml: Media instructions and structures for gen8
v2: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
- switch MI_FLUSH_DW fields to bool
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Toni Lönnberg [Wed, 16 Jan 2019 11:54:02 +0000 (13:54 +0200)]
intel/genxml: Media instructions and structures for gen7.5
v2: Fixed MI_WAIT_FOR_EVENT to be for video also
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Toni Lönnberg [Wed, 16 Jan 2019 11:53:13 +0000 (13:53 +0200)]
intel/genxml: Media instructions and structures for gen7
v2: Fixed MI_WAIT_FOR_EVENT to be for blitter and video also
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Toni Lönnberg [Wed, 16 Jan 2019 11:52:11 +0000 (13:52 +0200)]
intel/genxml: Media instructions and structures for gen6
v2: Fixed MI_WAIT_FOR_EVENT to be for blitter and video also
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Toni Lönnberg [Thu, 15 Nov 2018 14:04:34 +0000 (16:04 +0200)]
intel/genxml: Only handle instructions meant for render engine when generating
headers
v2: Fixed the check for engine
v3: Changed engine into an argument given to the scripts
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Dave Airlie [Wed, 27 Mar 2019 05:21:08 +0000 (15:21 +1000)]
softpipe: add indirect store buffer/image unit
The code to handle image unit indirect was missing
Fixes piglit tests/spec/arb_arrays_of_arrays/execution/image_store/basic-imageStore-mixed-const-non-const-uniform-index.shader_test
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Dave Airlie [Wed, 27 Mar 2019 04:06:50 +0000 (14:06 +1000)]
softpipe/draw: fix vertex id in soft paths.
This fixes the vertex id fetch in the non-llvm drawing paths.
This vertex id in elt mode comes from the elts not just a linear
value.
Note we don't bad basevertex in the elts case as it's already included
in the elts by the looks of it (at least tests fail if I add it)
Fixes piglit end-primitive tests and some others.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Kristian H. Kristensen [Tue, 26 Mar 2019 17:31:54 +0000 (10:31 -0700)]
freedreno/ir3: Push UBOs to constant file
We have a rather big constant file and it seems that the best way to
use it is to upload all UBOs and lower UBO access the load_uniform.
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Kristian H. Kristensen [Tue, 26 Mar 2019 17:31:54 +0000 (10:31 -0700)]
freedreno/ir3: Enable PIPE_CAP_PACKED_UNIFORMS
This commit turns on the gallium cap and adds a pass to lower the
load_ubo intrinsics for block 0 back to load_uniform intrinsics and
adjust the backend where the cap switches units from vec4s to dwords.
As we stop using ir3_glsl_type_size() for uniform layout, this also
corrects an issue where we would allocate a vec4 slot for samplers in
uniforms, fixing:
dEQP-GLES3.functional.shaders.struct.uniform.sampler_array_fragment
dEQP-GLES3.functional.shaders.struct.uniform.sampler_array_vertex
dEQP-GLES3.functional.shaders.struct.uniform.sampler_nested_fragment
dEQP-GLES2.functional.shaders.struct.uniform.sampler_nested_vertex
dEQP-GLES2.functional.shaders.struct.uniform.sampler_nested_fragment
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Kristian H. Kristensen [Tue, 26 Mar 2019 16:53:38 +0000 (09:53 -0700)]
st/glsl_to_nir: Calculate num_uniforms from NumParameterValues
We don't need to determine the number of uniform slots here, it's
already available as prog->Parameters->NumParameterValues. The way we
previously determined the number of slots was also broken for
PackedDriverUniformStorage, where we would add loc (in dwords) and
type_size() (in vec4s).
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Anuj Phogat [Mon, 21 May 2018 20:54:13 +0000 (13:54 -0700)]
intel: Add Elkhart Lake PCI-IDs
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Anuj Phogat [Fri, 7 Sep 2018 21:40:12 +0000 (14:40 -0700)]
intel: Add Elkhart Lake device info
V2: Fix L3 bank count (Vivek)
Fix simulator_id and num_eu_per_subslice (Lionel)
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Leo Liu [Tue, 26 Mar 2019 18:36:09 +0000 (14:36 -0400)]
radeon/vcn: add H.264 constrained baseline support
VCN supports this profile as well as UVD, so add it
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
CC: <mesa-stable@lists.freedesktop.org>
Gurchetan Singh [Wed, 27 Mar 2019 02:20:13 +0000 (19:20 -0700)]
egl/android: chose node type based on swrast and preprocessor flags
kms_swrast can work with primary nodes out of the box, but also
with rendernodes if the build environment specifies the
EGL_FORCE_RENDERNODE flag.
Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Gurchetan Singh [Wed, 13 Mar 2019 17:59:59 +0000 (10:59 -0700)]
egl/android: use software rendering when appropriate
Now the init logic fallbacks to or forces software rendering.
v2: simplify flow (@eric)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Gurchetan Singh [Wed, 13 Mar 2019 17:49:20 +0000 (10:49 -0700)]
egl/android: use swrast option in droid_load_driver
Load the kms_swrast driver when specified.
Doesn't work with drm_gralloc.
v2: remove unneeded line (@eric)
v3: Remove swrast_loader_extensions (@evelikov)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Gurchetan Singh [Wed, 13 Mar 2019 17:43:35 +0000 (10:43 -0700)]
egl/android: plumb swrast option
It's good to have options.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Gurchetan Singh [Wed, 27 Mar 2019 00:13:01 +0000 (17:13 -0700)]
egl/android: refactor droid_load_driver a bit
This way, we can use primary nodes with kms_swrast too.
Also fix up some whitespace issues.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Gurchetan Singh [Mon, 25 Mar 2019 23:50:46 +0000 (16:50 -0700)]
egl/android: droid_open_device_drm_gralloc --> droid_open_device
Makes things easier to follow.
Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Gurchetan Singh [Mon, 25 Mar 2019 23:46:31 +0000 (16:46 -0700)]
egl/android: move droid_open_device_drm_gralloc down a bit
1) Removes a forward declaration.
2) Makes next patch easier.
Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Gurchetan Singh [Mon, 25 Mar 2019 23:44:34 +0000 (16:44 -0700)]
egl/android: move droid_image_loader_extension down a bit
This removes some #ifdefs.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Wed, 27 Mar 2019 17:14:08 +0000 (10:14 -0700)]
docs: update calendar, add news item and link release notes for 19.0.1
Dylan Baker [Wed, 27 Mar 2019 17:10:37 +0000 (10:10 -0700)]
docs: Add SHA256 sums for mesa 19.0.1
Dylan Baker [Wed, 27 Mar 2019 17:02:21 +0000 (10:02 -0700)]
docs: Add release notes for 19.0.1
Jason Ekstrand [Wed, 27 Mar 2019 16:16:15 +0000 (11:16 -0500)]
Revert "anv/radv: release memory allocated by glsl types during spirv_to_nir"
This reverts commit
4e1bbb000cdfe4ba01bee5a6868c54fed7285dae. It turns
out that some DXVK apps due to some implementation detail of DXVK or
other create and destroy instances in an interleaved way. Freeing the
glsl_type memory without being a bit more careful causes use-after-free
issues. Looks like we need to try again.
Tomeu Vizoso [Wed, 27 Mar 2019 15:28:35 +0000 (16:28 +0100)]
panfrost: Wait for last job to finish in force_flush_fragment
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Tomeu Vizoso [Wed, 27 Mar 2019 15:26:49 +0000 (16:26 +0100)]
panfrost: Pass the context BOs to the kernel so they aren't unmapped while in use
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Tomeu Vizoso [Wed, 27 Mar 2019 13:57:33 +0000 (14:57 +0100)]
panfrost: Also tell the kernel about the checksum_slab
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Tomeu Vizoso [Wed, 27 Mar 2019 13:56:36 +0000 (14:56 +0100)]
panfrost: Set the GEM handle for AFBC buffers
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Tomeu Vizoso [Wed, 27 Mar 2019 13:56:00 +0000 (14:56 +0100)]
panfrost: Fix sscanf format options
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alexandros Frantzis [Mon, 18 Mar 2019 14:30:29 +0000 (16:30 +0200)]
virgl: Fake MSAA when max samples is 1
When the host is running on softpipe/llvmpipe the maximum number of
samples for multisampling is 1. GL 3.0 requires at least 4 samples, and
softpipe/llvmpipe get around this by enabling PIPE_CAP_FAKE_SW_MSAA.
This patch mimics softpipe/llvmpipe behavior in virgl by enabling the
same PIPE_CAP_FAKE_SW_MSAA workaround when the max sample count reported
by the host is 1. This change allows virgl on a softpipe/llvmpipe host
to advertise support for GL 3.0 and beyond.
Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Samuel Pitoiset [Mon, 25 Mar 2019 12:37:46 +0000 (13:37 +0100)]
ac: use llvm.amdgcn.fmed3 intrinsic for nir_op_fmed3
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Michel Dänzer [Tue, 26 Mar 2019 17:39:41 +0000 (18:39 +0100)]
gitlab-ci: Automatically retry jobs after runner system failure
Up to twice, for a total of 3 attempts maximum.
This will hopefully avoid spurious CI pipeline failures due to
intermittent GitLab/docker infrastructure issues.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Michel Dänzer [Tue, 26 Mar 2019 17:35:59 +0000 (18:35 +0100)]
gitlab-ci: Only pull/push cache contents in build+test stage jobs
The containers-build stage job doesn't use the cache, so this might save
some wasted time for it.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Michel Dänzer [Tue, 26 Mar 2019 09:04:27 +0000 (10:04 +0100)]
gitlab-ci: Make sure clang job actually uses ccache
Meson didn't automatically pick up ccache in this job for some reason.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Samuel Pitoiset [Tue, 26 Mar 2019 22:07:39 +0000 (23:07 +0100)]
spirv: propagate the access flag for store and load derefs
It was only propagated when UBO/SSBO access are lowered to offsets.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: <Jason Ekstrand jason@jlekstrand.net>
Samuel Pitoiset [Tue, 26 Mar 2019 22:06:53 +0000 (23:06 +0100)]
nir: add nir_{load,store}_deref_with_access() helpers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: <Jason Ekstrand jason@jlekstrand.net>
Timothy Arceri [Wed, 20 Mar 2019 04:56:54 +0000 (15:56 +1100)]
spirv: make use of the select control support in nir
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108841
Timothy Arceri [Wed, 20 Mar 2019 04:42:56 +0000 (15:42 +1100)]
nir: add support for user defined select control
This will allow us to make use of the selection control support in
spirv and the GL support provided by EXT_control_flow_attributes.
Note this only supports if-statements as we dont support switches
in NIR.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108841
Timothy Arceri [Wed, 20 Mar 2019 02:51:47 +0000 (13:51 +1100)]
spirv: make use of the loop control support in nir
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108841
Timothy Arceri [Wed, 20 Mar 2019 02:39:36 +0000 (13:39 +1100)]
nir: add support for user defined loop control
This will allow us to make use of the loop control support in
spirv and the GL support provided by EXT_control_flow_attributes.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108841
Alyssa Rosenzweig [Thu, 21 Mar 2019 02:54:38 +0000 (02:54 +0000)]
panfrost: Preliminary work for mipmaps
This patch refactors a substantial amount of code in preparation for
mipmaps. In particular, we know have a correct slice abstraction based
on offsets; cpu/gpu are no longer arbitrary pointers. We additionally
shuffle around other code to accompany these changes and cleanup how
tiled textures are handled, while drawing some attention to the blit
code.
Mipmaps are still disabled at this point, as autogeneration is not yet
implemented; enabling as-is would cause regressions.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Tue, 26 Mar 2019 04:48:20 +0000 (04:48 +0000)]
panfrost/midgard: fpow is a two-part operation
In fact, the native "fpow" instruction only does half of it; more work
is needed for the actual instruction. For now, just lower.
Fixes:
1ea42894c ("panfrost/midgard: Implement fpow")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Tue, 26 Mar 2019 04:36:58 +0000 (04:36 +0000)]
panfrost/midgard: Handle i2b constant
Fixes
dEQP-GLES2.functional.shaders.conversions.scalar_to_scalar.int_to_bool_fragment
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Tue, 26 Mar 2019 04:01:33 +0000 (04:01 +0000)]
panfrost/midgard: Expand fge lowering to more types
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Tue, 26 Mar 2019 04:00:33 +0000 (04:00 +0000)]
panfrost/midgard: Add ult/ule ops
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Mon, 25 Mar 2019 04:57:27 +0000 (04:57 +0000)]
panfrost: Stub out ES3 caps/callbacks
Although this is not functional (and the command stream side is not
aiming for ES3 right now), this is enough to run dEQP-GLES3 shader
tests with the version override directive; this is useful, as some ES3
shader feature can occur in ES2 class shaders due to lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Mon, 25 Mar 2019 03:17:43 +0000 (03:17 +0000)]
panfrost/midgard: Cleanup midgard_nir_algebraic.py
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Mon, 25 Mar 2019 02:49:04 +0000 (02:49 +0000)]
panfrost/midgard: Lower source modifiers for ints
On Midgard, float ops support standard source modifiers (abs/neg) and
destination modifiers (sat/pos/round). Integer ops do not support these,
however. To cope, we use native NIR source modifiers for floats, but
lower them away to iabs/ineg for integers, implementing those ops
simultaneously to avoid regressions.
Fixes the integer tests in
dEQP-GLES2.functional.shaders.operator.unary_operator.minus.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Mon, 25 Mar 2019 01:13:12 +0000 (01:13 +0000)]
panfrost/midgard: Implement b2i; improve b2f/f2b
Fixes
dEQP-GLES2.functional.shaders.conversions.scalar_to_scalar.bool_to_int_fragment
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Mon, 25 Mar 2019 00:56:48 +0000 (00:56 +0000)]
panfrost/midgard: Lower i2b32
Fixes
dEQP-GLES2.functional.shader.conversions.scalar_to_scalar.int_to_bool_vertex
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Mon, 25 Mar 2019 00:53:46 +0000 (00:53 +0000)]
panfrost/midgard: Lower f2b32 to fne
Fixes
dEQP-GLES2.functional.shaders.swizzles.vector_swizzles.mediump_bvec2_x_vertex
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Mon, 25 Mar 2019 00:25:01 +0000 (00:25 +0000)]
panfrost/midgard: Lower bool_to_int32
Fixes dEQP-GLES2.functional.shaders.linkage.varying_type_vec2 (among
many others).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Mon, 25 Mar 2019 00:12:06 +0000 (00:12 +0000)]
panfrost/midgard: Map more bany/ball opcodes
Some of these are not yet fully functional due to related bugs, but this
the correct op mapping. The native ball/bany opcodes act on vec4's
unconditionally. That said, both ball and bany have the nice property
that duplicating an argument does not affect their output, so the
default "hanging swizzles" allow us to implement 2/3-component opcodes
correctly, implicitly lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Mon, 25 Mar 2019 00:07:32 +0000 (00:07 +0000)]
panfrost/midgard: Add more ball/bany, iabs ops
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Sun, 24 Mar 2019 22:41:15 +0000 (22:41 +0000)]
panfrost/midgard: Schedule ball/bany to vectors
Though they output scalars, they need a vector unit to make sense.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Sun, 24 Mar 2019 22:27:06 +0000 (22:27 +0000)]
panfrost/midgard: Add fcsel_i opcode
Whereas a normal fcsel acts on a boolean input in r31.w, the fcsel_i
variant acts on an integer input in r31.w, which can be preloaded with
an instruction like imov (with the appropriate negate flag on the
source).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Sun, 24 Mar 2019 21:51:49 +0000 (21:51 +0000)]
panfrost: Implement scissor test
This preliminary implementation should handle some basic cases. Future
work should scissor the FRAGMENT job as well for efficiency.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Sun, 24 Mar 2019 20:01:15 +0000 (20:01 +0000)]
panfrost: Fix viewports
Our viewport code hardcoded a number of wrong assumptions, which sort of
sometimes worked but was definitely wrong (and broke most of dEQP). This
corrects the logic, accounting for flipped-Y framebuffers, which
fixes... most of dEQP.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Sun, 24 Mar 2019 16:07:31 +0000 (16:07 +0000)]
panfrost/midgard: Fix b2f32 swizzle for vectors
Fixes issues in most of dEQP-GLES2.functional.shaders.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Dave Airlie [Tue, 26 Mar 2019 05:25:18 +0000 (15:25 +1000)]
softpipe: fix clears to only clear specified color buffers.
This fixes piglit clearbuffer-mixed-format
Reviewed-by: Brian Paul <brianp@vmware.com>
Dave Airlie [Mon, 25 Mar 2019 05:38:18 +0000 (15:38 +1000)]
draw/vs: partly fix basevertex/vertex id
This gets the basevertex from the draw depending on whether
it's an indexed or non-indexed draw.
We still fail a transform feedback test for vertex id, as
the vertex id actually an index id, and isn't getting translated
properly to a vertex id, suggestions on how/where to fix that welcome.
Reviewed-by: Brian Paul <brianp@vmware.com>
Nicolai Hähnle [Wed, 9 Jan 2019 11:42:28 +0000 (12:42 +0100)]
amd/surface: provide firstMipIdInTail for metadata surface calculations
This field was added in a recent addrlib update, and while there
currently seems to be no issue with skipping it, we will have to
set it correctly in the future.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bas Nieuwenhuizen [Tue, 19 Mar 2019 00:29:43 +0000 (01:29 +0100)]
ac/nir: Return frag_coord as integer.
To preserve the invariant that nir ssa defs are integers or pointers
in LLVM.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Kristian H. Kristensen [Mon, 25 Mar 2019 21:04:20 +0000 (14:04 -0700)]
freedreno/ir3: Fix operand order for DSX/DSY
Most cat5 instructions are constructed using ir3_SAM, which uses
regs[1] for the (sampler, tex) src. Not DSX/DSY though, so we look up
src1 and src2 differently for those two.
Fixes:
1dffb089 ("freedreno/ir3: fix sam.s2en encoding")
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Kristian H. Kristensen [Mon, 25 Mar 2019 21:12:41 +0000 (14:12 -0700)]
freedreno/ir3: Track whether shader needs derivatives
In
1088b788 ("freedreno/ir3: find # of samplers from uniform vars") we
started counting number of samplers based on the uniform vars instead
of number of cat5 instructions. We used the number of samplers to
determine whether to enable derivatives, but when we only use
derivatives and no samplers, that now breaks. Track whether we need
derivatives explicitly and use that to enable the state.
Fixes:
1088b788 ("freedreno/ir3: find # of samplers from uniform vars")
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Andre Heider [Wed, 20 Mar 2019 20:38:40 +0000 (21:38 +0100)]
st/nine: enable csmt per default on iris
iris is thread safe, enable csmt for a ~5% performace boost.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Axel Davy <davyaxel0@gmail.com>
Jason Ekstrand [Wed, 27 Feb 2019 21:59:29 +0000 (15:59 -0600)]
spirv: Handle the NonUniformEXT decoration
Jason Ekstrand [Mon, 4 Mar 2019 19:04:45 +0000 (13:04 -0600)]
nir: Add access flags to deref and SSBO atomics
We will need them for a new ACCESS_NON_UNIFORM flag that's about to be
added in the next commit.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Sun, 28 Oct 2018 12:52:44 +0000 (07:52 -0500)]
nir: Add texture sources and intrinsics for bindless
On Intel, we have both bindless and bindful and we'd like to use them at
the same time if we can so we need to be able to distinguish at the NIR
level between the two. This also fixes nir_lower_tex to properly handle
bindless in its tex_texture_size and get_texture_lod helpers.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Danylo Piliaiev [Wed, 27 Feb 2019 15:10:42 +0000 (17:10 +0200)]
intel/fs: Make alpha test work with MRT and sample mask
Fix the order of src0_alpha and sample mask in fb payload.
From SKL PRM Volume 7, "Data Payload Register Order
for Render Target Write Messages":
Type S0A oM sZ oS M2 M3 M4
SIMD8 1 1 0 0 s0A oM R
SIMD16 1 1 0 0 1/0s0A 3/2s0A oM
It also fixes working of alpha to coverage with sample mask
on GEN6 since now they are in correct order.
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Danylo Piliaiev [Wed, 20 Feb 2019 17:39:18 +0000 (19:39 +0200)]
i965,iris,anv: Make alpha to coverage work with sample mask
From "Alpha Coverage" section of SKL PRM Volume 7:
"If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
hardware, regardless of the state setting for this feature."
From OpenGL spec 4.6, "15.2 Shader Execution":
"The built-in integer array gl_SampleMask can be used to change
the sample coverage for a fragment from within the shader."
From OpenGL spec 4.6, "17.3.1 Alpha To Coverage":
"If SAMPLE_ALPHA_TO_COVERAGE is enabled, a temporary coverage value
is generated where each bit is determined by the alpha value at the
corresponding sample location. The temporary coverage value is then
ANDed with the fragment coverage value to generate a new fragment
coverage value."
Similar wording could be found in Vulkan spec 1.1.100
"25.6. Multisample Coverage"
Thus we need to compute alpha to coverage dithering manually in shader
and replace sample mask store with the bitwise-AND of sample mask and
alpha to coverage dithering.
The following formula is used to compute final sample mask:
m = int(16.0 * clamp(src0_alpha, 0.0, 1.0))
dither_mask = 0x1111 * ((0xfea80 >> (m & ~3)) & 0xf) |
0x0808 * (m & 2) | 0x0100 * (m & 1)
sample_mask = sample_mask & dither_mask
Credits to Francisco Jerez <currojerez@riseup.net> for creating it.
It gives a number of ones proportional to the alpha for 2, 4, 8 or 16
least significant bits of the result.
GEN6 hardware does not have issue with simultaneous usage of sample mask
and alpha to coverage however due to the wrong sending order of oMask
and src0_alpha it is still affected by it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109743
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Wed, 27 Feb 2019 20:36:44 +0000 (14:36 -0600)]
nir: Add a lowering pass for non-uniform resource access
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>