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Kostya Serebryany [Tue, 14 Mar 2017 21:47:52 +0000 (21:47 +0000)]
[libFuzzer] remove more stale code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297785
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Kostya Serebryany [Tue, 14 Mar 2017 21:40:53 +0000 (21:40 +0000)]
[libFuzzer] don't clear Counters in TracePC::CollectFeatures since they will be cleared anyway in ResetMaps
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297783
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Daniel Sanders [Tue, 14 Mar 2017 21:32:08 +0000 (21:32 +0000)]
[globalisel][tblgen] Add support for ComplexPatterns
Summary:
Adds a new kind of MachineOperand: MO_Placeholder.
This operand must not appear in the MIR and only exists as a way of
creating an 'uninitialized' operand until a matcher function overwrites it.
Depends on D30046, D29712
Reviewers: t.p.northover, ab, rovka, aditya_nandakumar, javed.absar, qcolombet
Reviewed By: qcolombet
Subscribers: dberris, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D30089
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297782
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Kostya Serebryany [Tue, 14 Mar 2017 21:30:14 +0000 (21:30 +0000)]
[libFuzzer] remove stale code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297781
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Simon Pilgrim [Tue, 14 Mar 2017 21:26:58 +0000 (21:26 +0000)]
[SelectionDAG] Add a signed integer absolute ISD node
Reduced version of D26357 - based on the discussion on llvm-dev about canonicalization of UMIN/UMAX/SMIN/SMAX as well as ABS I've reduced that patch to just the ABS ISD node (with x86/sse support) to improve basic combines and lowering.
ARM/AArch64, Hexagon, PowerPC and NVPTX all have similar instructions allowing us to make this a generic opcode and move away from the hard coded tablegen patterns which makes it tricky to match more complex patterns.
At the moment this patch doesn't attempt legalization as we only create an ABS node if its legal/custom.
Differential Revision: https://reviews.llvm.org/D29639
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297780
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Derek Schuff [Tue, 14 Mar 2017 20:23:22 +0000 (20:23 +0000)]
[WebAssembly] Use LEB encoding for value types
Previously we were using the encoded LEB hex values
for the value types. This change uses the decoded
negative value and the LEB encoder to write them out.
Differential Revision: https://reviews.llvm.org/D30847
Patch by Sam Clegg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297777
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Rafael Espindola [Tue, 14 Mar 2017 19:57:13 +0000 (19:57 +0000)]
Archives require a symbol table on Solaris, even if empty.
On Solaris ld (and some other tools that use the underlying utility
libraries, such as elfdump) chokes on an archive library that has no
symbol table. The Solaris tools always create one, even if it's empty.
That bug has been fixed in the latest development line, and can
probably be backported to a supported release, but it would be nice if
LLVM's archiver could emit the empty symbol table, too.
Patch by Danek Duvall!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297773
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Evgeniy Stepanov [Tue, 14 Mar 2017 19:28:51 +0000 (19:28 +0000)]
Fix asm printing of associated sections.
Make MCSectionELF::AssociatedSection be a link to a symbol, because
that's how it works in the assembly, and use it in the asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297769
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Eli Friedman [Tue, 14 Mar 2017 18:43:37 +0000 (18:43 +0000)]
[ARM] Replace some C++ selection code with TableGen patterns. NFC.
Differential Revision: https://reviews.llvm.org/D30794
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297768
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Juergen Ributzka [Tue, 14 Mar 2017 18:37:44 +0000 (18:37 +0000)]
[Support] Make the SystemZ bot happy by using make_error_code.
This should fix the last issue on the SystemZ bot related to the broken symlink
test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297767
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Sanjay Patel [Tue, 14 Mar 2017 18:06:28 +0000 (18:06 +0000)]
[DAG] vector div/rem with any zero element in divisor is undef
This is the backend counterpart to:
https://reviews.llvm.org/rL297390
https://reviews.llvm.org/rL297409
and follow-up to:
https://reviews.llvm.org/rL297384
It surprised me that we need to duplicate the check in FoldConstantArithmetic and FoldConstantVectorArithmetic,
but one or the other doesn't catch all of the test cases. There is an existing code comment about merging those
someday.
Differential Revision: https://reviews.llvm.org/D30826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297762
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Dehao Chen [Tue, 14 Mar 2017 17:33:01 +0000 (17:33 +0000)]
SamplePGO ThinLTO ICP fix for local functions.
Summary:
In SamplePGO, if the profile is collected from non-LTO binary, and used to drive ThinLTO, the indirect call promotion may fail because ThinLTO adjusts local function names to avoid conflicts. There are two places of where the mismatch can happen:
1. thin-link prepends SourceFileName to front of FuncName to build the GUID (GlobalValue::getGlobalIdentifier). Unlike instrumentation FDO, SamplePGO does not use the PGOFuncName scheme and therefore the indirect call target profile data contains a hash of the OriginalName.
2. backend compiler promotes some local functions to global and appends .llvm.{$ModuleHash} to the end of the FuncName to derive PromotedFunctionName
This patch tries at the best effort to find the GUID from the original local function name (in profile), and use that in ICP promotion, and in SamplePGO matching that happens in the backend after importing/inlining:
1. in thin-link, it builds the map from OriginalName to GUID so that when thin-link reads in indirect call target profile (represented by OriginalName), it knows which GUID to import.
2. in backend compiler, if sample profile reader cannot find a profile match for PromotedFunctionName, it will try to find if there is a match for OriginalFunctionName.
3. in backend compiler, we build symbol table entry for OriginalFunctionName and pointer to the same symbol of PromotedFunctionName, so that ICP can find the correct target to promote.
Reviewers: mehdi_amini, tejohnson
Reviewed By: tejohnson
Subscribers: llvm-commits, Prazek
Differential Revision: https://reviews.llvm.org/D30754
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297757
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Sanjay Patel [Tue, 14 Mar 2017 17:27:27 +0000 (17:27 +0000)]
[InstCombine] improve readability; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297755
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Sanjay Patel [Tue, 14 Mar 2017 16:27:46 +0000 (16:27 +0000)]
[InstCombine] consolidate rem tests and update checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297747
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Sanjay Patel [Tue, 14 Mar 2017 16:16:40 +0000 (16:16 +0000)]
[InstCombine] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297746
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Krzysztof Parzyszek [Tue, 14 Mar 2017 15:21:33 +0000 (15:21 +0000)]
[Hexagon] Fix a condition in HexagonEarlyIfConv.cpp
This fixes llvm.org/PR32265.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297745
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Artyom Skrobov [Tue, 14 Mar 2017 14:13:19 +0000 (14:13 +0000)]
Fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297742
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Simon Pilgrim [Tue, 14 Mar 2017 14:03:16 +0000 (14:03 +0000)]
[X86] Add extra BITREVERSE tests
Test on 32-bit and 64-bit targets.
Add bitreverse tests for i64, i32 and i16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297741
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Gil Rapaport [Tue, 14 Mar 2017 13:50:47 +0000 (13:50 +0000)]
[LV] Refactor cross-iteration phi's back-patching; NFC
This patch refactors the PHisToFix loop as follows:
- The loop itself now resides in its own method.
- The new method iterates on scalar-loop's header; the PHIsToFix map formerly
propagated as an output parameter and filled during phi widening is removed.
- The code handling reductions is moved into its own method, similar to the
existing fixFirstOrderRecurrence().
Differential Revision: https://reviews.llvm.org/D30755
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297740
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Oliver Stannard [Tue, 14 Mar 2017 13:50:10 +0000 (13:50 +0000)]
[ARM] Diagnose ARM MOVT without :lower16: or :upper16: expression
This instruction was missing from the list of opcodes that we check, so we were
hitting an llvm_unreachable in ARMMCCodeEmitter.cpp for the ARM MOVT
instruction, rather than the diagnostic that is emitted for the other MOVW/MOVT
instructions.
Differential revision: https://reviews.llvm.org/D30936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297739
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Artyom Skrobov [Tue, 14 Mar 2017 13:38:45 +0000 (13:38 +0000)]
De-duplicate the two implementations of ARMBaseInstrInfo::isProfitableToIfCvt() [NFC]
Reviewers: congh, rengolin
Subscribers: aemerson, llvm-commits
Differential Revision: https://reviews.llvm.org/D30934
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297738
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Ayal Zaks [Tue, 14 Mar 2017 13:07:04 +0000 (13:07 +0000)]
[LV] Refactor Cost Model's selectVectorizationFactor(); NFC
Refactoring Cost Model's selectVectorizationFactor() so that it handles only the
selection of the best VF from a pre-computed range of candidate VF's, extracting
early-exit criteria and the computation of a MaxVF upper-bound to other methods,
all driven by a newly introduced LoopVectorizationPlanner.
Differential Revision: https://reviews.llvm.org/D30653
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297737
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Simon Pilgrim [Tue, 14 Mar 2017 12:13:41 +0000 (12:13 +0000)]
[X86][MMX] Update FIXME comment. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297736
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Daniel Berlin [Tue, 14 Mar 2017 11:25:45 +0000 (11:25 +0000)]
Make PredIteratorCache size() logically const. Do not require copying predecessors to get size.
Summary:
Every single benchmark i can run, on large and small cfgs, fully
connected, etc, across 3 different platforms (x86, arm., and PPC) says
that the current pred iterator cache is a losing proposition.
I can't find a case where it's faster than just walking preds, and in some cases, it's 5-10% slower.
This is due to copying the preds.
It also degrades into copying the entire cfg.
The one operation that is occasionally faster is the cached size.
This makes that operation faster by not relying on having the copies available.
I'm not even sure that is faster enough to be worth it. I, again, have
trouble finding cases where this takes long enough in a pass to be
worth caching compared to a million other things they could cache or
improve.
My suggestion:
We next remove the get() interface.
We do stronger benchmarking of size().
We probably end up killing this entire cache.
/
Reviewers: chandlerc
Subscribers: aemerson, llvm-commits, trentxintong
Differential Revision: https://reviews.llvm.org/D30873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297733
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James Henderson [Tue, 14 Mar 2017 10:51:14 +0000 (10:51 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297731
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Benjamin Kramer [Tue, 14 Mar 2017 10:29:47 +0000 (10:29 +0000)]
[CodeGen] Fix -Wreorder warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297729
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Tobias Grosser [Tue, 14 Mar 2017 10:18:11 +0000 (10:18 +0000)]
Fix typos in ADCE comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297726
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Oliver Stannard [Tue, 14 Mar 2017 10:13:17 +0000 (10:13 +0000)]
[ValueTracking] Out of range shifts might be undef
If it is possible for the RHS of a shift operation to be greater than or equal
to the bit-width, then the result might be undef, and we can't report any known
bits.
In some cases, this was allowing a transformation in instcombine which widened
an undef value from i1 to i32, increasing the range of values that a function
could return.
Differential revision: https://reviews.llvm.org/D30781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297724
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Sam Parker [Tue, 14 Mar 2017 09:13:22 +0000 (09:13 +0000)]
[ARM] Move SMULW[B|T] isel to DAG Combine
Create nodes for smulwb and smulwt and move their selection from
DAGToDAG to DAG combine. smlawb and smlawt can then be selected
using tablegen. Added some helper functions to detect shift patterns
as well as a wrapper around SimplifyDemandBits. Added a couple of
extra tests.
Differential Revision: https://reviews.llvm.org/D30708
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297716
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Oren Ben Simhon [Tue, 14 Mar 2017 09:09:26 +0000 (09:09 +0000)]
Disable Callee Saved Registers
Each Calling convention (CC) defines a static list of registers that should be preserved by a callee function. All other registers should be saved by the caller.
Some CCs use additional condition: If the register is used for passing/returning arguments – the caller needs to save it - even if it is part of the Callee Saved Registers (CSR) list.
The current LLVM implementation doesn’t support it. It will save a register if it is part of the static CSR list and will not care if the register is passed/returned by the callee.
The solution is to dynamically allocate the CSR lists (Only for these CCs). The lists will be updated with actual registers that should be saved by the callee.
Since we need the allocated lists to live as long as the function exists, the list should reside inside the Machine Register Info (MRI) which is a property of the Machine Function and managed by it (and has the same life span).
The lists should be saved in the MRI and populated upon LowerCall and LowerFormalArguments.
The patch will also assist to implement future no_caller_saved_regsiters attribute intended for interrupt handler CC.
Differential Revision: https://reviews.llvm.org/D28566
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297715
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Craig Topper [Tue, 14 Mar 2017 06:40:04 +0000 (06:40 +0000)]
[AVX-512] Use iPTR instead of i64 in patterns for extract_subvector/insert_subvector index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297707
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Craig Topper [Tue, 14 Mar 2017 06:40:00 +0000 (06:40 +0000)]
[AVX-512] Add test cases that demonstrate some patterns that don't work correctly in 32-bit mode. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297706
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Jonas Paulsson [Tue, 14 Mar 2017 06:35:36 +0000 (06:35 +0000)]
[TargetTransformInfo] getIntrinsicInstrCost() scalarization estimation improved
getIntrinsicInstrCost() used to only compute scalarization cost based on types.
This patch improves this so that the actual arguments are checked when they are
available, in order to handle only unique non-constant operands.
Tests updates:
Analysis/CostModel/X86/arith-fp.ll
Transforms/LoopVectorize/AArch64/interleaved_cost.ll
Transforms/LoopVectorize/ARM/interleaved_cost.ll
The improvement in getOperandsScalarizationOverhead() to differentiate on
constants made it necessary to update the interleaved_cost.ll tests even
though they do not relate to intrinsics.
Review: Hal Finkel
https://reviews.llvm.org/D29540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297705
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Craig Topper [Tue, 14 Mar 2017 04:18:25 +0000 (04:18 +0000)]
[AVX-512] Pre-emptively fix more places in fastisel where we might copy a VK1 register into a AH/BH/CH/DH register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297704
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Daniel Berlin [Tue, 14 Mar 2017 01:46:51 +0000 (01:46 +0000)]
Add missing condprop-xfail.ll that contains the remaining xfail'd tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297699
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Nirav Dave [Tue, 14 Mar 2017 01:42:23 +0000 (01:42 +0000)]
Recommitting Craig Topper's patch now that r296476 has been recommitted.
When checking if chain node is foldable, make sure the intermediate nodes have a single use across all results not just the result that was used to reach the chain node.
This recovers a test case that was severely broken by r296476, my making sure we don't create ADD/ADC that loads and stores when there is also a flag dependency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297698
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Nirav Dave [Tue, 14 Mar 2017 00:34:14 +0000 (00:34 +0000)]
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297695
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Vitaly Buka [Mon, 13 Mar 2017 23:49:00 +0000 (23:49 +0000)]
[libFuzzer] Reorder includes in test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297692
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Vitaly Buka [Mon, 13 Mar 2017 23:46:30 +0000 (23:46 +0000)]
[libFuzzer] Fix compilation of CustomCrossOverAndMutateTest on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297690
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Zachary Turner [Mon, 13 Mar 2017 23:28:25 +0000 (23:28 +0000)]
Add the beginning of PDB diffing support.
For now this only diffs the stream directory and the MSF
Superblock. Future patches will drill down into individual
streams to find out where the differences lie.
Differential Revision: https://reviews.llvm.org/D30908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297689
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Adrian Prantl [Mon, 13 Mar 2017 22:56:14 +0000 (22:56 +0000)]
Revert "Debug Info: Add basic support for external types references."
This reverts commit r242302. External type refs of this form were
never used by any LLVM frontend so this is effectively dead code.
(They were introduced to support clang module debug info, but in the
end we came up with a better design that doesn't use this feature at
all.)
rdar://problem/
25897929
Differential Revision: https://reviews.llvm.org/D30917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297684
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Daniel Berlin [Mon, 13 Mar 2017 22:43:30 +0000 (22:43 +0000)]
NewGVN: We pass rle-nonlocal, we just perform the replacement in a way that keeps the old name instead of the new one
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297683
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Artyom Skrobov [Mon, 13 Mar 2017 22:36:14 +0000 (22:36 +0000)]
[Thumb1] combine ADDC/SUBC with a negative immediate
Summary: This simple optimization has been split out of https://reviews.llvm.org/D30400
Reviewers: efriedma, jmolloy
Subscribers: llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D30829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297682
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Rui Ueyama [Mon, 13 Mar 2017 22:19:05 +0000 (22:19 +0000)]
Make FileOutputBuffer fail early if you pass a directory.
Previously, it created a temporary directory and then failed when
FileOutputBuffer tried to rename that file to the destination file
(which is actually a directory name).
Differential Revision: https://reviews.llvm.org/D30912
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297679
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Craig Topper [Mon, 13 Mar 2017 21:58:54 +0000 (21:58 +0000)]
[AVX-512] Fix another case where we are copying from a mask register using AH/BH/CH/DH with fastisel.
Fixes PR32256. Still planning to do an audit for other possible cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297678
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David Blaikie [Mon, 13 Mar 2017 21:46:37 +0000 (21:46 +0000)]
Fix llvm-symbolizer to navigate both DW_AT_abstract_origin and DW_AT_specification in a single chain
In a recent refactoring (r291959) this regressed to only following one
or the other, not both, in a single chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297676
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David Blaikie [Mon, 13 Mar 2017 21:46:14 +0000 (21:46 +0000)]
Remove unused lambda capture
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297675
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David Blaikie [Mon, 13 Mar 2017 21:46:12 +0000 (21:46 +0000)]
Fix sign compare warning in unit test by using an explicit unsigned literal suffix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297674
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Marcello Maggioni [Mon, 13 Mar 2017 21:42:53 +0000 (21:42 +0000)]
[IPRA] Change algorithm for RegUsageInfoCollector.
The previous algorithm for RegUsageInfoCollector had pretty bad
performance on architectures with a lot of registers that alias
a lot one another, because we potentially iterate for every register
over all the aliasing registers. This costs even more if the function
is small and doesn't define a lot of registers.
This patch changes the algorithm to one that while iterating over
all the registers it will iterate over the aliasing registers only
if the register itself is defined.
This should be faster based on the assumption that only a subset
of the whole LLVM registers set is actually defined in the function.
Differential Revision: https://reviews.llvm.org/D30880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297673
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Juergen Ributzka [Mon, 13 Mar 2017 21:40:20 +0000 (21:40 +0000)]
[Support] Follow-up for "Test directory iterators and recursive directory iterators with broken symlinks."
Fix the test by sorting the result vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297672
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Volkan Keles [Mon, 13 Mar 2017 21:36:19 +0000 (21:36 +0000)]
GlobalISel: Translate ConstantDataVector
Reviewers: qcolombet, aditya_nandakumar, dsanders, t.p.northover, javed.absar, ab
Reviewed By: qcolombet, dsanders, ab
Subscribers: dberris, rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D30216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297670
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Juergen Ributzka [Mon, 13 Mar 2017 21:34:07 +0000 (21:34 +0000)]
[Support] Test directory iterators and recursive directory iterators with broken symlinks.
This commit adds a unit test to the file system tests to verify the behavior of
the directory iterator and recursive directory iterator with broken symlinks.
This test is Unix only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297669
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Tim Northover [Mon, 13 Mar 2017 21:25:10 +0000 (21:25 +0000)]
Revert "GlobalISel: move vector extract/insert inside generic opcode region."
I was writing against an earlier branch and Volkan had already fixed this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297668
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Simon Pilgrim [Mon, 13 Mar 2017 21:23:29 +0000 (21:23 +0000)]
[X86][MMX] Fix folding of shift value loads to cover whole 64-bits
rL230225 made the assumption that only the lower 32-bits of an MMX register load is used as a shift value, when in fact the whole 64-bits are reloaded and treated as a i64 to determine the shift value.
This patch reverts rL230225 to ensure that the whole 64-bits of memory are folded and ensures that the upper 32-bit are zero'd for cases where the shift value has come from a scalar source.
Found during fuzz testing.
Differential Revision: https://reviews.llvm.org/D30833
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297667
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Tim Northover [Mon, 13 Mar 2017 21:18:59 +0000 (21:18 +0000)]
GlobalISel: move vector extract/insert inside generic opcode region.
Otherwise they won't be legalized or selected, causing instruction selection to
fail horribly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297666
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Andrew Kaylor [Mon, 13 Mar 2017 20:35:10 +0000 (20:35 +0000)]
Revert r295004 (Add MXCSR) due to errors reported by MachineVerifier
I am leaving the code in clang which filters mxcsr from the clobber list because that is still technically correct and will be useful again when the MXCSR register is reintroduced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297664
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Volkan Keles [Mon, 13 Mar 2017 20:31:45 +0000 (20:31 +0000)]
[GlobalISel] Update PRE_ISEL_GENERIC_OPCODE_END marker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297663
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Matt Arsenault [Mon, 13 Mar 2017 20:18:14 +0000 (20:18 +0000)]
AMDGPU: Re-use TM.getNullPointerValue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297662
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Rafael Espindola [Mon, 13 Mar 2017 20:00:25 +0000 (20:00 +0000)]
Bring back r297624.
The issues was just a missing REQUIRES in the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297661
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Sanjay Patel [Mon, 13 Mar 2017 19:59:14 +0000 (19:59 +0000)]
[SimplifyCFG] move tests for PR31028 from CGP
Hopefully, this will make sense with a forthcoming patch. If not, we can move these back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297660
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Matt Arsenault [Mon, 13 Mar 2017 19:47:31 +0000 (19:47 +0000)]
AMDGPU: Treat 0 as private null pointer in addrspacecast lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297658
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Rafael Espindola [Mon, 13 Mar 2017 19:38:32 +0000 (19:38 +0000)]
Revert "Fix crash when multiple raw_fd_ostreams to stdout are created."
This reverts commit r297624.
It was failing on the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297657
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Daniel Berlin [Mon, 13 Mar 2017 19:09:23 +0000 (19:09 +0000)]
Fix some indenting and line-wrapping issues identified in ProgrammersManual. Make description of debugCounters a little clearer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297656
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Jessica Paquette [Mon, 13 Mar 2017 18:39:33 +0000 (18:39 +0000)]
[Outliner] Add tail call support
This commit adds tail call support to the MachineOutliner pass. This allows
the outliner to insert jumps rather than calls in areas where tail calling is
possible. Outlined tail calls include the return or terminator of the basic
block being outlined from.
Tail call support allows the outliner to take returns and terminators into
consideration while finding candidates to outline. It also allows the outliner
to save more instructions. For example, in the X86-64 outliner, a tail called
outlined function saves one instruction since no return has to be inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297653
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Craig Topper [Mon, 13 Mar 2017 18:34:46 +0000 (18:34 +0000)]
[X86] Lower AVX2 gather intrinsics similar to AVX-512. Apply the same input source optimizations to break execution dependencies.
For AVX-512 we force the input to zero if the input is undef or the mask is all ones to break an execution dependency. This patch brings the same behavior to AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297652
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Craig Topper [Mon, 13 Mar 2017 18:17:46 +0000 (18:17 +0000)]
[AVX-512] If gather mask is all ones, force the input to a zero vector.
We were already forcing undef inputs to become a zero vector, this now catches an all ones mask too.
Ideally we'd use undef and let execution dep fix handle picking the best register/clearance for the undef, but I don't think it can handle the early clobber today.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297651
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Matt Arsenault [Mon, 13 Mar 2017 18:14:02 +0000 (18:14 +0000)]
AMDGPU: Fold icmp/fcmp into icmp intrinsic
The typical use is a library vote function which
compares to 0. Fold the user condition into the intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297650
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Jonas Devlieghere [Mon, 13 Mar 2017 18:08:11 +0000 (18:08 +0000)]
[Linker] Provide callback for internalization
Differential Revision: https://reviews.llvm.org/D30738
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297649
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Craig Topper [Mon, 13 Mar 2017 17:37:14 +0000 (17:37 +0000)]
[SelectionDAG] Enhance SDTCisSameNumEltsAs to work with scalar types and use it on extend/trunc/round operations.
Currently we don't enforce that ISD::ANY_EXTEND, ZERO_EXTEND, SIGN_EXTEND, TRUNC, FP_ROUND, FP_EXTEND have the same number of elements(including scalar) between their input and output. Though we have them documented as such. Up until a few months ago x86 created nodes that violated this rule. That's all been fixed now, and we should enforce the rule going forward.
In order to do this we need to allow SDTCisSameNumEltsAs to support scalar types and not enforce being a vector. If one type is scalar we will force the other type to also be scalar.
Differential Revision: https://reviews.llvm.org/D30878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297648
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Zachary Turner [Mon, 13 Mar 2017 17:25:47 +0000 (17:25 +0000)]
Add missing include on <limits>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297646
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Adrian Prantl [Mon, 13 Mar 2017 17:20:47 +0000 (17:20 +0000)]
API gardening: Rename FindAllocaDbgValue to findDbgValue (NFC)
and use have it use SmallVectorImpl.
There is nothing specific about allocas in this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297643
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Zachary Turner [Mon, 13 Mar 2017 17:12:37 +0000 (17:12 +0000)]
Use numeric_limits<size_t>::max() instead of size_t(-1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297641
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Zachary Turner [Mon, 13 Mar 2017 16:41:49 +0000 (16:41 +0000)]
Fix a warning due to signed/unsigned comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297639
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Zachary Turner [Mon, 13 Mar 2017 16:32:08 +0000 (16:32 +0000)]
Use the new member accessors of llvm::enumerate.
The value_type is no longer a struct, it's a class whose
members you have to access via a method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297635
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Zachary Turner [Mon, 13 Mar 2017 16:24:10 +0000 (16:24 +0000)]
[ADT] Improve the genericity of llvm::enumerate().
There were some issues in the implementation of enumerate()
preventing it from being used in various contexts. These were
all related to the fact that it did not supporter llvm's
iterator_facade_base class. So this patch adds support for that
and additionally exposes a new helper method to_vector() that
will evaluate an entire range and store the results in a
vector.
Differential Revision: https://reviews.llvm.org/D30853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297633
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Zachary Turner [Mon, 13 Mar 2017 16:18:08 +0000 (16:18 +0000)]
Remove an unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297632
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Sanjay Patel [Mon, 13 Mar 2017 15:45:37 +0000 (15:45 +0000)]
[CGP] add tests for PR31028; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297629
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Zachary Turner [Mon, 13 Mar 2017 14:57:45 +0000 (14:57 +0000)]
[llvm-pdbdump] Add support for dumping symbols from Yaml -> PDB.
Previously we could round-trip type records from PDB -> Yaml ->
PDB, but for symbols we could only go from PDB -> Yaml. This
completes the round-tripping for symbols as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297625
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Rafael Espindola [Mon, 13 Mar 2017 14:45:06 +0000 (14:45 +0000)]
Fix crash when multiple raw_fd_ostreams to stdout are created.
If raw_fd_ostream is constructed with the path of "-", it claims
ownership of the stdout file descriptor. This means that it closes
stdout when it is destroyed. If there are multiple users of
raw_fd_ostream wrapped around stdout, then a crash can occur because
of operations on a closed stream.
An example of this would be running something like "clang -S -o - -MD
-MF - test.cpp". Alternatively, using outs() (which creates a local
version of raw_fd_stream to stdout) anywhere combined with such a
stream usage would cause the crash.
The fix duplicates the stdout file descriptor when used within
raw_fd_ostream, so that only that particular descriptor is closed when
the stream is destroyed.
Patch by James Henderson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297624
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Diana Picus [Mon, 13 Mar 2017 14:28:34 +0000 (14:28 +0000)]
[ARM] GlobalISel: Support SP in regbankselect
We used to hit an unreachable in getRegBankFromRegClass when dealing with the
stack pointer. This commit adds support for the GPRsp reg class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297621
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Aaron Ballman [Mon, 13 Mar 2017 12:24:51 +0000 (12:24 +0000)]
Reverting r297617 because it broke some bots:
http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/49970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297618
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Aaron Ballman [Mon, 13 Mar 2017 12:17:14 +0000 (12:17 +0000)]
Add support for getting file system permissions and implement sys::fs::permissions to set them.
Patch by James Henderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297617
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Balaram Makam [Mon, 13 Mar 2017 10:42:17 +0000 (10:42 +0000)]
[AArch64] Map Sched Read/Write resources for Falkor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297611
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Gil Rapaport [Mon, 13 Mar 2017 10:23:46 +0000 (10:23 +0000)]
[LV] Set memcheck metadata also for VF==1
This commit is a follow-up on r297580. It fixes the FIXME added temporarily
by that commit to keep the removal of Unroller's specialized version of
scalarizeInstruction() an NFC. See https://reviews.llvm.org/D30715 for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297610
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Sjoerd Meijer [Mon, 13 Mar 2017 09:41:10 +0000 (09:41 +0000)]
ARMDisassembler: loop over ARM decode tables
Loop over the ARM decode tables; this is a clean-up to reduce some code
duplication.
Differential Revision: https://reviews.llvm.org/D30814
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297608
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Konstantin Zhuravlyov [Mon, 13 Mar 2017 06:03:11 +0000 (06:03 +0000)]
AMDGPU/RelocVisitor: Handle R_AMDGPU_ABS64
Test is in the separate patch.
Differential Revision: https://reviews.llvm.org/D30027
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297604
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Craig Topper [Mon, 13 Mar 2017 05:47:56 +0000 (05:47 +0000)]
[AVX-512] Add EVEX2VEX test cases for the cvt instructions fixed in r297599 and r297600.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297603
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Craig Topper [Mon, 13 Mar 2017 05:34:03 +0000 (05:34 +0000)]
Revert "[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead."
This reverts r297596.
There were other issues that were making this not work that have been fixed now. Reverting this results in a more accurate table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297602
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Craig Topper [Mon, 13 Mar 2017 05:14:47 +0000 (05:14 +0000)]
[AVX-512] Add VEX_WIG to VEX vcvtsd2ss/vcvtss2sd intrinsic instructions so they can be correctly matched by EVEX2VEX table generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297601
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Craig Topper [Mon, 13 Mar 2017 05:14:44 +0000 (05:14 +0000)]
[AVX-512] Use sse_loadf32/f64 for vcvtss2sd and vcvtsd2ss intrinsic patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297600
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Craig Topper [Mon, 13 Mar 2017 03:59:06 +0000 (03:59 +0000)]
[AVX-512] Use sse_load_f64/f32 in VCVTSS2SI/VCVTSD2SI patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297599
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Craig Topper [Mon, 13 Mar 2017 00:36:49 +0000 (00:36 +0000)]
[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead.
This exposed that we have several intrinsic instructions that have identical TSFlags to other instructions. We should merge their patterns and kill of the duplicate. I'll fix that in a follow up patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297596
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Craig Topper [Mon, 13 Mar 2017 00:36:46 +0000 (00:36 +0000)]
[X86] Minor formatting tweaks in EVEX to VEX tables. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297595
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Craig Topper [Sun, 12 Mar 2017 23:05:03 +0000 (23:05 +0000)]
[X86] Remove unused SDTypeProfile. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297594
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Craig Topper [Sun, 12 Mar 2017 23:05:00 +0000 (23:05 +0000)]
[X86] Lower SSE/AVX cmpps/pd intrinsics directly to X86ISD::CMPP SDNodes.
This allows us to remove a duplicate set of patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297593
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Craig Topper [Sun, 12 Mar 2017 22:29:12 +0000 (22:29 +0000)]
[AVX-512] Fix the valid immediates for the scatter/gather prefetch intrinsics.
The immediate should be 1 or 2, not 0 or 1. This was found while adding bounds checking to clang. In fact the existing clang builtin test failed if we ran it all the way to assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297591
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Sanjay Patel [Sun, 12 Mar 2017 18:28:48 +0000 (18:28 +0000)]
[x86] don't blindly transform SETB into SBB
I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently.
This happens because we were transforming any 'setb' - even when we only wanted a single-bit result.
This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it
is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that
existing behavior in this patch.
Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files
where this transform still fires.
The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register
stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate
issue.
Differential Revision: https://reviews.llvm.org/D30611
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297586
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Anna Thomas [Sun, 12 Mar 2017 14:06:41 +0000 (14:06 +0000)]
[LVI] Add Datalayout to the class LazyValueInfo since all its Impls require it. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297583
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Azharuddin Mohammed [Sun, 12 Mar 2017 14:02:32 +0000 (14:02 +0000)]
Remove CRC32 instructions from AArch64InstrInfo::hasShiftedReg
Summary:
A53 scheduler causes an assertion failure on all CRC instructions:
include/llvm/CodeGen/MachineInstr.h:280: const llvm::MachineOperand
&llvm::MachineInstr::getOperand(unsigned int) const: Assertion `i <
getNumOperands() && "getOperand() out of range!"' failed.
The case statements corresponding to CRC instructions are incorrect and should
be removed.
Also adding a testcase while on this.
Reviewers: t.p.northover, javed.absar, apazos, rengolin
Reviewed By: rengolin
Subscribers: evandro, aemerson, llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D30274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297582
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Igor Breger [Sun, 12 Mar 2017 13:20:10 +0000 (13:20 +0000)]
[X86] Add vector zext tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297581
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