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Sanjoy Das [Mon, 13 Jun 2016 19:55:04 +0000 (19:55 +0000)]
Fix AAResults::callCapturesBefore for operand bundles
Summary:
AAResults::callCapturesBefore would previously ignore operand
bundles. It was possible for a later instruction to miss its memory
dependency on a call site that would only access the pointer through a
bundle.
Patch by Oscar Blumberg!
Reviewers: sanjoy
Differential Revision: http://reviews.llvm.org/D21286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272580
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George Burgess IV [Mon, 13 Jun 2016 19:38:49 +0000 (19:38 +0000)]
Attempt to make windows buildbots happy.
Broken by r272578. I didn't realize that the default move ctor
complaints would happen for non-template classes. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272579
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George Burgess IV [Mon, 13 Jun 2016 19:21:18 +0000 (19:21 +0000)]
[CFLAA] Refactor to remove redundant maps. NFC.
Patch by Jia Chen.
Differential Revision: http://reviews.llvm.org/D21233
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272578
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Simon Pilgrim [Mon, 13 Jun 2016 19:08:28 +0000 (19:08 +0000)]
[X86][SSE] Added extract to scalar nontemporal store tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272577
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David Majnemer [Mon, 13 Jun 2016 17:33:13 +0000 (17:33 +0000)]
[X86] Remove llvm.x86.bit.scan.{forward,reverse}.32
The need for these intrinsics has been obviated by r272564 which
reimplements their functionality using generic IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272566
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Rafael Espindola [Mon, 13 Jun 2016 17:08:15 +0000 (17:08 +0000)]
Add triple to input file.
Patch by H.J. Lu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272563
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Marek Olsak [Mon, 13 Jun 2016 16:05:57 +0000 (16:05 +0000)]
AMDGPU/SI: Set INDEX_STRIDE for scratch coalescing
Summary:
Mesa and other users must set this to enable coalescing:
- STRIDE = 0
- SWIZZLE_ENABLE = 1
This makes one particular compute shader 8x faster.
Reviewers: tstellarAMD, arsenm
Subscribers: arsenm, kzhuravl
Differential Revision: http://reviews.llvm.org/D21136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272556
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Taewook Oh [Mon, 13 Jun 2016 15:54:56 +0000 (15:54 +0000)]
In openFileForRead, attempt to fetch the actual name of the file on disk -- including case -- so that clang can later warn about non-portable #include and #import directives.
Differential Revision: http://reviews.llvm.org/D19842
Corresponding clang patch: http://reviews.llvm.org/D19843
Re-commit after addressing issues with of generating too many warnings for Windows and asan test failures
Patch by Eric Niebler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272555
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Matt Arsenault [Mon, 13 Jun 2016 15:53:52 +0000 (15:53 +0000)]
AMDGPU: Fix post-RA verifier errors with trackLivenessAfterRegAlloc
The condition reg of the cndmask_b64 expansion can't be killed by
the first one, and the implicit super register implicit def is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272554
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Ulrich Weigand [Mon, 13 Jun 2016 14:24:05 +0000 (14:24 +0000)]
[SystemZ] Enable index register memory constraints for inline ASM
This enables use of the 'R' and 'T' memory constraints for inline ASM
operands on SystemZ, which allow an index register as well as an
immediate displacement. This patch includes corresponding documentation
and test case updates.
As with the last patch of this kind, I moved the 'm' constraint to the
most general case, which is now 'T' (base + 20-bit signed displacement +
index register).
Author: colpell
Differential Revision: http://reviews.llvm.org/D21239
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272547
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Ranjeet Singh [Mon, 13 Jun 2016 10:58:24 +0000 (10:58 +0000)]
[ARM] Reverting r272544 because clang patch needs
to go in as soon as llvm patch has gone in because
tests will start breaking in Clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272546
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Vikram TV [Mon, 13 Jun 2016 10:49:28 +0000 (10:49 +0000)]
Fix a typo in loop versioning.
Reviewers: ashutosh.nema
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D21281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272545
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Ranjeet Singh [Mon, 13 Jun 2016 10:43:50 +0000 (10:43 +0000)]
[ARM] Add mrrc/mrrc2 co-processor intrinsics
MRRC/MRRC2 instruction writes to two registers. The
intrinsic definition returns a single uint64_t to
represent the write, this is a compact way of
representing a write to two 32 bit registers,
the alternative might have been two return a
struct of 2 uint32_t's but this isn't as nice.
Differential Revision:
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272544
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Strahinja Petrovic [Mon, 13 Jun 2016 10:29:29 +0000 (10:29 +0000)]
This patch fixes handling long double type when it is
constant in soft float mode on PowerPC 32 architecture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272543
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Simon Pilgrim [Mon, 13 Jun 2016 10:14:42 +0000 (10:14 +0000)]
[X86][SSE4A] Renamed tests to correspond with the the instruction with being tested
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272542
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Haojian Wu [Mon, 13 Jun 2016 09:03:45 +0000 (09:03 +0000)]
Fix an enumeral mismatch warning.
Summary:
The "-Werror=enum-compare" shows that the statement is using two different enums:
enumeral mismatch in conditional expression: 'llvm::X86ISD::NodeType' vs 'llvm::ISD::NodeType'
A follow-up fix on D21235.
Reviewers: klimek
Subscribers: spatel, cfe-commits
Differential Revision: http://reviews.llvm.org/D21278
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272539
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Zijiao Ma [Mon, 13 Jun 2016 05:27:58 +0000 (05:27 +0000)]
[AArch64] Add RAS extensions support in AArch64TargetParser.
RAS extensions are part of ARMv8.2,now supported in Clang.
Add RAS extensions support in AArch64TargetParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272533
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Craig Topper [Mon, 13 Jun 2016 02:36:48 +0000 (02:36 +0000)]
[AVX512] Remove maksed pshufd, pshuflw, and phufhw intrinsics and autoupgrade them to selects and shufflevector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272527
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Craig Topper [Mon, 13 Jun 2016 02:36:42 +0000 (02:36 +0000)]
[X86] Refactor some of the X86 autoupgrade code to split mask vector and select generation into routines that can be reused for future intrinsic upgrades. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272526
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Mike Spertus [Mon, 13 Jun 2016 01:43:14 +0000 (01:43 +0000)]
Improved Visual Studio 2015 visualization of SmallVectorImpl
When visualizing small vectors in VS2015, show the first few elements in the DisplayString instead of the size. For example, a SmallVector of DeclAccessPair will visualize like
{public typename ...Ts, public typename U}
The visualization in VS2013 remains the same because we continue to include the old visualizer with a lower-than-default priority of MediumLow, and the same SmallVector would continue to be visualized as
{size = 2}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272525
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NAKAMURA Takumi [Mon, 13 Jun 2016 00:18:19 +0000 (00:18 +0000)]
Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272523
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Benjamin Kramer [Sun, 12 Jun 2016 19:02:34 +0000 (19:02 +0000)]
Use 'auto' to avoid implicit copies.
td_type is std::pair<std::string, std::string>, but the map returns
elements of std::pair<const std::string, std::string>. In well-designed
languages like C++ that yields an implicit copy perfectly hidden by
constref's lifetime extension. Just use auto, the typedef obscured the
real type anyways.
Found with a little help from clang-tidy's
performance-implicit-cast-in-loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272519
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Benjamin Kramer [Sun, 12 Jun 2016 17:46:23 +0000 (17:46 +0000)]
[Verifier] Simplify code. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272517
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Benjamin Kramer [Sun, 12 Jun 2016 17:30:47 +0000 (17:30 +0000)]
Run clang-tidy's performance-unnecessary-copy-initialization over LLVM.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272516
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Xinliang David Li [Sun, 12 Jun 2016 16:54:03 +0000 (16:54 +0000)]
[MBP] Code cleanup /NFC
This is second patch to clean up the code.
In this patch, the logic to determine block outlinining
is refactored and more comments are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272514
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Benjamin Kramer [Sun, 12 Jun 2016 16:13:55 +0000 (16:13 +0000)]
Move instances of std::function.
Or replace with llvm::function_ref if it's never stored. NFC intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272513
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Benjamin Kramer [Sun, 12 Jun 2016 15:39:02 +0000 (15:39 +0000)]
Pass DebugLoc and SDLoc by const ref.
This used to be free, copying and moving DebugLocs became expensive
after the metadata rewrite. Passing by reference eliminates a ton of
track/untrack operations. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272512
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Sanjay Patel [Sun, 12 Jun 2016 15:03:25 +0000 (15:03 +0000)]
[x86, SSE] change patterns for CMPP to float types to allow matching with SSE1 (PR28044)
This patch is intended to solve:
https://llvm.org/bugs/show_bug.cgi?id=28044
By changing the definition of X86ISD::CMPP to use float types, we allow it to be created
and pass legalization for an SSE1-only target where v4i32 is not legal.
The motivational trail for this change includes:
https://llvm.org/bugs/show_bug.cgi?id=28001
and eventually makes this trigger:
http://reviews.llvm.org/D21190
Ie, after this step, we should be free to have Clang generate FP compare IR instead of x86
intrinsics for SSE C packed compare intrinsics. (We can auto-upgrade and remove the LLVM
sse.cmp intrinsics as a follow-up step.) Once we're generating vector IR instead of x86
intrinsics, a big pile of generic optimizations can trigger.
Differential Revision: http://reviews.llvm.org/D21235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272511
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Craig Topper [Sun, 12 Jun 2016 14:11:32 +0000 (14:11 +0000)]
[X86] Remove sse2 pshufd/pshuflw/pshufhw intrinsics and upgrade them to shufflevector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272510
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Benjamin Kramer [Sun, 12 Jun 2016 13:32:23 +0000 (13:32 +0000)]
[RegUsageInfoCollector] Drop unneccesary const_cast. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272509
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Simon Pilgrim [Sun, 12 Jun 2016 09:56:05 +0000 (09:56 +0000)]
[X86][BMI] Added fast-isel tests for BMI1 intrinsics
A lot of the codegen is pretty awful for these as they are mostly implemented as generic bit twiddling ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272508
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Sean Silva [Sun, 12 Jun 2016 09:16:39 +0000 (09:16 +0000)]
[PM] Port DeadArgumentElimination to the new PM
The approach taken here follows r267631.
deadarghaX0r should be easy to port when the time comes to add new-PM
support to bugpoint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272507
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Amaury Sechet [Sun, 12 Jun 2016 07:56:21 +0000 (07:56 +0000)]
Change () to (void) in the C API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272506
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Sean Silva [Sun, 12 Jun 2016 07:48:51 +0000 (07:48 +0000)]
[PM] Port ReversePostOrderFunctionAttrs to the new PM
Below are my super rough notes when porting. They can probably serve as
a basic guide for porting other passes to the new PM. As I port more
passes I'll expand and generalize this and make a proper
docs/HowToPortToNewPassManager.rst document. There is also missing
documentation for general concepts and API's in the new PM which will
require some documentation.
Once there is proper documentation in place we can put up a list of
passes that have to be ported and game-ify/crowdsource the rest of the
porting (at least of the middle end; the backend is still unclear).
I will however be taking personal responsibility for ensuring that the
LLD/ELF LTO pipeline is ported in a timely fashion. The remaining passes
to be ported are (do something like
`git grep "<the string in the bullet point below>"` to find the pass):
General Scalar:
[ ] Simplify the CFG
[ ] Jump Threading
[ ] MemCpy Optimization
[ ] Promote Memory to Register
[ ] MergedLoadStoreMotion
[ ] Lazy Value Information Analysis
General IPO:
[ ] Dead Argument Elimination
[ ] Deduce function attributes in RPO
Loop stuff / vectorization stuff:
[ ] Alignment from assumptions
[ ] Canonicalize natural loops
[ ] Delete dead loops
[ ] Loop Access Analysis
[ ] Loop Invariant Code Motion
[ ] Loop Vectorization
[ ] SLP Vectorizer
[ ] Unroll loops
Devirtualization / CFI:
[ ] Cross-DSO CFI
[ ] Whole program devirtualization
[ ] Lower bitset metadata
CGSCC passes:
[ ] Function Integration/Inlining
[ ] Remove unused exception handling info
[ ] Promote 'by reference' arguments to scalars
Please let me know if you are interested in working on any of the passes
in the above list (e.g. reply to the post-commit thread for this patch).
I'll probably be tackling "General Scalar" and "General IPO" first FWIW.
Steps as I port "Deduce function attributes in RPO"
---------------------------------------------------
(note: if you are doing any work based on these notes, please leave a
note in the post-commit review thread for this commit with any
improvements / suggestions / incompleteness you ran into!)
Note: "Deduce function attributes in RPO" is a module pass.
1. Do preparatory refactoring.
Do preparatory factoring. In this case all I had to do was to pull out a static helper (r272503).
(TODO: give more advice here e.g. if pass holds state or something)
2. Rename the old pass class.
llvm/lib/Transforms/IPO/FunctionAttrs.cpp
Rename class ReversePostOrderFunctionAttrs -> ReversePostOrderFunctionAttrsLegacyPass
in preparation for adding a class ReversePostOrderFunctionAttrs as the pass in the new PM.
(edit: actually wait what? The new class name will be
ReversePostOrderFunctionAttrsPass, so it doesn't conflict. So this step is
sort of useless churn).
llvm/include/llvm/InitializePasses.h
llvm/lib/LTO/LTOCodeGenerator.cpp
llvm/lib/Transforms/IPO/IPO.cpp
llvm/lib/Transforms/IPO/FunctionAttrs.cpp
Rename initializeReversePostOrderFunctionAttrsPass -> initializeReversePostOrderFunctionAttrsLegacyPassPass
(note that the "PassPass" thing falls out of `s/ReversePostOrderFunctionAttrs/ReversePostOrderFunctionAttrsLegacyPass/`)
Note that the INITIALIZE_PASS macro is what creates this identifier name, so renaming the class requires this renaming too.
Note that createReversePostOrderFunctionAttrsPass does not need to be
renamed since its name is not generated from the class name.
3. Add the new PM pass class.
In the new PM all passes need to have their
declaration in a header somewhere, so you will often need to add a header.
In this case
llvm/include/llvm/Transforms/IPO/FunctionAttrs.h is already there because
PostOrderFunctionAttrsPass was already ported.
The file-level comment from the .cpp file can be used as the file-level
comment for the new header. You may want to tweak the wording slightly
from "this file implements" to "this file provides" or similar.
Add declaration for the new PM pass in this header:
class ReversePostOrderFunctionAttrsPass
: public PassInfoMixin<ReversePostOrderFunctionAttrsPass> {
public:
PreservedAnalyses run(Module &M, AnalysisManager<Module> &AM);
};
Its name should end with `Pass` for consistency (note that this doesn't
collide with the names of most old PM passes). E.g. call it
`<name of the old PM pass>Pass`.
Also, move the doxygen comment from the old PM pass to the declaration of
this class in the header.
Also, include the declaration for the new PM class
`llvm/Transforms/IPO/FunctionAttrs.h` at the top of the file (in this case,
it was already done when the other pass in this file was ported).
Now define the `run` method for the new class.
The main things here are:
a) Use AM.getResult<...>(M) to get results instead of `getAnalysis<...>()`
b) If the old PM pass would have returned "false" (i.e. `Changed ==
false`), then you should return PreservedAnalyses::all();
c) In the old PM getAnalysisUsage method, observe the calls
`AU.addPreserved<...>();`.
In the case `Changed == true`, for each preserved analysis you should do
call `PA.preserve<...>()` on a PreservedAnalyses object and return it.
E.g.:
PreservedAnalyses PA;
PA.preserve<CallGraphAnalysis>();
return PA;
Note that calls to skipModule/skipFunction are not supported in the new PM
currently, so optnone and optimization bisect support do not work. You can
just drop those calls for now.
4. Add the pass to the new PM pass registry to make it available in opt.
In llvm/lib/Passes/PassBuilder.cpp add a #include for your header.
`#include "llvm/Transforms/IPO/FunctionAttrs.h"`
In this case there is already an include (from when
PostOrderFunctionAttrsPass was ported).
Add your pass to llvm/lib/Passes/PassRegistry.def
In this case, I added
`MODULE_PASS("rpo-functionattrs", ReversePostOrderFunctionAttrsPass())`
The string is from the `INITIALIZE_PASS*` macros used in the old pass
manager.
Then choose a test that uses the pass and use the new PM `-passes=...` to
run it.
E.g. in this case there is a test that does:
; RUN: opt < %s -basicaa -functionattrs -rpo-functionattrs -S | FileCheck %s
I have added the line:
; RUN: opt < %s -aa-pipeline=basic-aa -passes='require<targetlibinfo>,cgscc(function-attrs),rpo-functionattrs' -S | FileCheck %s
The `-aa-pipeline=basic-aa` and
`require<targetlibinfo>,cgscc(function-attrs)` are what is needed to run
functionattrs in the new PM (note that in the new PM "functionattrs"
becomes "function-attrs" for some reason). This is just pulled from
`readattrs.ll` which contains the change from when functionattrs was ported
to the new PM.
Adding rpo-functionattrs causes the pass that was just ported to run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272505
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Amaury Sechet [Sun, 12 Jun 2016 06:17:24 +0000 (06:17 +0000)]
Make sure we have a Add/Remove/Has function for various thing that can have attribute.
Summary: This also deprecated the get attribute function familly.
Reviewers: Wallbraker, whitequark, joker.eph, echristo, rafael, jyknight
Subscribers: axw, joker.eph, llvm-commits
Differential Revision: http://reviews.llvm.org/D19181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272504
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Sean Silva [Sun, 12 Jun 2016 05:44:51 +0000 (05:44 +0000)]
Factor out a helper. NFC
Prep for porting to new PM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272503
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Craig Topper [Sun, 12 Jun 2016 04:48:00 +0000 (04:48 +0000)]
[X86] Pre-allocate some of the shuffle mask SmallVectors in the auto upgrade code instead of calling push_back in a loop. This removes the need to check if the vector needs to grow on each iteration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272501
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Craig Topper [Sun, 12 Jun 2016 04:14:13 +0000 (04:14 +0000)]
[AVX512] Remove the masked palignr intrinsics that I forgot to remove when I added auto-upgrade code to turn them into shufflevectors and selects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272497
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Craig Topper [Sun, 12 Jun 2016 03:10:47 +0000 (03:10 +0000)]
[X86] Greatly simplify the llvm.x86.avx.vpermil.* auto-upgrade code. We can fully derive everything using types of the intrinsic arguments rather than writing separate loops for each intrinsic. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272496
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Eli Friedman [Sun, 12 Jun 2016 02:11:20 +0000 (02:11 +0000)]
[MergedLoadStoreMotion] Use correct helper for load hoist safety.
It isn't legal to hoist a load past a call which might not return;
even if it doesn't throw, it could, for example, call exit().
Fixes http://llvm.org/PR27953.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272495
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Craig Topper [Sun, 12 Jun 2016 01:41:06 +0000 (01:41 +0000)]
[X86] Move tests for llvm.x86.avx.vpermil.* intrinsics to a -upgrade test since they are autoupgraded to shufflevector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272494
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Craig Topper [Sun, 12 Jun 2016 01:05:59 +0000 (01:05 +0000)]
[X86,IR] Make use of the CreateShuffleVector form that takes an ArrayRef<uint32_t> to avoid the need to manually create a bunch of Constants and a ConstantVector. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272493
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Craig Topper [Sun, 12 Jun 2016 00:41:19 +0000 (00:41 +0000)]
[IR] Require ArrayRef of 'uint32_t' instead of 'int' for the mask argument for one of the signatures of CreateShuffleVector. This better emphasises that you can't use it for the -1 as undef behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272491
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Eli Friedman [Sat, 11 Jun 2016 21:48:25 +0000 (21:48 +0000)]
[LICM] Make isGuaranteedToExecute more accurate.
Summary:
Make isGuaranteedToExecute use the
isGuaranteedToTransferExecutionToSuccessor helper, and make that helper
a bit more accurate.
There's a potential performance impact here from assuming that arbitrary
calls might not return. This probably has little impact on loads and
stores to a pointer because most things alias analysis can reason about
are dereferenceable anyway. The other impacts, like less aggressive
hoisting of sdiv by a variable and less aggressive hoisting around
volatile memory operations, are unlikely to matter for real code.
This also impacts SCEV, which uses the same helper. It's a minor
improvement there because we can tell that, for example, memcpy always
returns normally. Strictly speaking, it's also introducing
a bug, but it's not any worse than everywhere else we assume readonly
functions terminate.
Fixes http://llvm.org/PR27857.
Reviewers: hfinkel, reames, chandlerc, sanjoy
Subscribers: broune, llvm-commits
Differential Revision: http://reviews.llvm.org/D21167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272489
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Simon Pilgrim [Sat, 11 Jun 2016 20:39:21 +0000 (20:39 +0000)]
[X86] Updated test checks script to generalise LCPI symbol refs
The script now replace '.LCPI888_8' style asm symbols with the {{\.LCPI.*}} re pattern - this helps stop hardcoded symbols in 32-bit x86 tests changing with every edit of the file
Refreshed some tests to demonstrate the new check
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272488
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Simon Pilgrim [Sat, 11 Jun 2016 19:23:02 +0000 (19:23 +0000)]
[CostModel][X86][SSE] Updated costs for vector BITREVERSE ops on SSSE3+ targets
To account for the fast PSHUFB implementation now available
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272484
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Xinliang David Li [Sat, 11 Jun 2016 18:35:40 +0000 (18:35 +0000)]
[MBP] Code cleanup /NFC
This is one of the patches to clean up the code so that
it is in a better form to make future enhancements easier.
In htis patch, the logic to collect viable successors are
extrated as a helper to unclutter the caller which gets very
large recenty. Also cleaned up BP adjustment code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272482
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Vassil Vassilev [Sat, 11 Jun 2016 17:20:53 +0000 (17:20 +0000)]
[CMake] Allow LLVM to be embedded and built in a subfolder as part of another project.
Patch by Bertrand Bellenot!
Reviewed by Chris Bieneman and me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272481
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Vikram TV [Sat, 11 Jun 2016 16:41:10 +0000 (16:41 +0000)]
Delay dominator updation while cloning loop.
Summary:
Dominator updation fails for a loop inserted with a new basicblock.
A block required by DT to set the IDom might not have been cloned yet. This is because there is no predefined ordering of loop blocks (except for the header block which should be the first block in the list).
The patch first creates DT nodes for the cloned blocks and then separately updates the DT in a follow-on loop.
Reviewers: anemet, dberlin
Subscribers: dberlin, llvm-commits
Differential Revision: http://reviews.llvm.org/D20899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272479
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Simon Pilgrim [Sat, 11 Jun 2016 15:44:13 +0000 (15:44 +0000)]
[X86][SSSE3] Added PSHUFB LUT implementation of BITREVERSE
PSHUFB can speed up BITREVERSE of byte vectors by performing LUT on the low/high nibbles separately and ORing the results. Wider integer vector types are already BSWAP'd beforehand so also make use of this approach.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272477
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Simon Pilgrim [Sat, 11 Jun 2016 14:34:10 +0000 (14:34 +0000)]
Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272476
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Craig Topper [Sat, 11 Jun 2016 13:57:08 +0000 (13:57 +0000)]
[AVX512] Re-generate v8i64 shuffle test now that we use pshufd for some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272474
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Craig Topper [Sat, 11 Jun 2016 13:43:21 +0000 (13:43 +0000)]
[AVX512] Lower v8i64 and v16i32 to pshufd when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272473
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Craig Topper [Sat, 11 Jun 2016 13:43:18 +0000 (13:43 +0000)]
[X86] Remove GCC builtin name from some intrinsics that are no longer used by clang. A future commit can remove the intrinsics entirely.
Some of these have been unused for a long time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272472
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Simon Pilgrim [Sat, 11 Jun 2016 13:38:28 +0000 (13:38 +0000)]
[X86][SSE] Added PSLLDQ/PSRLDQ as a target shuffle type
Ensure that PALIGNR/PSLLDQ/PSRLDQ are byte vectors so that they can be correctly decoded for target shuffle combining
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272471
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Simon Pilgrim [Sat, 11 Jun 2016 13:18:21 +0000 (13:18 +0000)]
[X86][AVX2] Added PSLLDQ/PSRLDQ shuffle combining tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272469
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Simon Pilgrim [Sat, 11 Jun 2016 12:54:37 +0000 (12:54 +0000)]
[X86][SSE] Use vXi8 return type for PSLLDQ/PSRLDQ instructions
These are byte shift instructions and it will make shuffle combining a lot more straightforward if we can assume a vXi8 vector of bytes so decoded shuffle masks match the return type's number of elements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272468
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Simon Pilgrim [Sat, 11 Jun 2016 11:18:38 +0000 (11:18 +0000)]
[X86][AVX512] Tidied up VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 comment generation
Now matches other shuffles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272464
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Chandler Carruth [Sat, 11 Jun 2016 09:13:00 +0000 (09:13 +0000)]
Try a bit harder to remove the signed and unsigned comparison warning.
Hopefully this time it actually works and stays away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272463
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Chandler Carruth [Sat, 11 Jun 2016 08:19:59 +0000 (08:19 +0000)]
Use a two-level cast through an intptr_t, and make them C-style casts.
This shouldn't have any functional difference, but it appears to be the
pattern used for other methods on DynamicLibrary, and it should avoid
the -Wpedantic warning on one of the build bots about the direct
reinterpret_cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272461
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Chandler Carruth [Sat, 11 Jun 2016 08:12:17 +0000 (08:12 +0000)]
Add a using declaration so that the overrides don't hide some of the
base class methods.
This was caught by GCC's -Woverloaded-virtual, not sure why it wasn't
caught by Clang's. =/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272460
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Chandler Carruth [Sat, 11 Jun 2016 08:02:01 +0000 (08:02 +0000)]
Compare to an unsigned literal to avoid a -Wsign-compare warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272459
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Chandler Carruth [Sat, 11 Jun 2016 08:01:57 +0000 (08:01 +0000)]
Use const_cast to cast away constness. This silences a warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272458
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NAKAMURA Takumi [Sat, 11 Jun 2016 06:37:28 +0000 (06:37 +0000)]
DebugInfoPDBTests:MappedBlockStreamTest.TestWriteThenRead: Avoid assigning temporary object to ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272457
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Lang Hames [Sat, 11 Jun 2016 05:47:04 +0000 (05:47 +0000)]
[MCJIT] Update MCJIT and get the fibonacci example working again.
MCJIT will now set the DataLayout on a module when it is added to the JIT,
rather than waiting until it is codegen'd, and the runFunction method will
finalize the module containing the function to be run before running it.
The fibonacci example has been updated to include and link against MCJIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272455
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Craig Topper [Sat, 11 Jun 2016 03:27:42 +0000 (03:27 +0000)]
[AVX512] Add support for lowering v32i16 shuffles with repeated lanes. This allows us to create 512-bit PSHUFLW/PSHUFHW.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272450
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Craig Topper [Sat, 11 Jun 2016 03:27:37 +0000 (03:27 +0000)]
[AVX512] No need to check for BWI being enabled before lowering v32i16 and v64i8 shuffles. If we get this far the types are already legal which means BWI must be enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272449
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Matthias Braun [Sat, 11 Jun 2016 00:31:28 +0000 (00:31 +0000)]
LiveIntervalAnalysis: findLastUseBefore() must ignore undef uses.
undef uses are no real uses of a register and must be ignored by
findLastUseBefore() so that handleMove() does not produce invalid live
intervals in some cases.
This fixed http://llvm.org/PR28083
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272446
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Qin Zhao [Fri, 10 Jun 2016 22:28:55 +0000 (22:28 +0000)]
[esan|cfrag] Handle complex GEP instr in the cfrag tool
Summary:
Iterates all (except the first and the last) operands within each GEP
instruction for instrumentation.
Adds test struct_field_gep.ll.
Reviewers: aizatsky
Subscribers: vitalybuka, zhaoqin, kcc, eugenis, bruening, llvm-commits
Differential Revision: http://reviews.llvm.org/D21242
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272442
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Zachary Turner [Fri, 10 Jun 2016 22:12:18 +0000 (22:12 +0000)]
Try again to fix this endianness issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272440
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Michael Zolotukhin [Fri, 10 Jun 2016 22:03:56 +0000 (22:03 +0000)]
Don't try to rotate a loop more than once - we never do this anyway.
Summary:
I can't find a case where we can rotate a loop more than once, and it looks
like we never do this. To rotate a loop following conditions should be met:
1) its header should be exiting
2) its latch shouldn't be exiting
But after the first rotation the header becomes the new latch, so this
condition can never be true any longer.
Tested on with an assert on LNT testsuite and make check.
Reviewers: hfinkel, sanjoy
Subscribers: sebpop, sanjoy, llvm-commits, mzolotukhin
Differential Revision: http://reviews.llvm.org/D20181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272439
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Zachary Turner [Fri, 10 Jun 2016 21:47:26 +0000 (21:47 +0000)]
[pdb] Fix issues with pdb writing.
This fixes an alignment issue by forcing all cached allocations
to be 8 byte aligned, and also fixes an issue arising on big
endian systems by writing ulittle32_t's instead of uint32_t's
in the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272437
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Sebastian Pop [Fri, 10 Jun 2016 21:36:41 +0000 (21:36 +0000)]
MemorySSA: fix memory access local dominance function for live on entry
A memory access defined on function entry cannot be locally dominated by another memory access.
The patch was split from http://reviews.llvm.org/D19338 which exposes the problem.
Differential Revision: http://reviews.llvm.org/D21039
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272436
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Sanjoy Das [Fri, 10 Jun 2016 21:18:39 +0000 (21:18 +0000)]
[STLExtras] Introduce and use llvm::count_if; NFC
(This is split out from was D21115)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272435
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Quentin Colombet [Fri, 10 Jun 2016 20:50:35 +0000 (20:50 +0000)]
[IRTranslator] Support the translation of or.
Now or instructions get translated into G_OR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272433
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Quentin Colombet [Fri, 10 Jun 2016 20:50:33 +0000 (20:50 +0000)]
[IRTranslator] Rework the comments for the methods to translate.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272432
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Quentin Colombet [Fri, 10 Jun 2016 20:50:18 +0000 (20:50 +0000)]
[IRTranslator] Refactor to expose a translateBinaryOp method.
This method will be used for every binary operation.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272431
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Chad Rosier [Fri, 10 Jun 2016 20:49:18 +0000 (20:49 +0000)]
[AArch64] Move comments closer to relevant check. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272430
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Chad Rosier [Fri, 10 Jun 2016 20:47:14 +0000 (20:47 +0000)]
[AArch64] Refactor a check earlier. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272429
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Sanjay Patel [Fri, 10 Jun 2016 20:33:50 +0000 (20:33 +0000)]
[x86] enable bitcasted fabs/fneg transforms
The vector cases don't change because we already have folds in X86ISelLowering
to look through and remove bitcasts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272427
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Etienne Bergeron [Fri, 10 Jun 2016 20:24:38 +0000 (20:24 +0000)]
[CodeGen] Fix PrologEpilogInserter to avoid duplicate allocation of SEH structs
Summary:
When stack-protection is activated and WinEH exceptions is used,
the EHRegNode (exception handling registration) is allocated twice on the stack.
This was not breaking anything except loosing space on the stack.
```
D:\src\llvm\examples>llc exc2.ll -debug-only=pei
alloc FI(0) at SP[-24]
alloc FI(1) at SP[-48] <<-- Allocated
alloc FI(1) at SP[-72] <<-- Allocated twice!?
alloc FI(2) at SP[-76]
alloc FI(4) at SP[-80]
alloc FI(3) at SP[-84]
```
Reviewers: rnk, majnemer
Subscribers: chrisha, llvm-commits
Differential Revision: http://reviews.llvm.org/D21188
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272426
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Nico Weber [Fri, 10 Jun 2016 20:06:03 +0000 (20:06 +0000)]
Remove a few gendered pronouns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272422
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Evgeniy Stepanov [Fri, 10 Jun 2016 20:03:20 +0000 (20:03 +0000)]
Disable MSan-hostile loop unswitching.
Loop unswitching may cause MSan false positive when the unswitch
condition is not guaranteed to execute.
This is very similar to ASan and TSan special case in
llvm::isSafeToSpeculativelyExecute (they don't like speculative loads
and stores), but for branch instructions.
This is a workaround for PR28054.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272421
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Evgeniy Stepanov [Fri, 10 Jun 2016 20:03:17 +0000 (20:03 +0000)]
Move isGuaranteedToExecute out of LICM.
Also rename LICMSafetyInfo to LoopSafetyInfo.
Both will be used in LoopUnswitch in a separate change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272420
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Zhan Jun Liau [Fri, 10 Jun 2016 19:58:10 +0000 (19:58 +0000)]
[SystemZ] Support Compare and Traps
Support and generate Compare and Traps like CRT, CIT, etc.
Support Trap as legal DAG opcodes and generate "j .+2" for them by default.
Add support for Conditional Traps and use the If Converter to convert them into
the corresponding compare and trap opcodes.
Differential Revision: http://reviews.llvm.org/D21155
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272419
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Tom Stellard [Fri, 10 Jun 2016 19:26:38 +0000 (19:26 +0000)]
AMDGPU/SI: Don't use fixup_si_rodata for scratch rsrc relocations
Summary:
We need to set the fixup type to FK_Data_4 for the
SCRATCH_RSRC_DWORD[01] symbols, since these require absolute
relocations, and fixup_si_rodata is for relative relocations.
Reviewers: arsenm, kzhuravl
Subscribers: arsenm, kzhuravl, llvm-commits
Differential Revision: http://reviews.llvm.org/D21153
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272417
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Mehdi Amini [Fri, 10 Jun 2016 19:14:01 +0000 (19:14 +0000)]
Move CodeGen test from Generic to X86 specific directory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272416
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Mehdi Amini [Fri, 10 Jun 2016 18:37:21 +0000 (18:37 +0000)]
Interprocedural Register Allocation (IPRA): add a Transformation Pass
Adds a MachineFunctionPass that scans the body to find calls, and
update the register mask with the one saved by the
RegUsageInfoCollector analysis in PhysicalRegisterUsageInfo.
Patch by Vivek Pandya <vivekvpandya@gmail.com>
Differential Revision: http://reviews.llvm.org/D21180
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272414
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Sanjay Patel [Fri, 10 Jun 2016 18:05:55 +0000 (18:05 +0000)]
[x86] add test for PR28044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272411
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Chad Rosier [Fri, 10 Jun 2016 17:59:22 +0000 (17:59 +0000)]
Add a period. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272410
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Chad Rosier [Fri, 10 Jun 2016 17:58:01 +0000 (17:58 +0000)]
Fix whitespace. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272409
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Saleem Abdulrasool [Fri, 10 Jun 2016 17:33:28 +0000 (17:33 +0000)]
test: split test into two files
Split up the test cases into two inputs as per post-commit review comments from
Renato. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272408
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Michael Kuperstein [Fri, 10 Jun 2016 17:01:05 +0000 (17:01 +0000)]
[X86] Add costs for SSE zext/sext to v4i64 to TTI
The costs are somewhat hand-wavy, but should be much closer to the truth
than what we get from BasicTTI.
Differential Revision: http://reviews.llvm.org/D21156
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272406
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Mehdi Amini [Fri, 10 Jun 2016 16:19:46 +0000 (16:19 +0000)]
Interprocedural Register Allocation (IPRA) Analysis
Add an option to enable the analysis of MachineFunction register
usage to extract the list of clobbered registers.
When enabled, the CodeGen order is changed to be bottom up on the Call
Graph.
The analysis is split in two parts, RegUsageInfoCollector is the
MachineFunction Pass that runs post-RA and collect the list of
clobbered registers to produce a register mask.
An immutable pass, RegisterUsageInfo, stores the RegMask produced by
RegUsageInfoCollector, and keep them available. A future tranformation
pass will use this information to update every call-sites after
instruction selection.
Patch by Vivek Pandya <vivekvpandya@gmail.com>
Differential Revision: http://reviews.llvm.org/D20769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272403
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Evandro Menezes [Fri, 10 Jun 2016 16:00:18 +0000 (16:00 +0000)]
[AArch64] Add preferred alignments for Exynos M1
Differential Revision: http://reviews.llvm.org/D21203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272400
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Krzysztof Parzyszek [Fri, 10 Jun 2016 15:43:18 +0000 (15:43 +0000)]
[Hexagon] Remove incorrect offset scaling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272399
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Sanjay Patel [Fri, 10 Jun 2016 15:30:52 +0000 (15:30 +0000)]
[x86] fix test attributes and autogenerate checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272398
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Sanjay Patel [Fri, 10 Jun 2016 15:17:54 +0000 (15:17 +0000)]
[x86] add missing tests for fcmp ueq/one
Somehow, the codegen logic for these sequences has gone completely untested
until now (note the 2 compare instructions generated per test).
There's also an *Intel* AVX optimization opportunity exposed in these cases
and the existing tests. Intel's (but not AMD's) AVX spec shows that extra FP
predicates were added, so a single comparison should always be sufficient,
and operand commutation should never be necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272397
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Sanjay Patel [Fri, 10 Jun 2016 14:48:50 +0000 (14:48 +0000)]
[x86] regenerate checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272396
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Matthew Simpson [Fri, 10 Jun 2016 14:33:30 +0000 (14:33 +0000)]
Reapply "[TTI] Refine default cost for interleaved load groups with gaps"
This reapplies commit r272385 with a fix. The build was failing when compiled
with gcc, but not with clang. With the fix, we now get the data layout from the
current TTI implementation, which will hopefully solve the issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272395
91177308-0d34-0410-b5e6-
96231b3b80d8