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Craig Topper [Fri, 15 Dec 2017 19:35:22 +0000 (19:35 +0000)]
[SelectionDAG][X86] Fix insert_vector_elt lowering for v32i1/v64i1 with non-constant index
Summary:
Currently we don't handle v32i1/v64i1 insert_vector_elt correctly as we fail to look at the number of elements closely and assume it can only be v16i1 or v8i1.
We also can't type legalize v64i1 insert_vector_elt correctly on KNL due to the type not being byte addressable as required by the legalizing through memory accesses path requires.
For the first issue, the patch now tries to pick a 512-bit register with the correct number of elements and promotes to that.
For the second issue, we now extend the vector to a byte addressable type, do the stores to memory, load the two halves, and then truncate the halves back to the original type. Technically since we changed the type, we may not need two loads, but actually checking that is more work and for the v64i1 case we do need them.
Reviewers: RKSimon, delena, spatel, zvi
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40942
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320849
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Sean Fertile [Fri, 15 Dec 2017 19:29:12 +0000 (19:29 +0000)]
[Memcpy Loop Lowering] Insert loop BB inbetween the split BB.
The original memcpy expansion inserted the loop basic block inbetween
the 2 new basic blocks created by splitting the original block the memcpy
call was in. This commit makes the new memcpy expansion do the same to keep the
layout of the IR matching between the old and new implementations.
Differential Review: https://reviews.llvm.org/D41197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320848
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Craig Topper [Fri, 15 Dec 2017 19:01:51 +0000 (19:01 +0000)]
[X86] Add 'Requires<[In64BitMode]>' to a bunch of instructions that only have memory and immediate operands.
The asm parser wasn't preventing these from being accepted in 32-bit mode. Instructions that use a GR64 register are protected by the parser rejecting the register in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320846
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Craig Topper [Fri, 15 Dec 2017 19:01:50 +0000 (19:01 +0000)]
[X86] Change BNDLDX to use anymem instead of i64mem for itsmemory operand.
This instruction doesn't access memory. It juse use a similar looking memory encoding. Don't require Intel syntax to put "qword ptr" in front of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320845
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Craig Topper [Fri, 15 Dec 2017 19:01:49 +0000 (19:01 +0000)]
[X86] Remove the 'Requires' In64BitMode/Not64BitMode from the LWP instructions.
These aren't doing anything due to a top level "let Predicates =". I think the GR32/GR64 register class protects these anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320844
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Craig Topper [Fri, 15 Dec 2017 19:01:48 +0000 (19:01 +0000)]
[X86] Remove the 'Requires<[In64BitMode]>' from SHSTK instructions.
This has no effect due to a top level "let Predicates =" around the instructions. But its also not required because the GR64 usage in the instruction guarantees it can never match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320843
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Sanjay Patel [Fri, 15 Dec 2017 18:54:29 +0000 (18:54 +0000)]
[TargetLibraryInfo] fix documentation comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320842
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Sanjay Patel [Fri, 15 Dec 2017 18:34:45 +0000 (18:34 +0000)]
[CodeGen] fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320840
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Evandro Menezes [Fri, 15 Dec 2017 18:26:54 +0000 (18:26 +0000)]
[AArch64] Fix typo in the ASIMD instruction optimization pass
Fix typo in the representative instruction replacement.
Also, fix formatting and reword some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320839
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Sanjay Patel [Fri, 15 Dec 2017 18:25:13 +0000 (18:25 +0000)]
fix typo in comment and remove inaccurate comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320838
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Andrew V. Tischenko [Fri, 15 Dec 2017 18:13:05 +0000 (18:13 +0000)]
Fix for bug PR35549 - Repeated schedule comments.
Differential Revision: https://reviews.llvm.org/D40960
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320837
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Jun Bum Lim [Fri, 15 Dec 2017 18:12:49 +0000 (18:12 +0000)]
Revert "Re-commit : [LICM] Allow sinking when foldable in loop"
This reverts commit r320833.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320836
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Sanjay Patel [Fri, 15 Dec 2017 18:09:33 +0000 (18:09 +0000)]
[CodeGen] fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320835
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Jun Bum Lim [Fri, 15 Dec 2017 17:58:59 +0000 (17:58 +0000)]
Re-commit : [LICM] Allow sinking when foldable in loop
This recommit r320823 after fixing a test failure.
Original commit message:
Continue trying to sink an instruction if its users in the loop is foldable.
This will allow the instruction to be folded in the loop by decoupling it from
the user outside of the loop.
Reviewers: hfinkel, majnemer, davidxl, efriedma, danielcdh, bmakam, mcrosier
Reviewed By: hfinkel
Subscribers: javed.absar, bmakam, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D37076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320833
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Michael Trent [Fri, 15 Dec 2017 17:57:40 +0000 (17:57 +0000)]
Updated llvm-objdump to display local relocations in Mach-O binaries
Summary:
llvm-objdump's Mach-O parser was updated in r306037 to display external
relocations for MH_KEXT_BUNDLE file types. This change extends the Macho-O
parser to display local relocations for MH_PRELOAD files. When used with
the -macho option relocations will be displayed in a historical format.
All tests are passing for llvm, clang, and lld. llvm-objdump builds without
compiler warnings.
rdar://
35778019
Reviewers: enderby
Reviewed By: enderby
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320832
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Craig Topper [Fri, 15 Dec 2017 17:22:58 +0000 (17:22 +0000)]
[X86] Fix XSAVE64 and similar instructions to not be allowed by the assembler in 32-bit mode.
There was a top level "let Predicates =" in the .td file that was overriding the Requires on each instruction.
I've added an assert to the code emitter to catch more cases like this. I'm sure this isn't the only place where the right predicates aren't being applied. This assert already found that we don't block btq/btsq/btrq in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320830
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Jun Bum Lim [Fri, 15 Dec 2017 16:35:09 +0000 (16:35 +0000)]
Revert "[LICM] Allow sinking when foldable in loop"
This reverts commit r320823.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320828
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Francis Visoiu Mistrih [Fri, 15 Dec 2017 16:33:45 +0000 (16:33 +0000)]
[CodeGen] Print stack object references as %(fixed-)stack.0 in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`%stack.0` instead of `<fi#0>`, and `%fixed-stack.0` instead of
`<fi#-4>` (supposing there are 4 fixed stack objects).
Only debug syntax is affected.
Differential Revision: https://reviews.llvm.org/D41027
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320827
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Eugene Leviant [Fri, 15 Dec 2017 16:27:33 +0000 (16:27 +0000)]
[ThinLTO] Disallow multiple prevailing defs
https://reviews.llvm.org/D41291
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320825
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Craig Topper [Fri, 15 Dec 2017 16:22:20 +0000 (16:22 +0000)]
[X86] Widen (v2i32 (fp_to_uint v2f64)) to (v8i32 (fp_to_uint v8f64)) during legalization if we have AVX512F, but not VLX. NFC
Previously we widened it using isel patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320824
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Jun Bum Lim [Fri, 15 Dec 2017 16:09:54 +0000 (16:09 +0000)]
[LICM] Allow sinking when foldable in loop
Summary:
Continue trying to sink an instruction if its users in the loop is foldable.
This will allow the instruction to be folded in the loop by decoupling it from
the user outside of the loop.
Reviewers: hfinkel, majnemer, davidxl, efriedma, danielcdh, bmakam, mcrosier
Reviewed By: hfinkel
Subscribers: javed.absar, bmakam, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D37076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320823
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Sam Parker [Fri, 15 Dec 2017 15:30:39 +0000 (15:30 +0000)]
[ARM] Some DAG combine tests
Add some more and and shift load combine tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320822
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Francis Visoiu Mistrih [Fri, 15 Dec 2017 15:17:18 +0000 (15:17 +0000)]
[MIR] Add support for missing CFI directives
The following CFI directives are suported by MC but not by MIR:
* .cfi_rel_offset
* .cfi_adjust_cfa_offset
* .cfi_escape
* .cfi_remember_state
* .cfi_restore_state
* .cfi_undefined
* .cfi_register
* .cfi_window_save
Add support for printing, parsing and update tests.
Differential Revision: https://reviews.llvm.org/D41230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320819
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Simon Pilgrim [Fri, 15 Dec 2017 14:37:28 +0000 (14:37 +0000)]
[X86] Add RTM schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320815
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Haicheng Wu [Fri, 15 Dec 2017 14:34:41 +0000 (14:34 +0000)]
[InlineCost] Find repeated loads in the callee
SROA analysis of InlineCost can figure out that some stores can be removed
after inlining and then the repeated loads clobbered by these stores are also
free. This patch finds these clobbered loads and adjust the inline cost
accordingly.
Differential Revision: https://reviews.llvm.org/D33946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320814
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Simon Pilgrim [Fri, 15 Dec 2017 14:22:15 +0000 (14:22 +0000)]
[X86] Add MWAITX/MONITORX schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320812
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Nemanja Ivanovic [Fri, 15 Dec 2017 14:17:45 +0000 (14:17 +0000)]
Fix the second build bot break introduced by r320791.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320811
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Simon Pilgrim [Fri, 15 Dec 2017 14:02:35 +0000 (14:02 +0000)]
[X86] Add XOP schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320810
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Nemanja Ivanovic [Fri, 15 Dec 2017 11:47:48 +0000 (11:47 +0000)]
Fix code causing fallthrough warnings in the PPC back end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320806
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Simon Pilgrim [Fri, 15 Dec 2017 11:32:31 +0000 (11:32 +0000)]
[X86] Add AVX512 VPOPCNTDQ schedule tests
Demonstrates how to perform full coverage avx512 schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320805
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Alex Bradbury [Fri, 15 Dec 2017 10:20:51 +0000 (10:20 +0000)]
[RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero
c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C.
This patch adds uimmlog2xlennonzero to reflect this constraint as well as
tests.
Differential Revision: https://reviews.llvm.org/D41216
Patch by Shiva Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320799
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Nemanja Ivanovic [Fri, 15 Dec 2017 09:51:34 +0000 (09:51 +0000)]
Fix the build bot break introduced by r320791.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320798
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Alex Bradbury [Fri, 15 Dec 2017 09:47:01 +0000 (09:47 +0000)]
[RISCV] Enable emission of alias instructions by default
This patch switches the default for -riscv-no-aliases to false
and updates all affected MC and CodeGen tests. As recommended in
D41071, MC tests use the canonical instructions and the CodeGen
tests use the aliases.
Additionally, for the f and d instructions with rounding mode,
the tests for the aliased versions are moved and tightened such
that they can actually detect if alias emission is enabled.
(see D40902 for context)
Differential Revision: https://reviews.llvm.org/D41225
Patch by Mario Werner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320797
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Fedor Sergeev [Fri, 15 Dec 2017 09:32:11 +0000 (09:32 +0000)]
[PM] port Rewrite Statepoints For GC to the new pass manager.
Summary:
The port is nearly straightforward.
The only complication is related to the analyses handling,
since one of the analyses used in this module pass is domtree,
which is a function analysis. That requires asking for the results
of each function and disallows a single interface for run-on-module
pass action.
Decided to copy-paste the main body of this pass.
Most of its code is requesting analyses anyway, so not that much
of a copy-paste.
The rest of the code movement is to transform all the implementation
helper functions like stripNonValidData into non-member statics.
Extended all the related LLVM tests with new-pass-manager use.
No failures.
Reviewers: sanjoy, anna, reames
Reviewed By: anna
Subscribers: skatkov, llvm-commits
Differential Revision: https://reviews.llvm.org/D41162
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320796
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Roger Ferrer Ibanez [Fri, 15 Dec 2017 09:24:46 +0000 (09:24 +0000)]
[ARM] Add tests for D34515
This is NFC and a preparatory step for D34515.
Differential Revision: https://reviews.llvm.org/D41122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320795
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Eugene Leviant [Fri, 15 Dec 2017 09:18:21 +0000 (09:18 +0000)]
[LLVMgold] Don't set undefined symbol as prevailing
Differential revision: https://reviews.llvm.org/D41113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320794
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Nemanja Ivanovic [Fri, 15 Dec 2017 07:27:53 +0000 (07:27 +0000)]
[PowerPC] Convert r+r instructions to r+i (pre and post RA)
This patch adds the necessary infrastructure to convert instructions that
take two register operands to those that take a register and immediate if
the necessary operand is produced by a load-immediate. Furthermore, it uses
this infrastructure to perform such conversions twice - first at MachineSSA
and then pre-emit.
There are a number of reasons we may end up with opportunities for this
transformation, including but not limited to:
- X-Form instructions chosen since the exact offset isn't available at ISEL time
- Atomic instructions with constant operands (we will add patterns for this
in the future)
- Tail duplication may duplicate code where one block contains this redundancy
- When emitting compare-free code in PPCDAGToDAGISel, we don't handle constant
comparands specially
Furthermore, this patch moves the initialization of PPCMIPeepholePass so that
it can be used for MIR tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320791
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Craig Topper [Fri, 15 Dec 2017 07:16:41 +0000 (07:16 +0000)]
[X86] Fix a couple bugs in my recent changes to vXi1 insert_subvector lowering.
A couple places didn't use the same SDValue variables to connect everything all the way through.
I don't have a test case for a bug in insert into the lower bits of a non-zero, non-undef vector. Not sure the best way to create that. We don't create the case when lowering concat_vectors which is the main way to get insert_subvectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320790
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Serguei Katkov [Fri, 15 Dec 2017 05:24:42 +0000 (05:24 +0000)]
[SCEV] Fix the movement of insertion point in expander. PR35406.
We cannot move the insertion point to header if SCEV contains div/rem
operations due to they may go over check for zero denominator.
Reviewers: sanjoy, mkazantsev, sebpop
Reviewed By: sebpop
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320789
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Yaxun Liu [Fri, 15 Dec 2017 03:56:57 +0000 (03:56 +0000)]
Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
The regression on ppc64 was not due to this commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320788
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Nemanja Ivanovic [Fri, 15 Dec 2017 01:38:03 +0000 (01:38 +0000)]
Disabling r312514 as it causes miscompiles that show up on bootstrap
The compare elimination peephole introduced in https://reviews.llvm.org/rL312514
causes a miscompile in AMDGPUInstrInfo.cpp which in turn causes some AMDGPU
test case failures in stage2 bootstrap testing. This miscompile didn't cause any
test case failures until https://reviews.llvm.org/rL320614, so it appeared as if
that patch caused these failures.
Disabling this transformation for now to bring the build bots back to green and
the author of the patch will investigate the miscompile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320786
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Shoaib Meenai [Fri, 15 Dec 2017 01:05:48 +0000 (01:05 +0000)]
[cmake] Fix clang-cl cross-compilation on macOS
macOS paths usually start with /Users, which clang-cl interprets as a
macro undefine, leading to pretty much everything failing to compile.
CMake should be taught to put a -- in its compilation rules for clang-cl
(and I've been meaning to submit that upstream for a while). In the
meantime, however, and to support older CMake versions, we can just
create a custom make rules override to fix the compilation rules.
Differential Revision: https://reviews.llvm.org/D41219
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320785
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Craig Topper [Fri, 15 Dec 2017 01:03:46 +0000 (01:03 +0000)]
[X86] Add a TODO about v8i1 CONCAT_VECTORS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320784
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Craig Topper [Fri, 15 Dec 2017 01:03:45 +0000 (01:03 +0000)]
[SelectionDAG] Make getNode calls that take an ArrayRef of SDValue for operands call NewSDValueDbgMsg.
This makes it work better with some build_vector and concat_vectors creations.
Adjust the NewSDValueDbgMsg in getConstant to avoid duplicating the print when it calls getSplatBuildVector since getSplatBuildVector didn't trigger a print before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320783
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Craig Topper [Fri, 15 Dec 2017 01:03:43 +0000 (01:03 +0000)]
[X86] Further rearrange the setOperationAction calls to separate the ones that require 512-bit registers OR VLX into separate sections. NFCI
We have several instructions that were introduced in AVX512F that are only available in 512-bit form on KNL. We still make use of them for 128/256 by artificially widening and extracting during isel.
This commit separates these operations from the true 512-bit operations. This way we can qualify the normal 512-bit operations with needing 512-bit register support. And these special operations will get qualified with needing 512-bit registers OR VLX.
The 512-bit register qualification will be introduced in a future patch this just gets everything grouped to minimize deltas on that patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320782
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Craig Topper [Fri, 15 Dec 2017 01:03:42 +0000 (01:03 +0000)]
[X86] Group setOperationActions related to vXi1 masks together. NFCI
Previously they were sort of interleaved in with XMM/YMM/ZMM action related code.
Trying to separate things so its easier to split 512-bit vectors later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320781
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Craig Topper [Fri, 15 Dec 2017 01:03:40 +0000 (01:03 +0000)]
[X86] Make ISD::INSERT_SUBVECTOR v8i1 legal with AVX512F because we should be custom lowering inserting v1i1 into v8i1 under this.
I don't have a test case at the moment. Just noticed while auditing things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320780
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Craig Topper [Fri, 15 Dec 2017 01:03:38 +0000 (01:03 +0000)]
[X86] Move some of the hasVLX qualified code out of the main hasAVX512 block in the X86ISelLowering constructor. NFCI
Move it into the separate hasVLX block later in the constructor.
I'm trying to separate 128/256 and 512-bit related code so we can eventually qualify the hasAVX512 block with support for 512-bit vectors required by the prefer-vector-width feature support being talked about in D41096.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320779
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Saleem Abdulrasool [Fri, 15 Dec 2017 00:32:09 +0000 (00:32 +0000)]
FastISel: support no-PLT PIC calls on ELF x86_64
Add support for properly handling PIC code with no-PLT. This equates to
`-fpic -fno-plt -O0` with the clang frontend. External functions are
marked with nonlazybind, which must then be indirected through the GOT.
This allows code to be built without optimizations in PIC mode without
going through the PLT. Addresses PR35653!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320776
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Zachary Turner [Fri, 15 Dec 2017 00:27:49 +0000 (00:27 +0000)]
Don't crash in llvm-pdbutil when dumping TypeIndexes with high bit set.
This is a special code that indicates that it's a function id.
While I'm still not certain how to interpret these, we definitely
should *not* be using these values as indices into an array directly.
For now, when we encounter one of these, just print the numeric value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320775
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Sam Clegg [Fri, 15 Dec 2017 00:17:10 +0000 (00:17 +0000)]
[WebAssembly] Implement @llvm.global_ctors and @llvm.global_dtors
Summary:
- lowers @llvm.global_dtors by adding @llvm.global_ctors
functions which register the destructors with `__cxa_atexit`.
- impements @llvm.global_ctors with wasm start functions and linker metadata
See [here](https://github.com/WebAssembly/tool-conventions/issues/25) for more background.
Subscribers: jfb, dschuff, mgorny, jgravelle-google, aheejin, sunfish
Differential Revision: https://reviews.llvm.org/D41211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320774
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Don Hinton [Fri, 15 Dec 2017 00:06:26 +0000 (00:06 +0000)]
[debuginfo] Remove obsolete test_debuginfo.pl that was moved to debuginfo-tests.
Summary:
Now that r320495, "[debuginfo-tests] Support moving
debuginfo-tests to llvm/projects," has landed, which includes a local
copy of test_debuginfo.pl, remove the obsolete copy.
Reviewers: zturner, aprantl
Reviewed By: aprantl
Subscribers: llvm-commits, JDevlieghere
Differential Revision: https://reviews.llvm.org/D41260
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320771
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David Blaikie [Thu, 14 Dec 2017 23:45:58 +0000 (23:45 +0000)]
Remove a non-modular header (& inline it into its one use)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320768
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Quentin Colombet [Thu, 14 Dec 2017 23:44:07 +0000 (23:44 +0000)]
[TableGen][GlobalISel] Add a common class for all PredicateMatcher
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320767
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George Burgess IV [Thu, 14 Dec 2017 23:32:57 +0000 (23:32 +0000)]
[ProfileData] Use a different data structure to save memory.
This change swaps FunctionSamples to a std::map. This saves us around
17% of the memory required to parse sample profiles. To put hard numbers
on this, clang now eats around 1.3GB of RAM instead of 1.6GB while
parsing a 50MB profile.
The CPU time taken by a large profile merge (3.1GB of data across 226
files) is also reduced by ~11% by this patch (1:09.08 vs 1:01.11).
This was split out at the request of reviewers in D41152.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320764
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Evandro Menezes [Thu, 14 Dec 2017 23:13:04 +0000 (23:13 +0000)]
[Unit][AArch64] Additional tests for target parsing
Add Exynos M2/M3 to extension check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320762
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Evandro Menezes [Thu, 14 Dec 2017 23:06:18 +0000 (23:06 +0000)]
[AArch64] Test patch
Fix formatting by adding a missing blank line to test new network setup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320760
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Adrian Prantl [Thu, 14 Dec 2017 22:55:06 +0000 (22:55 +0000)]
EmitFuncArgumentDbgValue: Prefer stack slots over registers for stack arguments
While investigating LLVM PR22316 (http://llvm.org/bugs/show_bug.cgi?id=22316)
I started wondering if it were not always preferable to emit the
initial DBG_VALUEs for stack arguments as FI locations instead of
describing the first register they get copied into. The advantage of
doing this is that the arguments will be available as soon as the
stack is setup. As illustrated by the testcase in the PR, the first
copy of the FI into a register may be sunk by MachineSink.cpp into a
later basic block. By describing the argument on the stack, we nicely
circumvent this problem.
<rdar://problem/
19583723>
Differential Revision: https://reviews.llvm.org/D41135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320758
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Craig Topper [Thu, 14 Dec 2017 22:50:10 +0000 (22:50 +0000)]
[X86] Remove an unnecessary SmallVector that was collecting chains for two SDNode's we're still holding SDValues for. NFCI
We can just get the chains from those SDValues to create the TokenFactor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320757
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Matt Arsenault [Thu, 14 Dec 2017 22:34:10 +0000 (22:34 +0000)]
TLI: Allow using PSV for intrinsic mem operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320756
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Zachary Turner [Thu, 14 Dec 2017 22:07:03 +0000 (22:07 +0000)]
Fix many -Wsign-compare and -Wtautological-constant-compare warnings.
Most of the -Wsign-compare warnings are due to the fact that
enums are signed by default in the MS ABI, while the
tautological comparison warnings trigger on x86 builds where
sizeof(size_t) is 4 bytes, so N > numeric_limits<unsigned>::max()
is always false.
Differential Revision: https://reviews.llvm.org/D41256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320750
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Sanjay Patel [Thu, 14 Dec 2017 22:05:20 +0000 (22:05 +0000)]
[SimplifyCFG] don't sink common insts too soon (PR34603)
This should solve:
https://bugs.llvm.org/show_bug.cgi?id=34603
...by preventing SimplifyCFG from altering redundant instructions before early-cse has a chance to run.
It changes the default (canonical-forming) behavior of SimplifyCFG, so we're only doing the
sinking transform later in the optimization pipeline.
Differential Revision: https://reviews.llvm.org/D38566
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320749
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Matt Arsenault [Thu, 14 Dec 2017 21:39:51 +0000 (21:39 +0000)]
DAG: Expose all MMO flags in getTgtMemIntrinsic
Rather than adding more bits to express every
MMO flag you could want, just directly use the
MMO flags. Also fixes using a bunch of bool arguments to
getMemIntrinsicNode.
On AMDGPU, buffer and image intrinsics should always
have MODereferencable set, but currently there is no
way to do that directly during the initial intrinsic
lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320746
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Krzysztof Parzyszek [Thu, 14 Dec 2017 21:28:48 +0000 (21:28 +0000)]
[Hexagon] Generate HVX code for comparisons and selects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320744
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Sam Clegg [Thu, 14 Dec 2017 21:10:03 +0000 (21:10 +0000)]
[WebAssembly] Add support for init functions linking metadata
Summary:
This change lays the groundwork lowering of @llvm.global_ctors
and @llvm.global_dtors for the wasm object format. Some parts
of this patch are subset of: https://reviews.llvm.org/D40759
See https://github.com/WebAssembly/tool-conventions/issues/25
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish
Differential Revision: https://reviews.llvm.org/D41208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320742
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Zachary Turner [Thu, 14 Dec 2017 19:59:10 +0000 (19:59 +0000)]
Revert "Fix isPodLike for MSVC and use it in TypeHashing."
This reverts commit
ac5edc198eb612f82293850c3488042708b1c5fa.
Apparently this doesn't cover all the bases, so some compilers
and standard libraries still think this is not trivially copyable
even though it is. Reverting this back to an MSVC-only check for
now so that at least we have some coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320739
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Zachary Turner [Thu, 14 Dec 2017 19:41:28 +0000 (19:41 +0000)]
Fix isPodLike for MSVC and use it in TypeHashing.
This should be a better check than using is_trivially_copyable
behind an #ifdef _MSC_VER.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320737
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Guozhi Wei [Thu, 14 Dec 2017 19:35:43 +0000 (19:35 +0000)]
[SLPVectorizer] Don't ignore scalar extraction instructions of aggregate value
In SLPVectorizer, the vector build instructions (insertvalue for aggregate type) is passed to BoUpSLP.buildTree, it is treated as UserIgnoreList, so later in cost estimation, the cost of these instructions are not counted.
For aggregate value, later usage are more likely to be done in scalar registers, either used as individual scalars or used as a whole for function call or return value. Ignore scalar extraction instructions may cause too aggressive vectorization for aggregate values, and slow down performance. So for vectorization of aggregate value, the scalar extraction instructions are required in cost estimation.
Differential Revision: https://reviews.llvm.org/D41139
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320736
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Zachary Turner [Thu, 14 Dec 2017 19:11:28 +0000 (19:11 +0000)]
Only use is_trivially_copyable if we know it's safe to do so.
Apparently this isn't present on older versions of libstdc++, so
it causes some builds to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320733
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Krzysztof Parzyszek [Thu, 14 Dec 2017 19:05:21 +0000 (19:05 +0000)]
Add MVT::v128i1, NFC
Hexagon HVX has type v128i8, comparing two vectors of that type will
produce v128i1 types in SelectionDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320732
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Adam Nemet [Thu, 14 Dec 2017 18:55:33 +0000 (18:55 +0000)]
[opt-viewer] Render utf-8 characters properly in the generated HTML
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320729
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Paul Robinson [Thu, 14 Dec 2017 18:46:43 +0000 (18:46 +0000)]
[MC] Allow .file directives to be out-of-order
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320727
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Adam Nemet [Thu, 14 Dec 2017 18:42:42 +0000 (18:42 +0000)]
[opt-viewer] Support unicode characters in function names
This is a Swift feature. The output stream for the index page and the source
HTML page is utf-8 now.
The next patch will add the HTML magic to properly render these characters in
the browser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320725
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Shoaib Meenai [Thu, 14 Dec 2017 18:41:49 +0000 (18:41 +0000)]
[cmake] Only attempt to install MSVC system libraries on Windows
Newer versions of CMake (I'm on 3.10, but I believe 3.9 behaves the same
way) attempt to query the system for information about the VS 2017
install. Unfortunately, this query fails on non-Windows systems:
cmake_host_system_information does not recognize <key> VS_15_DIR
CMake isn't going to find these system libraries on non-Windows anyway
(and we were previously silencing the resultant warnings in our
cross-compilation toolchain), so it makes sense to just omit the
attempted installation entirely on non-Windows.
Differential Revision: https://reviews.llvm.org/D41220
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320724
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Craig Topper [Thu, 14 Dec 2017 18:35:25 +0000 (18:35 +0000)]
[X86] Don't zero the upper bits of the k-register before extracting a single bit from a vXi1.
This doesn't match the semantics of the extract_vector_elt operation. Nothing downstream knows the bits were zeroed so they still get masked or sign extended after the extrat anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320723
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Krzysztof Parzyszek [Thu, 14 Dec 2017 18:35:24 +0000 (18:35 +0000)]
[Hexagon] Remove vectors of i64 from valid HVX types
HVX does not support operations on 64-bit integers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320722
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Zachary Turner [Thu, 14 Dec 2017 18:20:23 +0000 (18:20 +0000)]
Fix error due to missing includes.
While I'm pushing cleanup changes, this also fixes a few warnings
related to extraneous semicolons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320720
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Zachary Turner [Thu, 14 Dec 2017 18:07:04 +0000 (18:07 +0000)]
[COFF] Teach LLD to use the COFF .debug$H section.
This adds the /DEBUG:GHASH option to LLD which will look for
the existence of .debug$H sections in linker inputs and use them
to accelerate type merging. The clang-cl side has already been
added, so this completes the work necessary to begin experimenting
with this feature.
Differential Revision: https://reviews.llvm.org/D40980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320719
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Geoff Berry [Thu, 14 Dec 2017 18:06:25 +0000 (18:06 +0000)]
[ARM] Fix isRenamable flag setting on expanded VSTMDIA opcode.
Fixes expensive-check ARM buildbot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320718
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Gadi Haber [Thu, 14 Dec 2017 16:46:47 +0000 (16:46 +0000)]
[X86][AVX][AVX2]: Adding full coverage of MC encoding for the AVX, AVX2 isa set.<NFC>
NFC.
Adding MC regressions tests to cover the AVX and AVX2 ISA sets.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
See revision: https://reviews.llvm.org/D39952
Reviewers: zvi, RKSimon, aymanmus, m_zuckerman
Differential Revison: https://reviews.llvm.org/D40287
Change-Id: I304687a2b7abb473f79de99c31fc55c97b2662da
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320716
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Simon Dardis [Thu, 14 Dec 2017 16:42:04 +0000 (16:42 +0000)]
[mips] Update some tests before posting a patch, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320715
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Yaxun Liu [Thu, 14 Dec 2017 16:12:04 +0000 (16:12 +0000)]
Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
This commit might have caused regression on ppc64. Revert it to verify that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320712
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Sander de Smalen [Thu, 14 Dec 2017 16:09:48 +0000 (16:09 +0000)]
Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.
Summary:
The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand.
This is because the code will only update the diagnostic if it is more
specific than the previous diagnostic. However, when having validated
operands and 'moved on' to a next operand (for some instruction/alias for
which all previous operands are valid), if the diagnostic is InvalidOperand,
than that should be set as the diagnostic, not the more specific message
about a previous operand for some other instruction/alias candidate.
(Re-committed with an extra whitespace in SVEInstrFormats.td to trigger rebuild
of AArch64GenAsmMatcher.inc, since the llvm-clang-x86_64-expensive-checks-win
builder does not seem to rebuild AArch64GenAsmMatcher.inc with the
newly built TableGen due to a missing dependency somewhere (see:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119555.html))
Reviewers: craig.topper, olista01, rengolin, stoklund
Reviewed By: olista01
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D40011
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320711
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Eugene Leviant [Thu, 14 Dec 2017 15:59:05 +0000 (15:59 +0000)]
[LLVMgold] Use platform dependent extension in tests
Differential revision: https://reviews.llvm.org/D41238
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320710
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Simon Dardis [Thu, 14 Dec 2017 14:55:25 +0000 (14:55 +0000)]
[mips] Add partial support for R6 in the long branch pass
MIPSR6 introduced several new jump instructions and deprecated
the use of the 'j' instruction. For microMIPS32R6, 'j' was removed
entirely and it only has non delay slot jumps.
This patch adds support for MIPSR6 by using some R6 instructions--
'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'--
and modifies the sequences not to use delay slots for R6.
Reviewers: atanasyan
Reviewed By: atanasyan
Subscribers: dschuff, arichardson, llvm-commits
Differential Revision: https://reviews.llvm.org/D40786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320703
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Bjorn Pettersson [Thu, 14 Dec 2017 14:47:52 +0000 (14:47 +0000)]
[ScalarEvolution] Fix base condition in isNormalAddRecPHI.
Summary:
The function is meant to recurse until it comes upon the
phi it's looking for. However, with the current condition,
it will recurse until it finds anything _but_ the phi.
The function will even fail for simple cases like:
%i = phi i32 [ %inc, %loop ], ...
...
%inc = add i32 %i, 1
because the base condition will not happen when the phi
is recursed to, and the recursion will end with a 'false'
result since the previous instruction is a phi.
Reviewers: sanjoy, atrick
Reviewed By: sanjoy
Subscribers: Ka-Ka, bjope, llvm-commits
Committing on behalf of: Bevin Hansson (bevinh)
Differential Revision: https://reviews.llvm.org/D40946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320700
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Haicheng Wu [Thu, 14 Dec 2017 14:36:18 +0000 (14:36 +0000)]
[InlineCost] Tracking Values through PHI Nodes
This patch fix this FIXME in visitPHI()
FIXME: We should potentially be tracking values through phi nodes,
especially when they collapse to a single value due to deleted CFG edges
during inlining.
Differential Revision: https://reviews.llvm.org/D38594
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320699
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Benjamin Kramer [Thu, 14 Dec 2017 14:03:07 +0000 (14:03 +0000)]
Revert "[DAGCombine] Move AND nodes to multiple load leaves"
This reverts commit r320679. Causes miscompiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320698
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Andrew V. Tischenko [Thu, 14 Dec 2017 12:07:11 +0000 (12:07 +0000)]
Any Target Asm comments should start from MachineInstr::TAsmComments value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320693
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Omer Paparo Bivas [Thu, 14 Dec 2017 12:00:04 +0000 (12:00 +0000)]
Inserting several lit tests to reflect current behaviour
Change-Id: I1b8188dc3c6c7c0f455715364ece7d35ef485f2f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320692
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Michael Zuckerman [Thu, 14 Dec 2017 11:55:50 +0000 (11:55 +0000)]
[AVX512] Adding support for load truncate store of I1
store operation on a truncated memory (load) of vXi1 is poorly supported by LLVM and most of the time end with an assertion.
This patch fixes this issue.
Differential Revision: https://reviews.llvm.org/D39547
Change-Id: Ida5523dd09c1ad384acc0a27e9e59273d28cbdc9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320691
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Simon Pilgrim [Thu, 14 Dec 2017 11:40:54 +0000 (11:40 +0000)]
[X86] Add FMA4 schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320690
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Simon Pilgrim [Thu, 14 Dec 2017 11:30:01 +0000 (11:30 +0000)]
[X86] Add FMA3 schedule tests
Rewrote to use inline asm for full coverage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320689
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Fedor Sergeev [Thu, 14 Dec 2017 10:36:31 +0000 (10:36 +0000)]
[PM][InstCombine] fixing omission of AliasAnalysis in new-pass-manager's version of InstCombine
Summary:
Passing AliasAnalysis results instead of nullptr appears to work just fine.
A couple new-pass-manager tests updated to align with new order of analyses.
Reviewers: chandlerc, spatel, craig.topper
Reviewed By: chandlerc
Subscribers: mehdi_amini, eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D41203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320687
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Fedor Sergeev [Thu, 14 Dec 2017 10:36:20 +0000 (10:36 +0000)]
Remove redundant includes from lib/Target/AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320686
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Francis Visoiu Mistrih [Thu, 14 Dec 2017 10:03:23 +0000 (10:03 +0000)]
[CodeGen] Print MCSymbol operands as <mcsymbol sym> in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`<mcsymbol sym>` instead of `<MCSym=sym>`.
Only debug syntax is affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320685
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Francis Visoiu Mistrih [Thu, 14 Dec 2017 10:03:18 +0000 (10:03 +0000)]
[CodeGen] Move printing MO_Metadata operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320684
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Francis Visoiu Mistrih [Thu, 14 Dec 2017 10:03:14 +0000 (10:03 +0000)]
[CodeGen] Print live-out register lists as liveout(...) in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`liveout(...)` instead of `<regliveout>`.
Only debug syntax is affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320683
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Francis Visoiu Mistrih [Thu, 14 Dec 2017 10:03:09 +0000 (10:03 +0000)]
[CodeGen] Print global addresses as @foo in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`@foo` instead of `<ga:@foo>`.
Also print target flags in the MIR format since most of them are used on
global address operands.
Only debug syntax is affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320682
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Thu, 14 Dec 2017 10:02:58 +0000 (10:02 +0000)]
[CodeGen] Print external symbols as $symbol in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`$symbol` instead of `<es:symbol>`.
Only debug syntax is affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320681
91177308-0d34-0410-b5e6-
96231b3b80d8