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Simon Dardis [Wed, 20 Jun 2018 21:25:50 +0000 (21:25 +0000)]
Remove myself from the release testers list. (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335178
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Benjamin Kramer [Wed, 20 Jun 2018 21:12:59 +0000 (21:12 +0000)]
[Dominators] Simplify child lists and make them deterministic
This fixes an extremely subtle non-determinism that can only be
triggered by an unfortunate alignment of passes. In my case:
- JumpThreading does large dominator tree updates
- CorrelatedValuePropagation preserves domtree now
- LICM codegen depends on the order of children on domtree nodes
The last part is non-deterministic if the update was stored in a set.
But it turns out that the set is completely unnecessary, updates are
deduplicated at an earlier stage so we can just use a vector, which is
both more efficient and doesn't destroy the input ordering.
I didn't manage to get the 240 MB IR file reduced enough, triggering
this bug requires a lot of jump threading, so landing this without a
test case.
Differential Revision: https://reviews.llvm.org/D48392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335176
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Alina Sbirlea [Wed, 20 Jun 2018 21:06:13 +0000 (21:06 +0000)]
[MemorySSA] Verify Phi incoming blocks are block predecessors.
Summary: Make the MemorySSA verify also check that all Phi incoming blocks are block predecessors.
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D48333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335174
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Craig Topper [Wed, 20 Jun 2018 21:05:02 +0000 (21:05 +0000)]
[X86] Use setcc ISD opcode for AVX512 integer comparisons all the way to isel
I don't believe there is any real reason to have separate X86 specific opcodes for vector compares. Setcc has the same behavior just uses a different encoding for the condition code.
I had to change the CondCodeAction for SETLT and SETLE to prevent some transforms from changing SETGT lowering.
Differential Revision: https://reviews.llvm.org/D43608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335173
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Simon Pilgrim [Wed, 20 Jun 2018 20:54:52 +0000 (20:54 +0000)]
[SLPVectorizer] Provide InstructionsState down the BoUpSLP vectorization call tree
As described in D48359, this patch pushes InstructionsState down the BoUpSLP call hierarchy instead of the corresponding raw OpValue. This makes it easier to track the alternate opcode etc. and avoids us having to call getAltOpcode which makes it difficult to support more than one alternate opcode.
Differential Revision: https://reviews.llvm.org/D48382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335170
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Stanislav Mekhanoshin [Wed, 20 Jun 2018 20:24:20 +0000 (20:24 +0000)]
Allow binop C1, (select cc, CF, CT) -> select folding
Previously this folding was done only if select is a first operand.
However, for non-commutative operations constant may go before
select.
Differential Revision: https://reviews.llvm.org/D48223
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335167
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Sanjay Patel [Wed, 20 Jun 2018 20:16:45 +0000 (20:16 +0000)]
[InstCombine] fix typo in test comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335165
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Simon Dardis [Wed, 20 Jun 2018 19:59:58 +0000 (19:59 +0000)]
[mips] Correct predicates for loads, bit manipulation instructions and some pseudos
Additionally, correct the definition of the rdhwr instruction.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D48216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335162
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Matt Arsenault [Wed, 20 Jun 2018 19:45:48 +0000 (19:45 +0000)]
AMDGPU: Fix scalar_to_vector for v4i16/v4f16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335161
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Matt Arsenault [Wed, 20 Jun 2018 19:45:40 +0000 (19:45 +0000)]
AMDGPU: Fix missing C++ mode comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335160
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Krzysztof Parzyszek [Wed, 20 Jun 2018 19:22:27 +0000 (19:22 +0000)]
[Hexagon] Replace .ll test for expanding post-ra pesudos with .mir
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335158
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Sanjay Patel [Wed, 20 Jun 2018 19:02:17 +0000 (19:02 +0000)]
[IR] add/use isIntDivRem convenience function
There are more existing potential users of this,
but I've limited this patch to the first couple
that I found to minimize typo risk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335157
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Chandler Carruth [Wed, 20 Jun 2018 18:57:07 +0000 (18:57 +0000)]
[PM/LoopUnswitch] Support partial trivial unswitching.
The idea of partial unswitching is to take a *part* of a branch's
condition that is loop invariant and just unswitching that part. This
primarily makes sense with i1 conditions of branches as opposed to
switches. When dealing with i1 conditions, we can easily extract loop
invariant inputs to a a branch and unswitch them to test them entirely
outside the loop.
As part of this, we now create much more significant cruft in the loop
body, so this relies on adding cleanup passes to the loop pipeline and
revisiting unswitched loops to do that cleanup before continuing to
process them.
This already appears to be more powerful at unswitching than the old
loop unswitch pass, and so I'd appreciate pretty careful review in case
I'm just missing some correctness checks. The `LIV-loop-condition` test
case is not unswitched by the old unswitch pass, but is with this pass.
Thanks to Sanjoy and Fedor for the review!
Differential Revision: https://reviews.llvm.org/D46706
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335156
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Alex Bradbury [Wed, 20 Jun 2018 18:42:25 +0000 (18:42 +0000)]
[RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for fmv.w.x and fmv.x.w
These instructions were renamed in version 2.2 of the user-level ISA spec, but
the old name should also be accepted by standard tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335154
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Jessica Paquette [Wed, 20 Jun 2018 18:41:11 +0000 (18:41 +0000)]
[MachineOutliner] Add debug info test for the outliner
The outliner emits debug info. Add a test that outlines a function
and uses llvm-dwarfdump to check the emitted DWARF for correctness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335153
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Vedant Kumar [Wed, 20 Jun 2018 18:40:14 +0000 (18:40 +0000)]
[Local] Generalize insertReplacementDbgValues, NFC
This utility should operate on Values, not Instructions. While I'm here,
I've also made it possible to skip emitting replacement dbg.values for
certain debug users (by having RewriteExpr return nullptr).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335152
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Sanjay Patel [Wed, 20 Jun 2018 17:48:43 +0000 (17:48 +0000)]
[InstCombine] add vector select of binops tests (PR37806)
These represent the most basic requested transform - a matching
operand and 2 constant operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335151
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Florian Hahn [Wed, 20 Jun 2018 17:42:01 +0000 (17:42 +0000)]
[PredicateInfo] Order instructions in different BBs by DFSNumIn.
Using OrderedInstructions::dominates as comparator for instructions in
BBs without dominance relation can cause a non-deterministic order
between such instructions. That in turn can cause us to materialize
copies in a non-deterministic order. While this does not effect
correctness, it causes some minor non-determinism in the final generated
code, because values have slightly different labels.
Without this patch, running -print-predicateinfo on a reasonably large
module produces slightly different output on each run.
This patch uses the dominator trees DFSInNum to order instruction from
different BBs, which should enforce a deterministic ordering and
guarantee that dominated instructions come after the instructions that
dominate them.
Reviewers: dberlin, efriedma, davide
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D48230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335150
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Paul Robinson [Wed, 20 Jun 2018 17:08:46 +0000 (17:08 +0000)]
[DWARF] Don't keep a ref to possibly stack allocated data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335146
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Vlad Tsyrklevich [Wed, 20 Jun 2018 16:50:56 +0000 (16:50 +0000)]
IRMover: Account for matching types present across modules
Summary:
Due to uniqueing of DICompositeTypes, it's possible for a type from one
module to be loaded into another earlier module without being renamed.
Then when the defining module is being IRMoved, the type can be used as
a Mapping destination before being loaded, such that when it's requested
using TypeMapTy::get() it will fail with an assertion that the type is a
source type when it's actually a type in both the source and
destination modules. Correctly handle that case by allowing a non-opaque
non-literal struct type be present in both modules.
Fix for PR37684.
Reviewers: pcc, tejohnson
Reviewed By: pcc, tejohnson
Subscribers: tobiasvk, mehdi_amini, steven_wu, llvm-commits, kcc
Differential Revision: https://reviews.llvm.org/D47898
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335145
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Vedant Kumar [Wed, 20 Jun 2018 16:50:25 +0000 (16:50 +0000)]
[Local] Add a utility to insert replacement dbg.values, NFC
The purpose of this utility is to make it easier for optimizations to
insert replacement dbg.values for instructions they are deleting. This
is useful in situations where salvageDebugInfo is inapplicable, say,
because the new dbg.value cannot refer to an operand of the dying value.
The utility is called insertReplacementDbgValues.
It assumes that the instruction 'From' is going to be deleted, and
inserts replacement dbg.values for each debug user of 'From'. The
newly-inserted dbg.values refer to 'To' instead of 'From'. Each
replacement dbg.value has the same location and variable as the debug
user it replaces, has a DIExpression determined by the result of
'RewriteExpr' applied to an old debug user of 'From', and is placed
before 'InsertBefore'.
This should simplify future patches, like D48331.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335144
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Paul Robinson [Wed, 20 Jun 2018 16:12:03 +0000 (16:12 +0000)]
Remove a redundant initialization. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335143
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Simon Pilgrim [Wed, 20 Jun 2018 16:11:00 +0000 (16:11 +0000)]
[SLPVectorizer] Move isOneOf after InstructionsState type. NFCI.
A future patch will have isOneOf use InstructionsState.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335142
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Bjorn Pettersson [Wed, 20 Jun 2018 16:06:09 +0000 (16:06 +0000)]
[DAG] Don't map a TableId to itself in the ReplacedValues map
Summary:
Found some regressions (infinite loop in DAGTypeLegalizer::RemapId)
after r334880. This patch makes sure that we do map a TableId to
itself.
Reviewers: niravd
Reviewed By: niravd
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48364
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335141
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Nirav Dave [Wed, 20 Jun 2018 15:36:29 +0000 (15:36 +0000)]
[DAG] Fix and-mask folding when narrowing loads.
Summary:
Check that and masks are strictly smaller than implicit mask from
narrowed load.
Fixes PR37820.
Reviewers: samparker, RKSimon, nemanjai
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D48335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335137
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Eugene Leviant [Wed, 20 Jun 2018 15:32:47 +0000 (15:32 +0000)]
[LIT] Enable testing of LLVM gold plugin on Mac OS X
Differential revision: https://reviews.llvm.org/D48350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335136
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Sam Clegg [Wed, 20 Jun 2018 15:17:12 +0000 (15:17 +0000)]
[WebAssembly] Update know failures for the wasm waterfall
Summary:
The waterfall no longer builds .s files and no longers uses
the wasm-o when it builds object files.
Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D48371
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335135
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Simon Pilgrim [Wed, 20 Jun 2018 15:13:40 +0000 (15:13 +0000)]
[SLPVectorizer] Use InstructionsState to record AltOpcode
This is part of a move towards generalizing the alternate opcode mechanism and not just supporting (F)Add/(F)Sub counterparts.
The patch embeds the AltOpcode in the InstructionsState instead of calling getAltOpcode so often.
I'm hoping to eventually remove all uses of getAltOpcode and handle alternate opcode selection entirely within getSameOpcode, that will require us to use InstructionsState throughout the BoUpSLP call hierarchy (similar to some of the changes in D28907), which I will begin in future patches.
Differential Revision: https://reviews.llvm.org/D48359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335134
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Andrea Di Biagio [Wed, 20 Jun 2018 14:30:17 +0000 (14:30 +0000)]
[llvm-mca] use APint::operator[] to obtain the bit value. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335131
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Simon Pilgrim [Wed, 20 Jun 2018 14:26:28 +0000 (14:26 +0000)]
[SLPVectorizer] Relax "alternate" opcode vectorisation to work with any SK_Select shuffle pattern
D47985 saw the old SK_Alternate 'alternating' shuffle mask replaced with the SK_Select mask which accepts either input operand for each lane, equivalent to a vector select with a constant condition operand.
This patch updates SLPVectorizer to make full use of this SK_Select shuffle pattern by removing the 'isOdd()' limitation.
The AArch64 regression will be fixed by D48172.
Differential Revision: https://reviews.llvm.org/D48174
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335130
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Sanjay Patel [Wed, 20 Jun 2018 14:22:49 +0000 (14:22 +0000)]
[InstSimplify] Fix missed optimization in simplifyUnsignedRangeCheck()
For both operands are unsigned, the following optimizations are valid, and missing:
1. X > Y && X != 0 --> X > Y
2. X > Y || X != 0 --> X != 0
3. X <= Y || X != 0 --> true
4. X <= Y || X == 0 --> X <= Y
5. X > Y && X == 0 --> false
unsigned foo(unsigned x, unsigned y) { return x > y && x != 0; }
should fold to x > y, but I found we haven't done it right now.
besides, unsigned foo(unsigned x, unsigned y) { return x < y && y != 0; }
Has been folded to x < y, so there may be a bug.
Patch by: Li Jia He!
Differential Revision: https://reviews.llvm.org/D47922
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335129
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Sanjay Patel [Wed, 20 Jun 2018 14:03:13 +0000 (14:03 +0000)]
[InstSimplify] Add tests for missed optimizations in simplifyUnsignedRangeCheck (NFC)
These are the baseline tests for the functional change in D47922.
Patch by Li Jia He!
Differential Revision: https://reviews.llvm.org/D48000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335128
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Alex Bradbury [Wed, 20 Jun 2018 14:03:02 +0000 (14:03 +0000)]
[RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}
These are produced by GCC and supported by GAS, but not currently contained in
the pseudoinstruction listing in the RISC-V ISA manual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335127
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Mikhail Dvoretckii [Wed, 20 Jun 2018 14:01:57 +0000 (14:01 +0000)]
[X86] Adding a test for PR37879
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335126
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Sam McCall [Wed, 20 Jun 2018 13:56:25 +0000 (13:56 +0000)]
[ADT] Allow llvm::hash_code as DenseMap key.
Summary:
This is useful when hash collisions are unlikely and acceptable, e.g. in clangd
completion ranking.
Reviewers: ioeric
Subscribers: ilya-biryukov, llvm-commits
Differential Revision: https://reviews.llvm.org/D48361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335125
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Krzysztof Parzyszek [Wed, 20 Jun 2018 13:56:09 +0000 (13:56 +0000)]
[Hexagon] Remove 'T' from HasVNN predicates, NFC
Patch by Sumanth Gundapaneni.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335124
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Simon Dardis [Wed, 20 Jun 2018 13:29:57 +0000 (13:29 +0000)]
[mips] Fix the predicates of some DSP instructions from AdditionalPredicates to ASEPredicate
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D48166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335122
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Sanjay Patel [Wed, 20 Jun 2018 13:22:26 +0000 (13:22 +0000)]
[InstCombine] ignore debuginfo when removing redundant assumes (PR37726)
This is similar to:
rL335083
Fixes::
https://bugs.llvm.org/show_bug.cgi?id=37726
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335121
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Alex Bradbury [Wed, 20 Jun 2018 12:54:02 +0000 (12:54 +0000)]
[RISCV] Add InstAlias definitions for sgt and sgtu
These are produced by GCC and supported by GAS, but not currently contained in
the pseudoinstruction listing in the RISC-V ISA manual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335120
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Tim Northover [Wed, 20 Jun 2018 12:09:44 +0000 (12:09 +0000)]
ARM: convert ORR instructions to ADD where possible on Thumb.
Thumb has more 16-bit encoding space dedicated to ADD than ORR, allowing both a
3-address encoding and a wider range of immediates. So, particularly when
optimizing for code size (but it doesn't make things worse elsewhere) it's
beneficial to select an OR operation to an ADD if we know overflow won't occur.
This is made even better by LLVM's penchant for putting operations in canonical
form by converting the other way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335119
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Tim Northover [Wed, 20 Jun 2018 12:09:01 +0000 (12:09 +0000)]
[AArch64] Implement FLT_ROUNDS macro.
Very similar to ARM implementation, just maps to an MRS.
Should fix PR25191.
Patch by Michael Brase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335118
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Clement Courbet [Wed, 20 Jun 2018 11:54:35 +0000 (11:54 +0000)]
[llvm-exegesis] Add mechanism to add target-specific passes.
Summary:
createX86FloatingPointStackifierPass is disabled until we handle
TracksLiveness correctly.
Reviewers: gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335117
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Guillaume Chatelet [Wed, 20 Jun 2018 11:09:36 +0000 (11:09 +0000)]
[llvm-exegesis] Fix failing test.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335115
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Andrea Di Biagio [Wed, 20 Jun 2018 10:08:11 +0000 (10:08 +0000)]
[llvm-mca][X86] Teach how to identify register writes that implicitly clear the upper portion of a super-register.
This patch teaches llvm-mca how to identify register writes that implicitly zero
the upper portion of a super-register.
On X86-64, a general purpose register is implemented in hardware as a 64-bit
register. Quoting the Intel 64 Software Developer's Manual: "an update to the
lower 32 bits of a 64 bit integer register is architecturally defined to zero
extend the upper 32 bits". Also, a write to an XMM register performed by an AVX
instruction implicitly zeroes the upper 128 bits of the aliasing YMM register.
This patch adds a new method named clearsSuperRegisters to the MCInstrAnalysis
interface to help identify instructions that implicitly clear the upper portion
of a super-register. The rest of the patch teaches llvm-mca how to use that new
method to obtain the information, and update the register dependencies
accordingly.
I compared the kernels from tests clear-super-register-1.s and
clear-super-register-2.s against the output from perf on btver2. Previously
there was a large discrepancy between the estimated IPC and the measured IPC.
Now the differences are mostly in the noise.
Differential Revision: https://reviews.llvm.org/D48225
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335113
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Simon Pilgrim [Wed, 20 Jun 2018 09:39:01 +0000 (09:39 +0000)]
[SLPVectorizer] Split Tree/Reduction cost calls to simplify debugging. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335110
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Clement Courbet [Wed, 20 Jun 2018 09:18:37 +0000 (09:18 +0000)]
[llvm-exegesis] Remove noexcept in r335105.
gcc checks for transitivity (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53903)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335109
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Clement Courbet [Wed, 20 Jun 2018 09:18:32 +0000 (09:18 +0000)]
[llvm-exegesis] Fix missing move in r335105.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335108
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Martin Storsjo [Wed, 20 Jun 2018 09:17:19 +0000 (09:17 +0000)]
[Support] Add missing includes of <system_error> for std::error_code
This fixes compilation with MinGW after SVN r333798, which added
a few functions within _WIN32 ifdefs, functions returning
std::error_code. Include everything that is needed instead of
hoping that this header being inclued transitively (which it apparently
is in MSVC builds).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335107
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Guillaume Chatelet [Wed, 20 Jun 2018 08:52:30 +0000 (08:52 +0000)]
[llvm-exegesis] Use a Prototype to defer picking a value for free vars.
Summary: Introducing a Prototype object to capture Variables that must be set but keeps degrees of freedom as Invalid. This allows exploring non constraint variables later on.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335105
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Roman Lebedev [Wed, 20 Jun 2018 07:54:11 +0000 (07:54 +0000)]
[NFC][SCEV] Add tests related to bit masking (PR37793)
Summary:
Related to https://bugs.llvm.org/show_bug.cgi?id=37793, https://reviews.llvm.org/D46760#
1127287
We'd like to do this canonicalization https://rise4fun.com/Alive/Gmc
But it is currently restricted by rL155136 / rL155362, which says:
```
// This is a constant shift of a constant shift. Be careful about hiding
// shl instructions behind bit masks. They are used to represent multiplies
// by a constant, and it is important that simple arithmetic expressions
// are still recognizable by scalar evolution.
//
// The transforms applied to shl are very similar to the transforms applied
// to mul by constant. We can be more aggressive about optimizing right
// shifts.
//
// Combinations of right and left shifts will still be optimized in
// DAGCombine where scalar evolution no longer applies.
```
I think these tests show that for *constants*, SCEV has no issues with that canonicalization.
Reviewers: mkazantsev, spatel, efriedma, sanjoy
Reviewed By: mkazantsev
Subscribers: sanjoy, javed.absar, llvm-commits, stoklund, bixia
Differential Revision: https://reviews.llvm.org/D48229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335101
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Sjoerd Meijer [Wed, 20 Jun 2018 07:27:45 +0000 (07:27 +0000)]
[PatternMatch] Add m_Store pattern match helper
Differential Revision: https://reviews.llvm.org/D48279
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335100
91177308-0d34-0410-b5e6-
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Roman Lebedev [Wed, 20 Jun 2018 07:01:14 +0000 (07:01 +0000)]
[X86][Znver1] Specify Register Files, RCU; FP scheduler capacity.
Summary:
First off: i do not have any access to that processor,
so this is purely theoretical, no benchmarks.
I have been looking into b**d**ver2 scheduling profile, and while cross-referencing
the existing b**t**ver2, znver1 profiles, and the reference docs
(`Software Optimization Guide for AMD Family {15,16,17}h Processors`),
i have noticed that only b**t**ver2 scheduling profile specifies these.
Also, there is no mca test coverage.
Reviewers: RKSimon, craig.topper, courbet, GGanesh, andreadb
Reviewed By: GGanesh
Subscribers: gbedwell, vprasad, ddibyend, shivaram, Ashutosh, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D47676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335099
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Clement Courbet [Wed, 20 Jun 2018 06:44:13 +0000 (06:44 +0000)]
[X86] Fix r335097
Missed `Generic` test in llvm-mca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335098
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Clement Courbet [Wed, 20 Jun 2018 06:13:39 +0000 (06:13 +0000)]
[X86] Add sched class WriteLAHFSAHF and fix values.
Summary:
I ran llvm-exegesis on SKX, SKL, BDW, HSW, SNB.
Atom is from Agner and SLM is a guess.
I've left AMD processors alone.
Reviewers: RKSimon, craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48079
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335097
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Hiroshi Inoue [Wed, 20 Jun 2018 05:29:26 +0000 (05:29 +0000)]
[NFC] fix trivial typos in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335096
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 20 Jun 2018 04:32:07 +0000 (04:32 +0000)]
[DAGCombiner] Add some comments to some true/false arguments to make it obvious what they are. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335095
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Craig Topper [Wed, 20 Jun 2018 04:32:06 +0000 (04:32 +0000)]
[X86] Remove a fptosi from the test_mm512_mask_reduce_max_pd fast-isel test.
The clang test inadvertently turned a floating point value into a double by having the wrong return type on the test function relative to the intrinsic it was testing.
This resulted in an extra fptosi instruction that propagated into this test when I copied the clang output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335094
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Craig Topper [Wed, 20 Jun 2018 04:32:05 +0000 (04:32 +0000)]
[SelectionDAG] Don't crash on inline assembly errors when the inline assembly return type is a struct.
Summary:
If we get an error building the SelectionDAG for inline assembly we try to continue and still build the DAG.
But if the return type for the inline assembly is a struct we end up crashing because we try to create an UNDEF node with a struct type which isn't valid.
Instead we need to create an UNDEF for each element of the struct and join them with merge_values.
This patch relies on single operand merge_values being handled gracefully by getMergeValues. If the return type is void there will be no VTs returned by ComputeValueVTs and now we just return instead of calling setValue. Hopefully that's ok, I assumed nothing would need to look up the mapped value for void node.
Fixes PR37359
Reviewers: rengolin, rovka, echristo, efriedma, bogner
Reviewed By: efriedma
Subscribers: craig.topper, llvm-commits
Differential Revision: https://reviews.llvm.org/D46560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335093
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Craig Topper [Wed, 20 Jun 2018 04:32:04 +0000 (04:32 +0000)]
[X86] Use binary search of the EVEX->VEX static tables instead of populating two DenseMaps for lookups
Summary:
After r335018, the static tables are guaranteed sorted by the EVEX opcode to convert. We can use this to do a binary search and remove the need for any secondary data structures.
Right now one table is 736 entries and the other is 482 entries. It might make sense to merge the two tables as a follow up. The effort it takes to select the table is probably similar to the extra binary search step it would require for a larger table.
I haven't done any measurements to see if this has any effect on compile time, but I don't imagine that EVEX->VEX conversion is a place we spend a lot of time.
Reviewers: RKSimon, spatel, chandlerc
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335092
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Philip Reames [Wed, 20 Jun 2018 02:43:46 +0000 (02:43 +0000)]
Add more test cases for deopt-operands via regalloc
This time, focused on reuse of arguments slots. Only one minor todo here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335091
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Vlad Tsyrklevich [Wed, 20 Jun 2018 00:02:32 +0000 (00:02 +0000)]
Revert r334980 and 334983
This reverts commits r334980 and r334983 because they were causing build
timeouts on the x86_64-linux-ubsan bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335085
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Vedant Kumar [Tue, 19 Jun 2018 23:42:17 +0000 (23:42 +0000)]
[IR] Introduce helpers to skip debug instructions (NFC)
This patch introduces two helpers to make it easier to ignore debug
intrinsics:
- Instruction::getNextNonDebugInstruction()
This is just like Instruction::getNextNode(), except that it skips debug
info.
- skipDebugInfo(BasicBlock::iterator)
A free function which advances a BasicBlock iterator past any debug
info. This is a no-op when the iterator already points to a non-debug
instruction.
Part of: llvm.org/PR37728
Related to: https://reviews.llvm.org/D47874
Differential Revision: https://reviews.llvm.org/D48305
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335083
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Kuba Mracek [Tue, 19 Jun 2018 22:22:48 +0000 (22:22 +0000)]
[llvm] Document "%T" as deprecated in TestingGuide.rst
Differential Revision: https://reviews.llvm.org/D48189
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335080
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Philip Reames [Tue, 19 Jun 2018 21:19:59 +0000 (21:19 +0000)]
[InlineSpiller] Fix a crash due to lack of forward progress from remat specifically for STATEPOINT
This patch covers up a fairly fundemental issue around remat and register allocation which shows up with psuedo instructions with more vreg uses than there are physical registers. This patch essentially just disables remat for STATEPOINTs which are the only case we've seen so far, but long term we need a better fix.
For STATEPOINTs specifically, this is a strict improvement. It unblocks progress towards enabling a currently off-by-default mode which integrates deopt bundle operand lowering with register allocator spilling so that we end up with smaller stack sizes and more optimally placed spills. Assming no other issues turn up during my next round of integration testing - which based on experience so far, is admittedly unlikely - we might finally be able to enable something I've been working towards in small bits and pieces for years now. :)
For psuedo ops in general, there are a couple of ideas for a "proper fix" discussed on the bug, but I'm far enough outside my knowledge area to not be able to see any of them through to a successful conclusion. If anyone wants to help out here, please do.
Differential Revision: https://reviews.llvm.org/D41098
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335077
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Jessica Paquette [Tue, 19 Jun 2018 21:14:48 +0000 (21:14 +0000)]
[MachineOutliner] NFC: Remove insertOutlinerPrologue, rename insertOutlinerEpilogue
insertOutlinerPrologue was not used by any target, and prologue-esque code was
beginning to appear in insertOutlinerEpilogue. Refactor that into one function,
buildOutlinedFrame.
This just removes insertOutlinerPrologue and renames insertOutlinerEpilogue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335076
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Heejin Ahn [Tue, 19 Jun 2018 20:30:42 +0000 (20:30 +0000)]
[WebAssembly] Fix liveness tracking info after drop insertion
Summary:
This fixes liveness tracking information after `drop` instruction
insertion in ExplicitLocals pass.
When a drop instruction is inserted to drop a dead register operand, the
original operand should be marked not dead anymore because it is now
used by the new drop instruction. And the operand to the new drop
instruction should be marked killed instead. This bug caused some
programs to fail when `llc` is run with `-verify-machineinstrs` option.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D48253
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335074
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Craig Topper [Tue, 19 Jun 2018 19:14:50 +0000 (19:14 +0000)]
[X86] Update fast-isel tests for clang's avx512f reduction intrinsics to match the codegen from r335070.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335071
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Craig Topper [Tue, 19 Jun 2018 18:52:15 +0000 (18:52 +0000)]
[X86] Add fast-isel tests for clang's AVX512F vector reduction intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335068
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Sanjay Patel [Tue, 19 Jun 2018 18:44:00 +0000 (18:44 +0000)]
[IR] move shuffle mask queries from TTI to ShuffleVectorInst
The optimizer is getting smarter (eg, D47986) about differentiating shuffles
based on its mask values, so we should make queries on the mask constant
operand generally available to avoid code duplication.
We'll probably use this soon in the vectorizers and instcombine (D48023 and
https://bugs.llvm.org/show_bug.cgi?id=37806).
We might clean up TTI a bit more once all of its current 'SK_*' options are
covered.
Differential Revision: https://reviews.llvm.org/D48236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335067
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Matt Davis [Tue, 19 Jun 2018 18:39:40 +0000 (18:39 +0000)]
[MIRParser] Update a diagnostic message to use the correct register sigil. NFC
Summary:
Patch r323922 changed the sigil for physical registers to '$', instead of '%'.
An error message was missed during this change, and reports the wrong sigil.
This patch corrects that diagnostic and the tests that check that error string.
Reviewers: zer0, bjope
Reviewed By: bjope
Subscribers: bjope, thegameg, plotfi, llvm-commits
Differential Revision: https://reviews.llvm.org/D48086
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335066
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Krzysztof Parzyszek [Tue, 19 Jun 2018 18:09:54 +0000 (18:09 +0000)]
[Hexagon] Fix the value of HexagonII::TypeCVI_FIRST
This value is the first vector instruction type in numerical order. The
previous value was incorrect, leaving TypeCVI_GATHER outside of the range
for vector instructions. This caused vector .new instructions to be
incorrectly encoded in the presence of gather.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335065
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Craig Topper [Tue, 19 Jun 2018 18:06:52 +0000 (18:06 +0000)]
[X86] Initialize FMA3Info directly in its constructor instead of relying on std::call_once
FMA3Info only exists as a managed static. As far as I know the ManagedStatic construction proccess is thread safe. It doesn't look like we ever access the ManagedStatic object without immediately doing a query on it that would require the map to be populated. So I don't think we're ever deferring the calculation of the tables from the construction of the object.
So I think we should be able to just populate the FMA3Info map directly in the constructor and get rid of all of the initGroupsOnce stuff.
Differential Revision: https://reviews.llvm.org/D48194
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335064
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Craig Topper [Tue, 19 Jun 2018 17:51:42 +0000 (17:51 +0000)]
[X86] Don't fold unaligned loads into SSE ROUNDPS/ROUNDPD for ceil/floor/nearbyint/rint/trunc.
Incorrect patterns were added in r334460. This changes them to check alignment properly for SSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335062
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Krzysztof Parzyszek [Tue, 19 Jun 2018 17:26:20 +0000 (17:26 +0000)]
[Hexagon] Enforce restrictions on packetizing cache instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335061
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Saleem Abdulrasool [Tue, 19 Jun 2018 16:47:31 +0000 (16:47 +0000)]
docs: document CodeView directives
Add documentation for assembler directives added to support CodeView
emission.
Patch by Ellis Hoag!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335058
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Simon Dardis [Tue, 19 Jun 2018 16:05:44 +0000 (16:05 +0000)]
[mips] Mark microMIPS64 as being unsupported.
There are no provided instruction definitions for this architecture.
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D48320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335057
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Simon Dardis [Tue, 19 Jun 2018 15:25:01 +0000 (15:25 +0000)]
[mips] Fix the predicates of some aliases
Previously, some aliases were marked as not being available for microMIPS32R6,
but this was overridden at the top level.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D48321
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335053
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Simon Pilgrim [Tue, 19 Jun 2018 13:40:00 +0000 (13:40 +0000)]
[SLPVectorizer] Remove default OperandValueKind arguments from getArithmeticInstrCost calls (NFC)
The getArithmeticInstrCost calls for shuffle vectors entry costs specify TargetTransformInfo::OperandValueKind arguments, but are just using the method's default values. This seems to be a copy + paste issue and doesn't affect the costs in anyway. The TargetTransformInfo::OperandValueProperties default arguments are already not being used.
Noticed while working on D47985.
Differential Revision: https://reviews.llvm.org/D48008
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335045
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Strahinja Petrovic [Tue, 19 Jun 2018 13:07:40 +0000 (13:07 +0000)]
[PowerPC] Fix label address calculation for ppc32
This patch fixes calculating address of label on ppc32 (for -fPIC).
Differential Revision: https://reviews.llvm.org/D46582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335043
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Roman Lebedev [Tue, 19 Jun 2018 11:58:10 +0000 (11:58 +0000)]
llvm-exegesis: mark ~ExegesisTarget() as virtual. Fixes build.
/build/llvm/tools/llvm-exegesis/lib/X86/../Target.h:32:3: error: 'exegesis::ExegesisTarget' has virtual functions but non-virtual destructor [-Werror,-Wnon-virtual-dtor]
~ExegesisTarget();
^
/build/llvm/tools/llvm-exegesis/lib/X86/Target.cpp:15:7: error: 'exegesis::(anonymous namespace)::ExegesisX86Target' has virtual functions but non-virtual destructor [-Werror,-Wnon-virtual-dtor]
class ExegesisX86Target : public ExegesisTarget {
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335042
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Clement Courbet [Tue, 19 Jun 2018 11:28:59 +0000 (11:28 +0000)]
Re-land r335038 "[llvm-exegesis] A mechanism to add target-specific functionality.""
Fix typo: LLVM_NATIVE_ARCH -> LLVM_EXEGESIS_NATIVE_ARCH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335041
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Clement Courbet [Tue, 19 Jun 2018 10:54:12 +0000 (10:54 +0000)]
Revert r335038 "[llvm-exegesis] A mechanism to add target-specific functionality."
Breaks buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335040
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Mikhail Dvoretckii [Tue, 19 Jun 2018 10:49:12 +0000 (10:49 +0000)]
[InstCombine] Replacing X86-specific rounding intrinsics with generic floor-ceil
This patch replaces calls to X86-specific intrinsics with floor-ceil semantics
with calls to target-independent @llvm.floor.* and @llvm.ceil.* intrinsics. This
doesn't affect the resulting machine code, as those intrinsics are lowered to
the same instructions, but exposes these specific rounding cases to generic
optimizations.
Differential Revision: https://reviews.llvm.org/D48067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335039
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Clement Courbet [Tue, 19 Jun 2018 10:39:50 +0000 (10:39 +0000)]
[llvm-exegesis] A mechanism to add target-specific functionality.
Summary: This is a step towards implementing memory operands and X87.
Reviewers: gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48210
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335038
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Mikhail Dvoretckii [Tue, 19 Jun 2018 10:37:52 +0000 (10:37 +0000)]
[X86] VRNDSCALE* folding from masked and scalar ffloor and fceil patterns
This patch handles back-end folding of generic patterns created by lowering the
X86 rounding intrinsics to native IR in cases where the instruction isn't a
straightforward packed values rounding operation, but a masked operation or a
scalar operation.
Differential Revision: https://reviews.llvm.org/D45203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335037
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David Green [Tue, 19 Jun 2018 09:43:36 +0000 (09:43 +0000)]
[LoopSimplifyCFG] Invalidate SCEV in LoopSimplifyCFG
LoopSimplifyCFG, being a loop pass, needs to preserve scalar
evolution. This invalidates SE for the loops altered during
block merging.
Differential Revision: https://reviews.llvm.org/D48258
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335036
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Roman Lebedev [Tue, 19 Jun 2018 09:21:27 +0000 (09:21 +0000)]
[MCA][NFC] Add generic XOP resource tests
Summary:
Based on
* [[ https://support.amd.com/TechDocs/43479.pdf | AMD64 Architecture Programmer’s Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions ]],
* [[ https://support.amd.com/TechDocs/24594.pdf | AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions]],
* https://en.wikipedia.org/wiki/XOP_instruction_set
Appears to be only supported in AMD's 15h generation, so only in b**d**ver[1-4],
for which currently llvm has no scheduling profiles.
Reviewers: RKSimon, craig.topper, andreadb, spatel
Reviewed By: RKSimon
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335034
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Roman Lebedev [Tue, 19 Jun 2018 09:21:22 +0000 (09:21 +0000)]
[MCA][NFC] Add generic TBM resource tests
Summary:
Based on https://support.amd.com/TechDocs/24594.pdf,
https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)
Appears to be only supported in AMD's 15h generation, so only in b**d**ver[1-4],
for which currently llvm has no scheduling profiles.
Reviewers: RKSimon, craig.topper, simark, andreadb
Reviewed By: RKSimon
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335033
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Simon Pilgrim [Tue, 19 Jun 2018 09:16:06 +0000 (09:16 +0000)]
[SLPVectorizer] Pull out AltOpcode determination from reorderAltShuffleOperands.
Minor step towards making the alternate opcode system work with a wider range of opcode pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335032
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Bjorn Pettersson [Tue, 19 Jun 2018 08:41:34 +0000 (08:41 +0000)]
Remove valueCoversEntireFragment asserts in ConvertDebugDeclareToDebugValue
This is a fixup for r334830 causing problems in polly-aosp buildbot.
Focus in r334830 was to fix a problem seen with
ConvertDebugDeclareToDebugValue involving store instructions.
It also added some asserts to find out of similar problems
existed for the ConvertDebugDeclareToDebugValue functions
involving load and phi instructions. One of those asserts seems
to blow in the polly-aosp buildbot, so I'll revert the asserts
while debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335031
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Adrian Kuegel [Tue, 19 Jun 2018 08:12:28 +0000 (08:12 +0000)]
Add a factory method to ConstantDataArray that allows to pass in the data as StringRef
This simplifies the case if we already have access to the raw data that we need to store in a ConstantDataArray.
The new factor method can also be reused for implementing the factory method that gets the data as ArrayRef.
Differential Revision: https://reviews.llvm.org/D47706
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335028
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Florian Hahn [Tue, 19 Jun 2018 08:03:24 +0000 (08:03 +0000)]
[LoopInterchange] Move PHI handling to adjustLoopBranches.
This patch moves the logic to handle reduction PHI nodes to the end of
adjustLoopBranches. Reduction PHI nodes in the outer loop header can be
moved to the inner loop header and reduction PHI nodes from the inner loop
header can be moved to the outer loop header. In the latter situation,
we have to deal with 1 kind of PHI nodes:
PHI nodes that are part of inner loop-only reductions.
We can replace the PHI node with the value coming from outside
the inner loop.
Reviewers: mcrosier, efriedma, karthikthecool
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D46198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335027
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Mikhail Dvoretckii [Tue, 19 Jun 2018 07:55:10 +0000 (07:55 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335026
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QingShan Zhang [Tue, 19 Jun 2018 06:54:51 +0000 (06:54 +0000)]
If the arch is P9, we will select the DFLOADf32/DFLOADf64 pseudo instruction when we are loading a floating,
and expand it post RA basing on the register pressure. However, we miss to do the add-imm peephole for these pseudo instruction.
Differential Revision: https://reviews.llvm.org/D47568
Reviewed By: Nemanjai
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335024
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Roger Ferrer Ibanez [Tue, 19 Jun 2018 06:45:47 +0000 (06:45 +0000)]
[RISCV] Add tests for overflow intrinsics
This is using the existing codegen so we can see the change once we custom
lower ISD::{U,S}{ADD,SUB}O nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335023
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Max Kazantsev [Tue, 19 Jun 2018 04:48:34 +0000 (04:48 +0000)]
[SimplifyIndVars] Eliminate redundant truncs
This patch adds logic to deal with the following constructions:
%iv = phi i64 ...
%trunc = trunc i64 %iv to i32
%cmp = icmp <pred> i32 %trunc, %invariant
Replacing it with
%iv = phi i64 ...
%cmp = icmp <pred> i64 %iv, sext/zext(%invariant)
In case if it is legal. Specifically, if `%iv` has signed comparison users, it is
required that `sext(trunc(%iv)) == %iv`, and if it has unsigned comparison
uses then we require `zext(trunc(%iv)) == %iv`. The current implementation
bails if `%trunc` has other uses than `icmp`, but in theory we can handle more
cases here (e.g. if the user of trunc is bitcast).
Differential Revision: https://reviews.llvm.org/D47928
Reviewed By: reames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335020
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Craig Topper [Tue, 19 Jun 2018 04:24:44 +0000 (04:24 +0000)]
[X86] Add the ability to force an EVEX2VEX mapping table entry from the .td files. Remove remaining manual table entries from the tablegen emitter.
This adds an EVEX2VEXOverride string to the X86 instruction class in X86InstrFormats.td. If this field is set it will add manual entry in the EVEX->VEX tables that doesn't check the encoding information.
Then use this mechanism to map VMOVDU/A8/16, 128-bit VALIGN, and VPSHUFF/I instructions to VEX instructions.
Finally, remove the manual table from the emitter.
This has the bonus of fully sorting the autogenerated EVEX->VEX tables by their EVEX instruction enum value. We may be able to use this to do a binary search for the conversion and get rid of the need to create a DenseMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335018
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Craig Topper [Tue, 19 Jun 2018 04:24:42 +0000 (04:24 +0000)]
[X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0.
EVEX makes heavy use of the VEX.W bit to indicate 64-bit element vs 32-bit elements. Many of the VEX instructions were split into 2 versions with different masking granularity.
The EVEX->VEX table generate can collapse the two versions if the VEX version uses is tagged as VEX_WIG. But if the VEX version is instead marked VEX.W==0 we can't combine them because we don't know if there is also a VEX version with VEX.W==1.
This patch adds a new VEX_W1X tag that indicates the EVEX instruction encodes with VEX.W==1, but is safe to convert to a VEX instruction with VEX.W==0.
This allows us to remove a bunch of manual EVEX->VEX table entries. We may want to look into splitting up the VEX_WPrefix field which would simplify the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335017
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Sanjoy Das [Tue, 19 Jun 2018 04:09:44 +0000 (04:09 +0000)]
Revert "[SCEV] Add nuw/nsw to mul ops in StrengthenNoWrapFlags"
This reverts r334428. It incorrectly marks some multiplications as nuw. Tim
Shen is working on a proper fix.
Original commit message:
[SCEV] Add nuw/nsw to mul ops in StrengthenNoWrapFlags where safe.
Summary:
Previously we would add them for adds, but not multiplies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335016
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Craig Topper [Tue, 19 Jun 2018 03:17:46 +0000 (03:17 +0000)]
[X86] Simplify the TSFlags checking code in EvexToVexInstPass. NFCI
The code was previously checking the L2 and L flag on 3 separate lines, treating the combination as an encoding. Instead its better to think of the L2 bit as being something that can't be done with VEX and early returning. Then we just need to check the L bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335015
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