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Pierre-Eric Pelloux Prayer [Mon, 23 Sep 2019 09:06:07 +0000 (11:06 +0200)]
mesa: implement glTextureStorageNDEXT functions
Implement the 3 functions using the texturestorage_error() helper.
_mesa_lookup_or_create_texture is always called to make sure that 'texture'
is initialized (even if the texturestorage_error() generates an error afterwards).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Wed, 11 Sep 2019 08:26:50 +0000 (10:26 +0200)]
mesa: add EXT_dsa NamedCopyBufferSubDataEXT function
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Wed, 11 Sep 2019 08:13:21 +0000 (10:13 +0200)]
mesa: add EXT_dsa NamedRenderbufferStorageMultisampleEXT function
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Wed, 11 Sep 2019 08:01:24 +0000 (10:01 +0200)]
mesa: add EXT_dsa Generate*MipmapEXT functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Wed, 11 Sep 2019 07:58:47 +0000 (09:58 +0200)]
mesa: refactor GenerateTextureMipmap handling
Rework _mesa_GenerateTextureMipmap to allow code sharing with EXT_dsa functions.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Wed, 11 Sep 2019 07:30:14 +0000 (09:30 +0200)]
mesa: add EXT_dsa glGetFloati_vEXT/glGetDoublei_vEXT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Mon, 9 Sep 2019 15:26:30 +0000 (17:26 +0200)]
mesa: add EXT_dsa + EXT_gpu_program_parameters functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Mon, 9 Sep 2019 15:14:18 +0000 (17:14 +0200)]
mesa: add EXT_dsa + EXT_gpu_shader4 functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Mon, 9 Sep 2019 14:44:11 +0000 (16:44 +0200)]
mesa: add EXT_dsa + EXT_texture_integer functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Mon, 9 Sep 2019 14:22:29 +0000 (16:22 +0200)]
mesa: add EXT_dsa + EXT_texture_buffer_object functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Mon, 9 Sep 2019 13:53:00 +0000 (15:53 +0200)]
mesa: add EXT_dsa glProgramUniform*EXT functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Tue, 28 May 2019 15:06:00 +0000 (17:06 +0200)]
mesa: add EXT_dsa NamedProgram functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Tue, 28 May 2019 08:27:52 +0000 (10:27 +0200)]
mesa: add EXT_dsa glClientAttribDefaultEXT / glPushClientAttribDefaultEXT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Pierre-Eric Pelloux-Prayer [Thu, 23 May 2019 14:34:16 +0000 (16:34 +0200)]
mesa: add EXT_dsa glNamedRenderbufferStorageEXT and glGetNamedRenderbufferParameterivEXT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Daniel Stone [Thu, 17 Oct 2019 11:49:54 +0000 (13:49 +0200)]
panfrost: Respect offset for imported resources
When we import a resource through Gallium, we need to take account of
the offset parameter passed.
Fixes a failure seen with the VIVID V4L2 driver, which would create NV12
resources within the same BO, with an offset. Sample pipeline to
reproduce (replace videoN with your actual VIVID device node):
gst-launch-1.0 v4l2src device=/dev/videoN ! video/x-raw,format=NV12 ! glimagesink
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reported-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Tested-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Jordan Justen [Fri, 31 May 2019 22:50:53 +0000 (15:50 -0700)]
iris/resource: Use isl surface alignment during bo allocation
Reworks:
* Change subject from "iris: Align main surface allocation to 64k on gen12+"
* Make use of isl surf alignment. (Nanley)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Fri, 4 May 2018 16:43:01 +0000 (09:43 -0700)]
intel/isl: Add isl_aux_usage_has_ccs
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Thu, 12 Apr 2018 05:48:33 +0000 (22:48 -0700)]
intel/isl: Add R10G10B10_FLOAT_A2_UNORM format
Reworks:
* Fill out the format's entry in the ISL format table. (Nanley)
* Support CCS_E-enabled BLORP copies with the format. (Nanley)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Tue, 10 Sep 2019 01:31:41 +0000 (18:31 -0700)]
intel/compiler: Report the number of non-spill/fill SEND messages
This can be useful to measure whether memory access optimizations are
having the desired effect. For example, we might see a reduction in
image loads/stores, or constant buffer loads. We can already see this
in cycle estimates to some extent, but this is a more direct approach,
minus a lot of the noise of random scheduler shuffling.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Marek Olšák [Thu, 17 Oct 2019 00:21:11 +0000 (20:21 -0400)]
st/mesa: don't call variables "tgsi" when they can reference NIR
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Wed, 16 Oct 2019 20:46:19 +0000 (16:46 -0400)]
st/mesa: merge st_fragment_program into st_common_program
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Thu, 17 Oct 2019 18:51:23 +0000 (14:51 -0400)]
st/mesa: remove redundant function st_reference_compprog
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Wed, 16 Oct 2019 20:22:43 +0000 (16:22 -0400)]
st/mesa: remove unused st_xxx_program::sha1
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Wed, 16 Oct 2019 20:19:09 +0000 (16:19 -0400)]
st/mesa: remove st_vp_variant_key in favor of st_common_variant_key
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Wed, 16 Oct 2019 20:10:43 +0000 (16:10 -0400)]
st/mesa: remove num_tgsi_tokens from st_xx_program
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Wed, 16 Oct 2019 20:05:10 +0000 (16:05 -0400)]
st/mesa: rename basic -> common for st_common_program
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Wed, 16 Oct 2019 19:59:41 +0000 (15:59 -0400)]
st/mesa: rename st_xxx_program::tgsi to state
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Tue, 15 Oct 2019 20:49:06 +0000 (16:49 -0400)]
st/mesa: lower doubles for NIR after linking
This allows dropping 1 call to st_nir_opts, because shaders are always
optimized after linking.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Tue, 8 Oct 2019 02:15:01 +0000 (22:15 -0400)]
st/mesa: call st_nir_opts for linked shaders only once
The removed st_nir_opts calls are mostly redundant.
There is an improvement with shader-db on radeonsi:
Before:
real 1m54.047s
user 28m37.857s
sys 0m7.573s
After:
real 1m52.012s
user 28m3.412s
sys 0m7.808s
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Mon, 15 Jul 2019 18:38:55 +0000 (11:38 -0700)]
intel/vec4: Don't try both sources as immediates for DPH
DPH isn't actually commutative, so this doesn't work. If the immediate
in src0 would be a VF candidate, we could do better. *shrug*
No shader-db changes on any Intel platform.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Fixes:
b04beaf41d2 ("intel/vec4: Try both sources as candidates for being immediates")
Ian Romanick [Mon, 15 Jul 2019 22:18:47 +0000 (15:18 -0700)]
nir/search: Fix possible NULL dereference in is_fsign
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Fixes:
09705747d72 ("nir/algebraic: Reassociate fadd into fmul in DPH-like pattern")
Jordan Justen [Fri, 19 Apr 2019 23:28:01 +0000 (16:28 -0700)]
iris: Let isl decide the supported tiling in more situations
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Suggested-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jordan Justen [Fri, 19 Jan 2018 08:48:33 +0000 (00:48 -0800)]
intel/isl: Add gen12 depth/stencil surface alignments
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Tue, 9 Jan 2018 00:28:46 +0000 (16:28 -0800)]
intel/isl: Select Y-tiling for stencil on gen12
Rework:
* Disallow linear 1D stencil buffers (Nanley)
* Force Y for gen12 stencil rather than ~W (Nanley)
Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Tue, 9 Jan 2018 00:27:45 +0000 (16:27 -0800)]
intel/genxml: Remove W-tiling on gen12
It's no longer supported by the hardware
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jordan Justen [Wed, 16 Aug 2017 23:45:47 +0000 (16:45 -0700)]
intel/genxml,isl: Add gen12 stencil buffer changes
Rework:
* NULL stencil buffer path (Jason)
* genxml fixes (Nanley)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jordan Justen [Wed, 16 Aug 2017 23:45:47 +0000 (16:45 -0700)]
intel/genxml,isl: Add gen12 depth buffer changes
Reworks:
* Fix 3DSTATE_DEPTH_BUFFER "Surface Format" end in xml (Jason)
* Remove WM_HZ_OP changes (Nanley)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jordan Justen [Wed, 16 Aug 2017 23:45:47 +0000 (16:45 -0700)]
intel/genxml,isl: Add gen12 render surface state changes
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Eric Anholt [Mon, 19 Aug 2019 22:17:58 +0000 (15:17 -0700)]
mesa: Refactor the entirety of _mesa_format_matches_format_and_type().
This function was difficult to implement for new formats due to the
combination of endianness and swapbytes support. Since it's mostly
used for fast paths, bugs in it were often missed during testing.
Just reimplement it on top of the recent
_mesa_format_from_format_and_type() which can give us a canonical
MESA_FORMAT for a format and type enum (while respecting endianness).
Fixes:
- R4G4B4A4_UNORM, B4G4R4_UINT, R4G4B4A4_UINT incorrectly matched with
swapBytes (you can't just reverse the channels if the channels
aren't bytes)
- A4R4G4B4_UNORM and A4R4G4B4_UINT missing BGRA/4444_REV matches
- failing to match RGB/BGR unorm8 array formats on BE
-
2101010 formats incorrectly matching with swapBytes set.
- UINT/SINT byte formats failed to match with swapBytes set.
This deletes the part of tests/mesa_formats.cpp that called
_mesa_format_matches_format_and_type() to make sure it didn't
assertion fail, as it now would assertion fail due to the fact that we
were passing an invalid format (GL_RG) for most types.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Wed, 18 Sep 2019 21:01:29 +0000 (14:01 -0700)]
mesa: Add support for array formats of depth and stencil.
In desktop GL, you can specify things like GL_DEPTH_COMPONENT/GL_BYTE as a
ReadPixels format, and we need to be able to represent that to see if we
have proper MESA_FORMATs for them. That's exactly what the
mesa_array_format enum is for.
v2: Drop _mesa from static fn.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Wed, 18 Sep 2019 21:27:51 +0000 (14:27 -0700)]
mesa: Add format/type matching for DEPTH/UINT_24_8.
We had missed this case where GLES3 allows glReadPixels(DEPTH, UINT_24_8),
and just got lucky by the readpixels path never asking for the matching
format from this function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 17 Sep 2019 21:54:48 +0000 (14:54 -0700)]
mesa: Fix depth/stencil ordering in _mesa_format_from_format_and_type().
The GL spec says the 24-bit component is in the high bits, and
format_unpack.c looks at the high 24 bits in the S8Z24 case, not
Z24SS8.
Avoids a regression in the next commit.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Wed, 18 Sep 2019 21:46:49 +0000 (14:46 -0700)]
mesa: Add debug info to _mesa_format_from_format_and_type() error path.
The unreachable() that follows isn't very useful for debug, and by adding
this here we get a nice description of the failure in debug builds.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kristian H. Kristensen [Fri, 11 Oct 2019 03:54:28 +0000 (20:54 -0700)]
freedreno/a6xx: Turn on geometry shaders
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Mon, 14 Oct 2019 02:32:37 +0000 (19:32 -0700)]
freedreno/ci: Add failing tests to skip list
Some queries are still failing and layered rending needs more work.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Wed, 16 Oct 2019 19:08:19 +0000 (12:08 -0700)]
freedreno/a6xx: Implement PIPE_QUERY_PRIMITIVES_GENERATED for GS
When we don't have streamout enabled, we have to read this register to
get the number of primitives emitted.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Fri, 11 Oct 2019 22:15:23 +0000 (15:15 -0700)]
freedreno/blitter: Save GS state
We have GS state now.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Thu, 10 Oct 2019 18:27:47 +0000 (11:27 -0700)]
st/mesa: Also enable GS when ESSLVersion > 320
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Fri, 11 Oct 2019 20:56:20 +0000 (13:56 -0700)]
freedreno/a6xx: Support layered render targets
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Fri, 11 Oct 2019 20:43:53 +0000 (13:43 -0700)]
freedreno/a6xx: Emit program state for GS
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Fri, 11 Oct 2019 19:37:38 +0000 (12:37 -0700)]
freedreno/ir3: End VS with CHMASK and CHSH in GS pipelines
When used in a GS pipeline, the VS doesn't end with the END
instruction. Instead it chains to the GS, which continues running with
the same register allocation. The intended use cases seems to be that
you can compile a regular VS (ie outputs in registers and ending with
END) but then tack on link-time generated code past the END to write
the outputs using STLW, in case the VS is used with GS.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Fri, 11 Oct 2019 19:36:49 +0000 (12:36 -0700)]
freedreno/ir3: Start GS with (ss) and (sy)
We don't know what kind of loads we might have to wait on when coming
in from chsh in the VS so set both sync flags.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Fri, 11 Oct 2019 19:34:54 +0000 (12:34 -0700)]
freedreno/ir3: Pre-color GS header and primitive ID
These sysvals have to be unclobbered by VS and in the same registers
in both VS and GS, since the chsh from VS to GS doesn't reload the
values. We use the pre-color argument to ir3_ra() to always place
these values in r0.x and r0.y.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Fri, 11 Oct 2019 19:24:12 +0000 (12:24 -0700)]
freedreno/ir3: Setup ir3 inputs and outputs for GS
Inputs are the GS header, which contains vertex ID, local primitive ID
and thread ID as well as primitive ID. The setup is a little different
from other sysvals, since we always have to receive them in the VS so
that it can pass them on into the GS.
The vertex flag outputs from GS is set up as a proper nir output in
the lowering pass and doesn't need special handling here.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Fri, 11 Oct 2019 04:02:45 +0000 (21:02 -0700)]
freedreno/ir3: Implement primitive layout intrinsics
This implements the load_vs_primitive_stride_ir3,
load_vs_vertex_stride_ir3 and load_primitive_location_ir3 intrinsics,
used for getting the primitive layout strides and locations.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Fri, 11 Oct 2019 00:17:10 +0000 (17:17 -0700)]
freedreno/ir3: Implement lowering passes for VS and GS
This introduces two new lowering passes. One to lower VS to explicit
outputs using STLW and one to lower GS to load input using LDLW and
implement the GS specific functionality.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Thu, 10 Oct 2019 22:37:19 +0000 (15:37 -0700)]
freedreno/ir3: Add has_gs flag to shader key
Since the presence of GS changes how the VS operates we need to track
that in the shader key.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Thu, 10 Oct 2019 22:24:10 +0000 (15:24 -0700)]
freedreno/a6xx: Add missing adjacency primitives to table
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Thu, 10 Oct 2019 22:15:37 +0000 (15:15 -0700)]
freedreno/ir3: Add intrinsics that map to LDLW/STLW
These intrinsics will let us do all the offset calculations in nir,
which is nicer to work with and lets nir_opt_algebraic eat it all up.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Thu, 10 Oct 2019 22:09:49 +0000 (15:09 -0700)]
freedreno/ir3: Add new LDLW/STLW instructions
These access memory used for passing data between geometry stages.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Thu, 10 Oct 2019 21:43:03 +0000 (14:43 -0700)]
freedreno/ir3: Extend RA with mechanism for pre-coloring registers
We'll need to pre-color certain input registers betwee VS and GS
shaders.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Thu, 10 Oct 2019 20:44:14 +0000 (13:44 -0700)]
freedreno/ir3: Use third register for offset for LDL and LDLV
Before, offset held the offset, which can be either immediate or a
register. Use a third register to hold the offset so that we can use
a register.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Thu, 10 Oct 2019 20:21:25 +0000 (13:21 -0700)]
freedreno/ir3: Add support for CHSH and CHMASK instructions
Just add the constructors for now and special case similar to END so
we don't remove them.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Fri, 11 Oct 2019 19:17:54 +0000 (12:17 -0700)]
freedreno/a6xx: Trim a few regs from fd6_emit_restore()
We know what these do an either write them in the program stateobj or
don't need to write them.
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Kristian H. Kristensen [Thu, 10 Oct 2019 22:21:25 +0000 (15:21 -0700)]
freedreno/registers: Update with GS, HS and DS registers
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Eric Anholt [Sun, 6 Oct 2019 02:46:38 +0000 (19:46 -0700)]
freedreno/ci: Ban texsubimage2d_pbo.r16ui_2d, due to two flakes reported.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Marek Olšák [Thu, 17 Oct 2019 20:07:26 +0000 (16:07 -0400)]
st/mesa: silence a warning in st_nir_lower_tex_src_plane
trivial
Marek Olšák [Thu, 17 Oct 2019 20:07:02 +0000 (16:07 -0400)]
gallium/u_blitter: remove an unused variable
trivial
Marek Olšák [Wed, 16 Oct 2019 21:22:20 +0000 (17:22 -0400)]
radeonsi: recreate aux_context after a GPU reset
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Wed, 16 Oct 2019 21:09:29 +0000 (17:09 -0400)]
radeonsi: call the reset callback if get_device_reset_status returns a failure
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Marek Olšák [Wed, 16 Oct 2019 21:12:43 +0000 (17:12 -0400)]
st/mesa: call the reset callback if glGetGraphicsResetStatus returns a failure
so that we immediately set the no-op dispatch
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Caio Marcelo de Oliveira Filho [Fri, 4 Oct 2019 19:30:08 +0000 (12:30 -0700)]
intel/fs/gen12: Add tests for scoreboard pass
Tests the combinations of cases of RAW, WAW and WAR hazards involving
both inorder and outoforder instructions. Also tests that
dependencies combine and propagate correctly through control
flow (loops and conditionals).
v2: Add an extra test illustrating that the non-logical CFG edge
between then-block and else-block is being taking into
account. (Curro)
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Daniel Schürmann [Thu, 17 Oct 2019 13:06:48 +0000 (15:06 +0200)]
aco: don't combine minmax3 if there is a neg or abs modifier in between
This fixes a graphical corruption in HotS.
No pipelinedb changes other than that.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Roland Scheidegger [Thu, 17 Oct 2019 02:14:28 +0000 (04:14 +0200)]
gallivm: Fix saturated signed psub/padd intrinsics on llvm 8
LLVM 8 did remove both the signed and unsigned sse2/avx intrinsics in
the end, and provide arch-independent llvm intrinsics instead.
Fixes a crash when using snorm framebuffers (tested with piglit
arb_color_buffer_float-render GL_RGBA8_SNORM -auto).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
CC: <mesa-stable@lists.freedesktop.org>
Samuel Pitoiset [Wed, 16 Oct 2019 20:51:08 +0000 (22:51 +0200)]
radv: fix DCC fast clear code for intensity formats (correctly)
Previous fix was pretty bogus.
This fixes a rendering regression with Nier (minimap too large).
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1943
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1952
Fixes:
ea92273cea8 ("radv: fix DCC fast clear code for intensity formats")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tomeu Vizoso [Wed, 9 Oct 2019 08:10:44 +0000 (10:10 +0200)]
panfrost: Keep track of active BOs
If two jobs use the same GEM object at the same time, the job that
finishes first will (previous to this commit) close the GEM object, even
if there's a job still referencing it.
To prevent this, have all jobs use the same panfrost_bo for a given GEM
object, so it's only closed once the last job is done with it.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Karol Herbst [Mon, 14 Oct 2019 20:50:58 +0000 (22:50 +0200)]
nv50/ir: remove DUMMY edge type
it was never used
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
James Xiong [Wed, 16 Oct 2019 16:22:22 +0000 (09:22 -0700)]
gallium: do not increase ref count of the new throttle fence
A new throttle fence was initialized to 1, and increased by 1
again when it's put in drawable->throttle_fence; the ref was
decreased by 1 when it's removed from drawable->throttle_fence,
and never reached to 0, caused leak.
Fixes:
ff77bf5cbf7 ("gallium: simplify throttle implementation")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1949
Signed-off-by: James Xiong <james.xiong@intel.com>
Reported-by: Florian Wesch <fw@info-beamer.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Erik Faye-Lund [Mon, 7 Oct 2019 10:19:15 +0000 (12:19 +0200)]
nir: drop unused alpha_ref_float
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Mon, 7 Oct 2019 10:08:55 +0000 (12:08 +0200)]
nir: drop support for using load_alpha_ref_float
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Mon, 7 Oct 2019 10:18:09 +0000 (12:18 +0200)]
v3d: do not report alpha-test as supported
This triggers lowering in the state-tracker, which makes things a bit
simpler.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Mon, 7 Oct 2019 10:07:47 +0000 (12:07 +0200)]
vc4: do not report alpha-test as supported
This triggers lowering in the state-tracker, which makes things a bit
simpler.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Mon, 7 Oct 2019 10:07:20 +0000 (12:07 +0200)]
panfrost: do not report alpha-test as supported
This triggers lowering in the state-tracker, which makes things a bit
simpler.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Thu, 25 Jul 2019 12:06:33 +0000 (14:06 +0200)]
mesa/st: support lowering user-clip-planes automatically
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Thu, 3 Oct 2019 20:53:47 +0000 (16:53 -0400)]
mesa/program: support referencing the clip-space clip-plane state
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Wed, 2 Oct 2019 20:30:45 +0000 (16:30 -0400)]
nir: support feeding state to nir_lower_clip_[vg]s
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Wed, 2 Oct 2019 20:19:08 +0000 (16:19 -0400)]
nir: support lowering clipdist to arrays
This allows us to make sure clipdist is emitted as a scalar array rather
than two vec4s. This matches SPIR-V semantics, and will be useful for
Zink.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Thu, 3 Oct 2019 20:51:19 +0000 (16:51 -0400)]
mesa/gallium: automatically lower two-sided lighting
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Thu, 3 Oct 2019 20:51:03 +0000 (16:51 -0400)]
nir: support derefs in two-sided lighting lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Thu, 3 Oct 2019 20:49:15 +0000 (16:49 -0400)]
mesa/gallium: automatically lower point-size
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Thu, 3 Oct 2019 20:44:29 +0000 (16:44 -0400)]
nir: add lowering-pass for point-size mov
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Thu, 18 Jul 2019 14:29:27 +0000 (16:29 +0200)]
st/mesa: move point_size_per_vertex-logic to helper
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Thu, 3 Oct 2019 20:35:23 +0000 (16:35 -0400)]
mesa/gallium: automatically lower alpha-testing
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Thu, 3 Oct 2019 20:22:58 +0000 (16:22 -0400)]
nir: allow passing alpha-ref state to lowering-code
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Thu, 4 Jul 2019 08:07:27 +0000 (10:07 +0200)]
mesa: expose alpha-ref as a state-variable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Thu, 24 Jan 2019 03:12:10 +0000 (13:12 +1000)]
st/mesa: handling lower flatshading for NIR drivers.
This uses the NIR pass to lower flatshading when the driver
requests it.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Thu, 24 Jan 2019 03:11:22 +0000 (13:11 +1000)]
gallium: add flatshade lowering capability
This allows the driver to request flatshade lowering.
(NIR drivers only so far).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Thu, 24 Jan 2019 03:07:42 +0000 (13:07 +1000)]
nir: add a pass to lower flat shading.
This takes any color or backcolor that has unspecified
shading and converts it to flat shading.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Erik Faye-Lund [Mon, 15 Jul 2019 12:44:48 +0000 (14:44 +0200)]
gallium/u_blitter: set a more sane viewport-state
This actually corresponds to legal GL depth-ranges, because depth-clear
values are always in the 0..1 range in OpenGL.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Wed, 16 Oct 2019 02:20:17 +0000 (22:20 -0400)]
st/mesa: reorder and document code in st_translate_vertex_program
move the TGSI code after the ARB_vp code
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>