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Arnold Schwaighofer [Tue, 26 Mar 2013 15:14:04 +0000 (15:14 +0000)]
Revert ARM Scheduler Model: Add resources instructions, map resources
This reverts commit r177968. It is causing failures in a local build bot.
"fatal error: error in backend: Expected a variant SchedClass"
Original commit message:
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178028
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Benjamin Kramer [Tue, 26 Mar 2013 14:17:42 +0000 (14:17 +0000)]
Remove default case from fully covered switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178025
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Christian Konig [Tue, 26 Mar 2013 14:04:17 +0000 (14:04 +0000)]
R600/SI: improve post ISel folding
Not only fold immediates, but avoid unnecessary copies as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178024
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Christian Konig [Tue, 26 Mar 2013 14:04:12 +0000 (14:04 +0000)]
R600/SI: improve vector interpolation
Prevent loading M0 multiple times.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178023
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Christian Konig [Tue, 26 Mar 2013 14:04:07 +0000 (14:04 +0000)]
R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLE
Just define the address as unknown instead of VReg_32.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178022
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Christian Konig [Tue, 26 Mar 2013 14:04:02 +0000 (14:04 +0000)]
R600/SI: switch back to RegPressure scheduling
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178021
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Christian Konig [Tue, 26 Mar 2013 14:03:57 +0000 (14:03 +0000)]
R600/SI: mark most intrinsics as readnone v2
They read from constant register space anyway.
v2: fix lit tests
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178020
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Christian Konig [Tue, 26 Mar 2013 14:03:50 +0000 (14:03 +0000)]
R600/SI: replace WQM intrinsic
Just enable WQM when we see an LDS interpolation instruction.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178019
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Christian Konig [Tue, 26 Mar 2013 14:03:44 +0000 (14:03 +0000)]
R600/SI: fix ELSE pseudo op handling
Restore the EXEC mask early, otherwise a copy might end up not beeing executed.
Candidate for the mesa stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178018
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Joe Abbey [Tue, 26 Mar 2013 13:58:53 +0000 (13:58 +0000)]
Patch by Gordon Keiser!
If PC or SP is the destination, the disassembler erroneously failed with the
invalid encoding, despite the manual saying that both are fine.
This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a
postindexed load, where the offset 0xc is applied to SP after the load occurs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178017
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Alexey Samsonov [Tue, 26 Mar 2013 13:05:41 +0000 (13:05 +0000)]
[ASan] Change the ABI of __asan_before_dynamic_init function: now it takes pointer to private string with module name. This string serves as a unique module ID in ASan runtime. LLVM part
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178013
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Ulrich Weigand [Tue, 26 Mar 2013 10:57:16 +0000 (10:57 +0000)]
PowerPC: Mark patterns as isCodeGenOnly.
There remain a number of patterns that cannot (and should not)
be handled by the asm parser, in particular all the Pseudo patterns.
This commit marks those patterns as isCodeGenOnly.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178008
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Ulrich Weigand [Tue, 26 Mar 2013 10:56:47 +0000 (10:56 +0000)]
PowerPC: Simplify handling of fixups.
MCTargetDesc/PPCMCCodeEmitter.cpp current has code like:
if (isSVR4ABI() && is64BitMode())
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_toc16));
else
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_lo16));
This is a problem for the asm parser, since it requires knowledge of
the ABI / 64-bit mode to be set up. However, more fundamentally,
at this point we shouldn't make such distinctions anyway; in an assembler
file, it always ought to be possible to e.g. generate TOC relocations even
when the main ABI is one that doesn't use TOC.
Fortunately, this is actually completely unnecessary; that code was added
to decide whether to generate TOC relocations, but that information is in
fact already encoded in the VariantKind of the underlying symbol.
This commit therefore merges those fixup types into one, and then decides
which relocation to use based on the VariantKind.
No changes in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178007
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Ulrich Weigand [Tue, 26 Mar 2013 10:56:22 +0000 (10:56 +0000)]
PowerPC: Simplify FADD in round-to-zero mode.
As part of the the sequence generated to implement long double -> int
conversions, we need to perform an FADD in round-to-zero mode. This is
problematical since the FPSCR is not at all modeled at the SelectionDAG
level, and thus there is a risk of getting floating point instructions
generated out of sequence with the instructions to modify FPSCR.
The current code handles this by somewhat "special" patterns that in part
have dummy operands, and/or duplicate existing instructions, making them
awkward to handle in the asm parser.
This commit changes this by leaving the "FADD in round-to-zero mode"
as an atomic operation on the SelectionDAG level, and only split it up into
real instructions at the MI level (via custom inserter). Since at *this*
level the FPSCR *is* modeled (via the "RM" hard register), much of the
"special" stuff can just go away, and the resulting patterns can be used by
the asm parser.
No significant change in generated code expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178006
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Ulrich Weigand [Tue, 26 Mar 2013 10:55:45 +0000 (10:55 +0000)]
PowerPC: Remove LDrs pattern.
The LDrs pattern is a duplicate of LD, except that it accepts memory
addresses where the displacement is a symbolLo64. An operand type
"memrs" is defined for just that purpose.
However, this wouldn't be necessary if the default "memrix" operand
type were to simply accept 64-bit symbolic addresses directly.
The only problem with that is that it uses "symbolLo", which is
hardcoded to 32-bit.
To fix this, this commit changes "memri" and "memrix" to use new
operand types for the memory displacement, which allow iPTR
instead of i32. This will also make address parsing easier to
implment in the asm parser.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178005
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Ulrich Weigand [Tue, 26 Mar 2013 10:55:20 +0000 (10:55 +0000)]
PowerPC: Remove ADDIL patterns.
The ADDI/ADDI8 patterns are currently duplicated into ADDIL/ADDI8L,
which describe the same instruction, except that they accept a
symbolLo[64] operand instead of a s16imm[64] operand.
This duplication confuses the asm parser, and it actually not really
needed, since symbolLo[64] already accepts immediate operands anyway.
So this commit removes the duplicate patterns.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178004
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Ulrich Weigand [Tue, 26 Mar 2013 10:54:54 +0000 (10:54 +0000)]
PowerPC: Use CCBITRC operand for ISEL patterns.
This commit changes the ISEL patterns to use a CCBITRC operand
instead of a "pred" operand. This matches the actual instruction
text more directly, and simplifies use of ISEL with the asm parser.
In addition, this change allows some simplification of handling
the "pred" operand, as this is now only used by BCC.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178003
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Ulrich Weigand [Tue, 26 Mar 2013 10:53:27 +0000 (10:53 +0000)]
PowerPC: Simplify BLR pattern.
The BLR pattern cannot be recognized by the asm parser in its current form.
This complexity is due to an apparent attempt to enable conditional BLR
variants. However, none of those can ever be generated by current code;
the pattern is only ever created using the default "pred" operand.
To simplify the pattern and allow it to be recognized by the parser,
this commit removes those attempts at conditional BLR support.
When we later come back to actually add real conditional BLR, this
should probably be done via a fully generic conditional branch pattern.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178002
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Ulrich Weigand [Tue, 26 Mar 2013 10:53:03 +0000 (10:53 +0000)]
PowerPC: Move some 64-bit branch patterns.
In PPCInstr64Bit.td, some branch patterns appear in a different sequence
than the corresponding 32-bit patterns in PPCInstrInfo.td.
To simplify future changes that affect both files, this commit moves
those patterns to rearrange them into a similar sequence.
No effect on generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178001
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Christian Konig [Tue, 26 Mar 2013 10:24:20 +0000 (10:24 +0000)]
R600: fix DenseMap with pointer key iteration in the structurizer
Use a MapVector on types where the iteration order matters.
Otherwise we doesn't always produce a deterministic output.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177999
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Alexey Samsonov [Tue, 26 Mar 2013 08:27:39 +0000 (08:27 +0000)]
Add asan/msan to the list of available features in LIT test runner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177994
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Alexey Samsonov [Tue, 26 Mar 2013 07:49:46 +0000 (07:49 +0000)]
Add CMake option LLVM_USE_SANITIZER={Address,Memory,MemoryWithOrigins} to simplify bootstrap of LLVM/Clang under ASan/MSan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177992
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Chandler Carruth [Tue, 26 Mar 2013 03:45:47 +0000 (03:45 +0000)]
Manually update the dependencies in the Makefiles. It turns out that all
that work on the LLVMBuild based dependency specification didn't
actually work, we just now maintain dependencies in *3* places instead
of 2. Yay.
There may still be some missing dependencies, I'm still sifting through
the bots and my builds, but this is a step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177988
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Andrew Trick [Tue, 26 Mar 2013 03:14:53 +0000 (03:14 +0000)]
Fix SCEV forgetMemoizedResults should search and destroy backedge exprs.
Fixes PR15570: SEGV: SCEV back-edge info invalid after dead code removal.
Indvars creates a SCEV expression for the loop's back edge taken
count, then determines that the comparison is always true and
removes it.
When loop-unroll asks for the expression, it contains a NULL
SCEVUnknkown (as a CallbackVH).
forgetMemoizedResults should invalidate the loop back edges expression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177986
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Chandler Carruth [Tue, 26 Mar 2013 02:25:37 +0000 (02:25 +0000)]
Split out the IRReader header and the utility functions it provides into
its own library. These functions are bridging between the bitcode reader
and the ll parser which are in different libraries. Previously we didn't
have any good library to do this, and instead played fast and loose with
a "header only" set of interfaces in the Support library. This really
doesn't work well as evidenced by the recent attempt to add timing logic
to the these routines.
As part of this, make them normal functions rather than weird inline
functions, and sink the implementation into the library. Also clean up
the header to be nice and minimal.
This requires updating lots of build system dependencies to specify that
the IRReader library is needed, and several source files to not
implicitly rely upon the header file to transitively include all manner
of other headers.
If you are using IRReader.h, this commit will break you (the header
moved) and you'll need to also update your library usage to include
'irreader'. I will commit the corresponding change to Clang momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177971
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Arnold Schwaighofer [Tue, 26 Mar 2013 02:01:42 +0000 (02:01 +0000)]
ARM Scheduler Model: Add resources instructions, map resources in subtargets
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177968
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Arnold Schwaighofer [Tue, 26 Mar 2013 02:01:39 +0000 (02:01 +0000)]
ARM Scheduler Model: Partial implementation of the new machine scheduler model
This is very much work in progress. Please send me a note if you start to depend
on the added abstract read/write resources. They are subject to change until
further notice.
The old itinerary is still the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177967
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Nick Lewycky [Tue, 26 Mar 2013 01:29:15 +0000 (01:29 +0000)]
Add missing file to cmake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177963
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Nick Lewycky [Tue, 26 Mar 2013 01:27:52 +0000 (01:27 +0000)]
Add a new watchdog timer interface. The interface does not permit handling timeouts, so
it's only really useful if you're going to crash anyways. Use it in the pretty stack trace
printer to kill the compiler if we hang while printing the stack trace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177962
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Bill Wendling [Tue, 26 Mar 2013 01:10:03 +0000 (01:10 +0000)]
Remove testcase. It's failing on some platforms but not others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177956
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Bill Wendling [Tue, 26 Mar 2013 01:08:02 +0000 (01:08 +0000)]
Hmm...not failing...odd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177955
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Bill Wendling [Tue, 26 Mar 2013 00:46:31 +0000 (00:46 +0000)]
Temporarily XFAIL this test until Michael can look at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177953
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Michael Gottesman [Tue, 26 Mar 2013 00:42:09 +0000 (00:42 +0000)]
[ObjCARC Annotations] Added support for displaying the state of pointers at the bottom/top of BBs of the ARC dataflow analysis for both bottomup and topdown analyses.
This will allow for verification and analysis of the merge function of
the data flow analyses in the ARC optimizer.
The actual implementation of this feature is by introducing calls to
the functions llvm.arc.annotation.{bottomup,topdown}.{bbstart,bbend}
which are only declared. Each such call takes in a pointer to a global
with the same name as the pointer whose provenance is being tracked and
a pointer whose name is one of our Sequence states and points to a
string that contains the same name.
To ensure that the optimizer does not consider these annotations in any
way, I made it so that the annotations are considered to be of IC_None
type.
A test case is included for this commit and the previous
ObjCARCAnnotation commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177952
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Michael Gottesman [Tue, 26 Mar 2013 00:42:04 +0000 (00:42 +0000)]
[ObjCARC Annotations] Implemented ARC annotation metadata to expose the ARC data flow analysis state in the IR via metadata.
Previously the inner works of the data flow analysis in ObjCARCOpts was hard to
get out of the optimizer for analysis of bugs or testing. All of the current ARC
unit tests are based off of testing the effect of the data flow
analysis (i.e. what statements are removed or moved, etc.). This creates
weakness in the current unit testing regimem since we are not actually testing
what effects various instructions have on the modeled pointer state.
Additionally in order to analyze a bug in the optimizer, one would need to track
by hand what the optimizer was actually doing either through use of DEBUG
statements or through the usage of a debugger, both yielding large loses in
developer productivity.
This patch deals with these two issues by providing ARC annotation
metadata that annotates instructions with the state changes that they cause in
various pointers as well as provides metadata to annotate provenance sources.
Specifically, we introduce the following metadata types:
1. llvm.arc.annotation.bottomup.
2. llvm.arc.annotation.topdown.
3. llvm.arc.annotation.provenancesource.
llvm.arc.annotation.{bottomup,topdown}: These annotations describes a state
change in a pointer when we are visiting instructions bottomup/topdown
respectively. The output format for both is the same:
!1 = metadata !{metadata !"(test,%x)", metadata !"S_Release", metadata !"S_Use"}
The first element is a string tuple with the following format:
(function,variable name)
The second two elements of the metadata show the previous state of the
pointer (in this case S_Release) and the new state of the pointer (S_Use). We
write the metadata in such a manner to ensure that it is easy for outside tools
to parse. This is important since I am currently working on a tool for taking
this information and pretty printing it besides the IR and that can be used for
LIT style testing via the generation of an index.
llvm.arc.annotation.provenancesource: This metadata is used to annotate
instructions which act as provenance sources, i.e. ones that introduce a
new (from the optimizer's perspective) non-argument pointer to track. This
enables cross-referencing in between provenance sources and the state changes
that occur to them.
This is still a work in progress. Additionally I plan on committing
later today additions to the annotations that annotate at the top/bottom
of basic blocks the state of the various pointers being tracked.
*NOTE* The metadata support is conditionally compiled into libObjCARCOpts only
when we are producing a debug build of llvm/clang and even so are
disabled by default. To enable the annotation metadata, pass in
-enable-objc-arc-annotations to opt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177951
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Michael Gottesman [Tue, 26 Mar 2013 00:34:27 +0000 (00:34 +0000)]
Added documentation to LangRef for the intrinsic llvm.ptr.annotation.* which for some reason was never written.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177950
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Michael Liao [Mon, 25 Mar 2013 23:50:10 +0000 (23:50 +0000)]
Revise alignment checking/calculation on 256-bit unaligned memory access
- It's still considered aligned when the specified alignment is larger
than the natural alignment;
- The new alignment for the high 128-bit vector should be min(16,
alignment) as the pointer is advanced by 16, a power-of-2 offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177947
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Michael Liao [Mon, 25 Mar 2013 23:47:35 +0000 (23:47 +0000)]
Enhance folding of (extract_subvec (insert_subvec V1, V2, IIdx), EIdx)
- Handle the case where the result of 'insert_subvect' is bitcasted
before 'extract_subvec'. This removes the redundant insertf128/extractf128
pair on unaligned 256-bit vector load/store on vectors of non 64-bit integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177945
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Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:43:23 +0000 (23:43 +0000)]
Add an -mcpu option to a test that is apparently scheduler-sensitive.
This should fix the clang-atom-d2700-ubuntu-rel buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177943
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Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:37:17 +0000 (23:37 +0000)]
Add a scheduling model for Intel Sandy Bridge microarchitecture.
The model isn't hooked up by this patch because the instruction set
isn't fully annotated yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177942
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Douglas Gregor [Mon, 25 Mar 2013 23:14:19 +0000 (23:14 +0000)]
Introduce a tiny CMake project to gather Subversion revision information and place it into a header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177938
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Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:12:41 +0000 (23:12 +0000)]
Remove IIC_DEFAULT from X86Schedule.td
All the instructions tagged with IIC_DEFAULT had nothing in common, and
we already have a NoItineraries class to represent untagged
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177937
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Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:07:35 +0000 (23:07 +0000)]
Annotate X86InstrCompiler.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177936
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Jakob Stoklund Olesen [Mon, 25 Mar 2013 23:07:32 +0000 (23:07 +0000)]
Annotate shifts and rotates with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177935
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Shuxin Yang [Mon, 25 Mar 2013 22:52:29 +0000 (22:52 +0000)]
Disable some unsafe-fp-math DAG-combine transformation after legalization.
For instance, following transformation will be disabled:
x + x + x => 3.0f * x;
The problem of these transformations is that it introduces a FP constant, which
following Instruction-Selection pass cannot handle.
Reviewed by Nadav, thanks a lot!
rdar://
13445387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177933
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John McCall [Mon, 25 Mar 2013 22:09:52 +0000 (22:09 +0000)]
Add an optimizer-side test case for ARC bug <rdar://
13195034>, fixed
in the frontend with @clang.arc.use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177928
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Eric Christopher [Mon, 25 Mar 2013 21:26:36 +0000 (21:26 +0000)]
Couple more sets of tidying.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177920
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Jyotsna Verma [Mon, 25 Mar 2013 21:15:11 +0000 (21:15 +0000)]
Disable profiling tests for Hexagon since it doesn't support JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177917
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NAKAMURA Takumi [Mon, 25 Mar 2013 21:07:53 +0000 (21:07 +0000)]
llvm/test/CodeGen/X86/atomic{32|64}.ll: Unmark them out of XFAIL:win32.
I know it is incorrect and they'd fail with +Asserts for win32 targets, though.
I'll try to fix them tonight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177914
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Jyotsna Verma [Mon, 25 Mar 2013 21:04:16 +0000 (21:04 +0000)]
XFAIL some of the generic CodeGen tests for Hexagon.
test/CodeGen/Generic/2008-02-20-MatchingMem.ll: Test contains inline assembly not supported by Hexagon.
Following tests are XFAILed due to multiple return values which Hexagon doesn't support.
test/CodeGen/Generic/multiple-return-values-cross-block-with-invoke.ll
test/CodeGen/Generic/select-cc.ll
test/CodeGen/Generic/vector.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177912
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NAKAMURA Takumi [Mon, 25 Mar 2013 20:55:49 +0000 (20:55 +0000)]
X86DisassemblerDecoder.c: Make this C89-compliant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177910
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NAKAMURA Takumi [Mon, 25 Mar 2013 20:55:43 +0000 (20:55 +0000)]
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177909
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Shuxin Yang [Mon, 25 Mar 2013 20:43:41 +0000 (20:43 +0000)]
Fix a bug in fast-math fadd/fsub simplification.
The problem is that the code mistakenly took for granted that following constructor
is able to create an APFloat from a *SIGNED* integer:
APFloat::APFloat(const fltSemantics &ourSemantics, integerPart value)
rdar://
13486998
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177906
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Shankar Easwaran [Mon, 25 Mar 2013 20:26:47 +0000 (20:26 +0000)]
[ELF] dont compute symbolname size in every loop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177903
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Jyotsna Verma [Mon, 25 Mar 2013 20:20:34 +0000 (20:20 +0000)]
XFAIL DebugInfo tests for Hexagon.
Hexagon does not support -filetype=obj(direct object generation) flag. Therefore,
the following tests are being XFAILed:
test/DebugInfo/dwarf-public-names.ll
test/DebugInfo/member-pointers.ll
test/DebugInfo/two-cus-from-same-file.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177901
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Akira Hatanaka [Mon, 25 Mar 2013 20:11:16 +0000 (20:11 +0000)]
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177899
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Eric Christopher [Mon, 25 Mar 2013 20:05:35 +0000 (20:05 +0000)]
Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177898
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Jyotsna Verma [Mon, 25 Mar 2013 20:02:14 +0000 (20:02 +0000)]
Disable Execution Engine tests not supported by Hexagon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177896
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Shankar Easwaran [Mon, 25 Mar 2013 19:50:40 +0000 (19:50 +0000)]
reflect comment to the official reference
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177895
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NAKAMURA Takumi [Mon, 25 Mar 2013 19:47:20 +0000 (19:47 +0000)]
Disable, for now, llvm/test/Transforms/GCOVProfiling on win32. I'll investigate them later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177894
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Ulrich Weigand [Mon, 25 Mar 2013 19:05:30 +0000 (19:05 +0000)]
Use direct types in PowerPC instruction patterns.
This commit updates the PowerPC back-end (PPCInstrInfo.td and
PPCInstr64Bit.td) to use types instead of register classes in
instruction patterns, along the lines of Jakob Stoklund Olesen's
changes in r177835 for Sparc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177890
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Ulrich Weigand [Mon, 25 Mar 2013 19:04:58 +0000 (19:04 +0000)]
Use direct types in PowerPC Pat patterns.
This commit updates the PowerPC back-end (PPCInstrInfo.td and
PPCInstr64Bit.td) to use types instead of register classes in
Pat patterns, along the lines of Jakob Stoklund Olesen's
changes in r177829 for Sparc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177889
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Dave Zarzycki [Mon, 25 Mar 2013 18:59:43 +0000 (18:59 +0000)]
x86 -- add the XTEST instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888
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Dave Zarzycki [Mon, 25 Mar 2013 18:59:38 +0000 (18:59 +0000)]
x86 -- disassemble the REP/REPNE prefix when needed
This fixes Apple bug:
13493622
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177887
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Chad Rosier [Mon, 25 Mar 2013 18:36:19 +0000 (18:36 +0000)]
Remove unnecessary attributes from test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177882
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Bill Wendling [Mon, 25 Mar 2013 17:42:20 +0000 (17:42 +0000)]
Remove assert. There may be target-dependent attributes left.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177878
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Dmitri Gribenko [Mon, 25 Mar 2013 17:08:25 +0000 (17:08 +0000)]
Documentation: Replace dead link for binfmt_misc
Patch by Thomas Schwinge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177876
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Chad Rosier [Mon, 25 Mar 2013 16:29:20 +0000 (16:29 +0000)]
[arm load/store optimizer] When trying to merge a base update load/store, make
sure the base register and would-be writeback register don't conflict for
stores. This was already being done for loads.
Unfortunately, it is rather difficult to create a test case for this issue. It
was exposed in 450.soplex at LTO and requires unlucky register allocation.
<rdar://
13394908>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177874
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Shankar Easwaran [Mon, 25 Mar 2013 16:06:51 +0000 (16:06 +0000)]
[tools][llvm-readobj] print the name of the section when iterating the symbol table / dynamic symbol table
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177873
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Shankar Easwaran [Mon, 25 Mar 2013 16:02:10 +0000 (16:02 +0000)]
[ELF] add elf_hash function to compute the hash value of a symbol in the dynamic symbol table
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177872
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Duncan Sands [Mon, 25 Mar 2013 14:12:21 +0000 (14:12 +0000)]
Teach cmake about the new Erlang GC files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177869
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Yiannis Tsiouris [Mon, 25 Mar 2013 13:47:46 +0000 (13:47 +0000)]
Add a GC plugin for Erlang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177867
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Duncan Sands [Mon, 25 Mar 2013 13:25:34 +0000 (13:25 +0000)]
Don't use add_llvm_definitions for adding warning flags. It makes it too hard
to have them appear in the right order. Instead append all warnings explicitly
to the language flags. This was already the case for many warnings. Fixes the
issue of -Wno-maybe-uninitialized not being effective because -Wall was being
placed after it rather than before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177866
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Joerg Sonnenberger [Mon, 25 Mar 2013 13:13:33 +0000 (13:13 +0000)]
Refine fenv.h handling: check if the desired macros exist, before using
it. NetBSD/ARM and TILE-Gx are examples for platforms that have an
unusable fenv.h and this avoids the need for a blacklist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177865
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Arnaud A. de Grandmaison [Mon, 25 Mar 2013 11:47:38 +0000 (11:47 +0000)]
Address issues found by Duncan during post-commit review of r177856.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177863
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Arnaud A. de Grandmaison [Mon, 25 Mar 2013 09:48:49 +0000 (09:48 +0000)]
InstCombine: simplify comparisons to zero of (shl %x, Cst) or (mul %x, Cst)
This simplification happens at 2 places :
- using the nsw attribute when the shl / mul is used by a sign test
- when the shl / mul is compared for (in)equality to zero
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177856
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Michael Gottesman [Mon, 25 Mar 2013 09:27:43 +0000 (09:27 +0000)]
Changed isNullOrUndef => IsNullOrUndef and isNoopInstruction => IsNoopInstruction so that all helper functions are named similarly in ObjCARC.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177855
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Jakob Stoklund Olesen [Mon, 25 Mar 2013 00:36:53 +0000 (00:36 +0000)]
Mention the new TableGen pattern format in the release notes.
Make threats about removing the old syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177848
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Justin Holewinski [Sun, 24 Mar 2013 21:17:47 +0000 (21:17 +0000)]
[NVPTX] Fix handling of vector arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177847
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Jakob Stoklund Olesen [Sun, 24 Mar 2013 19:37:04 +0000 (19:37 +0000)]
Clean up Sparc patterns.
The types of register variables no longer need to be specified in output
patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177845
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Jakob Stoklund Olesen [Sun, 24 Mar 2013 19:37:00 +0000 (19:37 +0000)]
Allow types to be omitted in output patterns.
This syntax is now preferred:
def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;
There is no reason to repeat the types in the output pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177844
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Jakob Stoklund Olesen [Sun, 24 Mar 2013 19:36:51 +0000 (19:36 +0000)]
Allow TableGen DAG arguments to be just a name.
DAG arguments can optionally be named:
(dag node, node:$name)
With this change, the node is also optional:
(dag node, node:$name, $name)
The missing node is treated as an UnsetInit, so the above is equivalent
to:
(dag node, node:$name, ?:$name)
This syntax is useful in output patterns where we currently require the
types of variables to be repeated:
def : Pat<(subc i32:$b, i32:$c), (SUBCCrr i32:$b, i32:$c)>;
This is preferable:
def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177843
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Tobias Grosser [Sun, 24 Mar 2013 15:15:19 +0000 (15:15 +0000)]
GettingStarted: Add Git clone instructions for compiler-rt and test-suite
Contributed-by: Thomas Schwinge <thomas@codesourcery.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177841
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Jakub Staszak [Sun, 24 Mar 2013 09:56:28 +0000 (09:56 +0000)]
Minor cleanups. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177837
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Jakub Staszak [Sun, 24 Mar 2013 09:25:47 +0000 (09:25 +0000)]
Use dyn_cast instead of isa && cast.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177836
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Jakob Stoklund Olesen [Sun, 24 Mar 2013 00:56:20 +0000 (00:56 +0000)]
Give Sparc instruction patterns direct types instead of register classes.
Also update the documentation since Sparc is the nicest backend, and
used as an example in WritingAnLLVMBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177835
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Jakob Stoklund Olesen [Sun, 24 Mar 2013 00:56:16 +0000 (00:56 +0000)]
Allow direct value types to be used in instruction 'set' patterns.
This makes it possible to define instruction patterns like this:
def LDri : F3_2<3,
0b000000,
(outs IntRegs:$dst), (ins MEMri:$addr),
"ld [$addr], $dst",
[(set i32:$dst, (load ADDRri:$addr))]>;
~~~
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177834
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Hal Finkel [Sat, 23 Mar 2013 22:06:07 +0000 (22:06 +0000)]
PPC ZERO register needs a register number of 0.
In order for the new ZERO register to be used with MC, etc. we need to specify
its register number (0).
Thanks to Kai for reporting the problem!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177833
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Hal Finkel [Sat, 23 Mar 2013 22:06:03 +0000 (22:06 +0000)]
Note in PPCFunctionInfo VRSAVE spills
In preparation for using the new register scavenger capability for providing
more than one register simultaneously, specifically note functions that have
spilled VRSAVE (currently, this can happen only in functions that use the
setjmp intrinsic). As with CR spilling, such functions will need to provide two
emergency spill slots to the scavenger.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177832
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Hal Finkel [Sat, 23 Mar 2013 20:53:15 +0000 (20:53 +0000)]
MCize the bcl instruction in PPCAsmPrinter
I recently added a BCL instruction definition as part of implementing SjLj
support. This can also be used to MCize bcl emission in the asm printer.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177830
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Jakob Stoklund Olesen [Sat, 23 Mar 2013 20:35:05 +0000 (20:35 +0000)]
Use direct types in Sparc def : Pat patterns.
The SelectionDAG graph has MVT type labels, not register classes, so
this makes it clearer what is happening.
This notation is also robust against adding more types to the IntRegs
register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177829
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Jakob Stoklund Olesen [Sat, 23 Mar 2013 20:35:01 +0000 (20:35 +0000)]
Allow direct value types in pattern definitions.
Just like register classes, value types can be used in two ways in
patterns:
(sext_inreg i32:$src, i16)
In a named leaf node like i32:$src, the value type simply provides the
type of the node directly. This simplifies type inference a lot compared
to the current practice of specifiying types indirectly with register
classes.
As an unnamed leaf node, like i16 above, the value type represents
itself as an MVT::Other immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177828
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Hal Finkel [Sat, 23 Mar 2013 19:36:47 +0000 (19:36 +0000)]
Cleanup some unused reg. scavenger parameters in PPCRegisterInfo
These spilling functions will eventually make use of the register scavenger,
however, they'll do so by taking advantage of PEI's virtual-register-based
delayed scavenging mechanism. As a result, these function parameters will not
be used, and can be removed.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177827
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Jakob Stoklund Olesen [Sat, 23 Mar 2013 18:08:44 +0000 (18:08 +0000)]
Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.
A register class can appear as a leaf TreePatternNode with and without a
name:
(COPY_TO_REGCLASS GPR:$src, F8RC)
In a named leaf node like GPR:$src, the register class provides type
information for the named variable represented by the node. The TypeSet
for such a node is the set of value types that the register class can
represent.
In an unnamed leaf node like F8RC above, the register class represents
itself as a kind of immediate. Such a node has the type MVT::i32,
we'll never create a virtual register representing it.
This change makes it possible to remove the special handling of
COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177825
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Hal Finkel [Sat, 23 Mar 2013 17:14:27 +0000 (17:14 +0000)]
Remove dead PPC LR spilling code
The LR register is unconditionally reserved, and its spilling and restoration
is handled by the prologue/epilogue code. As a result, it is never explicitly
spilled by the register allocator.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177823
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Benjamin Kramer [Sat, 23 Mar 2013 13:56:23 +0000 (13:56 +0000)]
Plug a memory leak in FileCheck when the input file is empty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177822
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Benjamin Kramer [Sat, 23 Mar 2013 09:35:44 +0000 (09:35 +0000)]
Move X86-dependent test into the right subdirectory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177821
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Owen Anderson [Sat, 23 Mar 2013 08:26:53 +0000 (08:26 +0000)]
Remove the type legality check from the SelectionDAGBuilder when it lowers @llvm.fmuladd to ISD::FMA nodes.
Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA.
For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's.
NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook. They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177820
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Michael Gottesman [Sat, 23 Mar 2013 05:46:19 +0000 (05:46 +0000)]
Change method name ClearRefCount => ClearKnownPositiveRefCount to match the name of the member that it is modifying.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177818
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Michael Gottesman [Sat, 23 Mar 2013 05:31:01 +0000 (05:31 +0000)]
Changed the method name PtrState.IsKnownIncremented() to PtrState.HasKnownPositiveRefCount().
Now said method matches namewise every other method which refers to
the member KnownPositiveRefCount of the class PtrState.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177816
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Hal Finkel [Sat, 23 Mar 2013 00:07:29 +0000 (00:07 +0000)]
Fix comparison of mixed signedness
177774 broke the lld-x86_64-darwin11 builder; error:
error: comparison of integers of different signs: 'int' and 'size_type' (aka 'unsigned long')
for (SI = 0; SI < Scavenged.size(); ++SI)
~~ ^ ~~~~~~~~~~~~~~~~
Fix this by making SI also unsigned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177780
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