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Andrei Elovikov [Tue, 20 Mar 2018 09:04:39 +0000 (09:04 +0000)]
[LV] Let recordVectorLoopValueForInductionCast to check if IV was created from the cast.
Summary:
It turned out to be error-prone to expect the callers to handle that - better to
leave the decision to this routine and make the required data to be explicitly
passed to the function.
This handles the case that was missed in the r322473 and fixes the assert
mentioned in PR36524.
Reviewers: dorit, mssimpso, Ayal, dcaballe
Reviewed By: dcaballe
Subscribers: Ka-Ka, hiraditya, dneilson, hsaito, llvm-commits
Differential Revision: https://reviews.llvm.org/D43812
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327960
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Jonas Paulsson [Tue, 20 Mar 2018 08:29:19 +0000 (08:29 +0000)]
[SystemZ] Add "REQUIRES: asserts" to test case to fix build bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327958
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Martin Storsjo [Tue, 20 Mar 2018 06:19:38 +0000 (06:19 +0000)]
[X86] Properly implement the calling convention for f80 for mingw/x86_64
In these cases, both parameters and return values are passed
as a pointer to a stack allocation.
MSVC doesn't use the f80 data type at all, while it is used
for long doubles on mingw.
Normally, this part of the calling convention is handled
within clang, but for intrinsics that are lowered to libcalls,
it may need to be handled within llvm as well.
Differential Revision: https://reviews.llvm.org/D44592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327957
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Lang Hames [Tue, 20 Mar 2018 05:56:58 +0000 (05:56 +0000)]
[ORC] Don't fully qualify explicit destructor call -- it confuses some compilers.
This should fix the builder failure at
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/19224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327955
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Craig Topper [Tue, 20 Mar 2018 05:00:20 +0000 (05:00 +0000)]
[X86] Rename MOVSX32_NOREXrr8 to MOVSX32rr8_NOREX so that the scheduler model regular expressions will pick it up with the regular version.
Do the same for MOVSX32_NOREXrm8, MOVZX32_NOREXrr8, and MOVZX32_NOREXrm8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327948
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Craig Topper [Tue, 20 Mar 2018 03:55:17 +0000 (03:55 +0000)]
[X86] Fix the SchedRW for memory forms of CMP and TEST.
They were incorrectly marked as RMW operations. Some of the CMP instrucions worked, but the ones that use a similar encoding as RMW form of ADD ended up marked as RMW.
TEST used the same tablegen class as some of the CMPs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327947
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Lang Hames [Tue, 20 Mar 2018 03:49:29 +0000 (03:49 +0000)]
[ORC] Rename SymbolSource to MaterializationUnit, and make the materialization
operation all-or-nothing, rather than allowing materialization on a per-symbol
basis.
This addresses a shortcoming of per-symbol materialization: If a
MaterializationUnit (/SymbolSource) wants to materialize more symbols than
requested (which is likely: most materializers will want to materialize whole
modules) then it needs a way to notify the symbol table about the extra symbols
being materialized. This process (checking what has been requested against what
is being provided and notifying the symbol table about the difference) has to
be repeated at every level of the JIT stack. Making materialization
all-or-nothing eliminates this issue, simplifying both materializer
implementations and the symbol table (VSO class) API. The cost is that
per-symbol materialization (e.g. for individual symbols in a module) now
requires multiple MaterializationUnits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327946
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Craig Topper [Tue, 20 Mar 2018 03:02:03 +0000 (03:02 +0000)]
[X86] Add TEST16mi/TEST32mi/TEST64mi32 to the Sandybridge/Haswell/Broadwell/Skylake scheduler models.
Move it from a load+store group on SNB to a load only group, the same group as CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327944
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Craig Topper [Tue, 20 Mar 2018 03:01:59 +0000 (03:01 +0000)]
[X86] Add ROR/ROL/SHR/SAR by 1 instructions to the Sandy Bridge scheduler model.
I assume these match the generic immediate version like they do in the other models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327943
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Quentin Colombet [Tue, 20 Mar 2018 02:44:40 +0000 (02:44 +0000)]
[ShrinkWrap] Take into account landing pad
When scanning the function for CSRs uses and defs, also check if
the basic block are landing pads.
Consider that landing pads needs the CSRs to be properly set.
That way we force the prologue/epilogue to always be pushed out
of the problematic "throw" region. The "throw" region is
problematic because the jumps are not properly modeled.
Fixes PR36513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327942
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David Blaikie [Tue, 20 Mar 2018 02:14:50 +0000 (02:14 +0000)]
Fix layering between llvm-c and Support by factoring out some typedefs into Support
llvm-c depends on Support, but Support (TargetRegistry) uses some of
llvm-c's typedefs. Move those into a Support header to be used from both
llvm-c and Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327940
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Shiva Chen [Tue, 20 Mar 2018 01:39:17 +0000 (01:39 +0000)]
[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects
E.g.
bar (int x)
{
char p[x];
push outgoing variables for foo.
call foo
}
We need to generate stack adjustment instructions for outgoing arguments by
eliminateCallFramePseudoInstr when the function contains variable size
objects to avoid outgoing variables corrupt the variable size object.
Default hasReservedCallFrame will return !hasFP().
We don't want to generate extra sp adjustment instructions when hasFP()
return true, So We override hasReservedCallFrame as !hasVarSizedObjects().
Differential Revision: https://reviews.llvm.org/D43752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327938
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Craig Topper [Tue, 20 Mar 2018 01:30:21 +0000 (01:30 +0000)]
[X86] Fix the SNB scheduler for BLENDVB.
PBLENDVBrr0 was with the memory version of VBLENDVB and PBLENDVBrm0 was missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327937
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Rafael Espindola [Tue, 20 Mar 2018 01:06:29 +0000 (01:06 +0000)]
Run dos2unix on a test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327934
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Aaron Smith [Tue, 20 Mar 2018 01:04:21 +0000 (01:04 +0000)]
[DebugInfoPDB] Add backward support flags to PDB_NameSearchFlags
For NS_CaseInFileNameExt support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327933
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Vitaly Buka [Tue, 20 Mar 2018 00:45:03 +0000 (00:45 +0000)]
Object: Fix handling of @@@ in .symver directive
Summary:
name@@@nodename is going to be replaced with name@@nodename if symbols is
defined in the assembled file, or name@nodename if undefined.
https://sourceware.org/binutils/docs/as/Symver.html
Fixes PR36623
Reviewers: pcc, espindola
Subscribers: mehdi_amini, hiraditya
Differential Revision: https://reviews.llvm.org/D44274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327930
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Vitaly Buka [Tue, 20 Mar 2018 00:38:33 +0000 (00:38 +0000)]
Object: Move attribute calculation into RecordStreamer. NFC
Summary: Preparation for D44274
Reviewers: pcc, espindola
Subscribers: hiraditya
Differential Revision: https://reviews.llvm.org/D44276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327928
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Aaron Smith [Mon, 19 Mar 2018 22:58:50 +0000 (22:58 +0000)]
[SelectionDAG] Transfer DbgValues when integer operations are promoted
Summary:
DbgValue nodes were not transferred when integer DAG nodes were promoted. For example, if an i32 add node was promoted to an i64 add node by DAGTypeLegalizer::PromoteIntegerResult(), its DbgValue node was not transferred to the new node. The simple fix is to update SetPromotedInteger() to transfer DbgValues.
Add AArch64/dbg-value-i8.ll to test this change and fix ARM/debug-info-d16-reg.ll which had the wrong DILocalVariable nodes with arg numbers even though they are not for function parameters.
Patch by Se Jong Oh!
Reviewers: vsk, JDevlieghere, aprantl
Reviewed By: JDevlieghere
Subscribers: javed.absar, kristof.beyls, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D44546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327919
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Jessica Paquette [Mon, 19 Mar 2018 22:48:40 +0000 (22:48 +0000)]
[MachineOutliner] AArch64: Emit CFI instructions when outlining calls
When outlining calls, the outliner needs to update CFI to ensure that, say,
exception handling works. This commit adds that functionality and adds a test
just for call outlining.
Call outlining stuff in machine-outliner.mir should be moved into
machine-outliner-calls.mir in a later commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327917
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Craig Topper [Mon, 19 Mar 2018 22:25:26 +0000 (22:25 +0000)]
[DAGCombiner] Fix type in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327916
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Craig Topper [Mon, 19 Mar 2018 21:58:02 +0000 (21:58 +0000)]
[X86] Simplify the AVX512 code in LowerTruncate a little.
We don't need to create an ISD::TRUNCATE node to return, we started with one and can return it. Also remove the call to getExtendInVec, the result is just going to be a getNode of that value passed in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327914
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Serge Guelton [Mon, 19 Mar 2018 21:35:30 +0000 (21:35 +0000)]
Accept any filepath in llvm_check_source_file_list
Cmake function llvm_check_source_file_list currently only accepts paths
relative to current CMAKE_SOURCE_DIR or relative to argument SOURCE_DIR.
Extend it to accept any path, including absolute ones.
Differential revision: https://reviews.llvm.org/D44625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327912
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Aaron Smith [Mon, 19 Mar 2018 21:20:04 +0000 (21:20 +0000)]
[PDB] Add a method to get the full path of the source file for PDBSymbolCompiland
Summary:
Redefine PDBSymbolCompiland::getSourceFileName() to return the filename (w/o directory) of the source file that is used to compile the compiland. This is because the result returned previously is ambiguous. It could be the filename, relative path or full path of the source file.
Move the implementation of SymbolFilePDB::GetSourceFileNameForPDBCompiland() into a new method PDBSymbolCompiland::getSourceFileFullPath().
Reviewers: zturner, rnk, llvm-commits
Reviewed By: zturner
Differential Revision: https://reviews.llvm.org/D44458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327910
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Aaron Smith [Mon, 19 Mar 2018 21:18:39 +0000 (21:18 +0000)]
[PDB] Add exclusive methods to derived symbol class
Summary: This commit adds two methods to the PDBSymboFunc class used in parsing symbols. getLineNumbers() is used to determine a Function symbol's declaration and getCompilandId() is used to initialize the SymbolContext field sc.comp_unit.
Reviewers: zturner, rnk, llvm-commits
Reviewed By: zturner
Differential Revision: https://reviews.llvm.org/D44457
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327909
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Krzysztof Parzyszek [Mon, 19 Mar 2018 21:05:21 +0000 (21:05 +0000)]
[Hexagon] Add REQUIRES: asserts to test/CodeGen/Hexagon/v6vec_inc1.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327907
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Zachary Turner [Mon, 19 Mar 2018 20:41:59 +0000 (20:41 +0000)]
Revert "Support embedding natvis files in PDBs."
This is causing a test failure on a certain bot, so I'm removing
this temporarily until we can figure out the source of the error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327903
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Zachary Turner [Mon, 19 Mar 2018 20:22:48 +0000 (20:22 +0000)]
Remove an unused private variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327900
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Craig Topper [Mon, 19 Mar 2018 20:20:22 +0000 (20:20 +0000)]
[X86] Replace a couple calls to getExtendInVec with getNode and the appropriate target independent EXTEND_VECTOR_INREG opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327899
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Nirav Dave [Mon, 19 Mar 2018 20:19:46 +0000 (20:19 +0000)]
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
Reland ISel cycle checking improvements after simplifying node id
invariant traversal and correcting typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327898
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Martin Storsjo [Mon, 19 Mar 2018 20:06:50 +0000 (20:06 +0000)]
[ARM, AArch64] Check the no-stack-arg-probe attribute for dynamic stack probes
This extends the use of this attribute on ARM and AArch64 from
SVN r325900 (where it was only checked for fixed stack
allocations on ARM/AArch64, but for all stack allocations on X86).
This also adds a testcase for the existing use of disabling the
fixed stack probe with the attribute on ARM and AArch64.
Differential Revision: https://reviews.llvm.org/D44291
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327897
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Alina Sbirlea [Mon, 19 Mar 2018 20:05:01 +0000 (20:05 +0000)]
Add cast to Type*, fix failure from r327894.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327896
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Zachary Turner [Mon, 19 Mar 2018 19:53:51 +0000 (19:53 +0000)]
Support embedding natvis files in PDBs.
Natvis is a debug language supported by Visual Studio for
specifying custom visualizers. The /NATVIS option is an
undocumented link.exe flag which will take a .natvis file
and "inject" it into the PDB. This way, you can ship the
debug visualizers for a program along with the PDB, which
is very useful for postmortem debugging.
This is implemented by adding a new "named stream" to the
PDB with a special name of /src/files/<natvis file name>
and simply copying the contents of the xml into this file.
Additionally, we need to emit a single stream named
/src/headerblock which contains a hash table of embedded
files to records describing them.
This patch adds this functionality, including the /NATVIS
option to lld-link.
Differential Revision: https://reviews.llvm.org/D44328
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327895
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Alina Sbirlea [Mon, 19 Mar 2018 19:49:28 +0000 (19:49 +0000)]
Make ConstantDataArray::get constructor templated. Will support signed integers.
Summary: Make ConstantDataArray::get() constructors a single templated one.
Reviewers: timshen, rsmith
Subscribers: sanjoy, llvm-commits, jlebar
Differential Revision: https://reviews.llvm.org/D44337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327894
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Sanjay Patel [Mon, 19 Mar 2018 19:26:22 +0000 (19:26 +0000)]
[AMDGPU] change test to avoid NaN math
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327891
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Sanjay Patel [Mon, 19 Mar 2018 19:23:53 +0000 (19:23 +0000)]
[AMDGPU] adjust tests to be nan-free
As suggested in D44521 - bitcast to integer for the math,
so we preserve the intent of these tests when NaN math
gets folded away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327890
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Lei Huang [Mon, 19 Mar 2018 19:22:52 +0000 (19:22 +0000)]
[Power9]Legalize and emit code for quad-precision copySign/abs/nabs/neg/sqrt
Legalize and emit code for quad-precision floating point operations:
* xscpsgnqp
* xsabsqp
* xsnabsqp
* xsnegqp
* xssqrtqp
Differential Revision: https://reviews.llvm.org/D44530
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327889
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Andrea Di Biagio [Mon, 19 Mar 2018 19:14:06 +0000 (19:14 +0000)]
[llvm-mca] Remove unused method from ResourceManager. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327888
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Andrea Di Biagio [Mon, 19 Mar 2018 19:09:38 +0000 (19:09 +0000)]
[llvm-mca] Simplify code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327886
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Krzysztof Parzyszek [Mon, 19 Mar 2018 19:03:18 +0000 (19:03 +0000)]
[Hexagon] Add a few more lit tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327884
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Craig Topper [Mon, 19 Mar 2018 19:00:37 +0000 (19:00 +0000)]
[X86] Add JMP16r and JMP32r to Sandybridge scheduler model.
Fixes PR36010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327883
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Craig Topper [Mon, 19 Mar 2018 19:00:35 +0000 (19:00 +0000)]
[X86] Remove OUT32rr/OUT8rr/OUT32ri/OUT8ri from Sandybridge scheduler model.
PR35590 was already filed for this information being wrong. It's probably better to default to WriteSystem behavior instead of using something completely wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327882
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Craig Topper [Mon, 19 Mar 2018 19:00:32 +0000 (19:00 +0000)]
[X86] Add JCXZ/JECXZ to Sandybridge/Haswell/Broadwell/Skylake scheduler models.
JRCXZ was already present, but not the others.
We never codegen this instruction so this doesn't affect much just trying to get them all into a single generated scheduler class in the output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327881
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Craig Topper [Mon, 19 Mar 2018 19:00:29 +0000 (19:00 +0000)]
[X86] Correct regular expression in Zen scheduler model that was excluding JECXZ instruction.
The regex was looking for JECXZ_32 or JECXZ_64, but their is just one instruction called JECXZ. They used to exist as separate instructions, but were merged over 3 years ago.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327880
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Craig Topper [Mon, 19 Mar 2018 19:00:26 +0000 (19:00 +0000)]
[X86] Correct the SchedRW on (V)MOVAPSrr_REV and similar to match their non _REV counterparts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327879
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Lei Huang [Mon, 19 Mar 2018 18:52:20 +0000 (18:52 +0000)]
[PowerPC][Power9]Legalize and emit code for quad-precision add/div/mul/sub
Legalize and emit code for quad-precision floating point operations:
* xsaddqp
* xssubqp
* xsdivqp
* xsmulqp
Differential Revision: https://reviews.llvm.org/D44506
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327878
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Nemanja Ivanovic [Mon, 19 Mar 2018 18:50:02 +0000 (18:50 +0000)]
[PowerPC] Make AddrSpaceCast noop
PowerPC targets do not use address spaces. As a result, we can get selection
failures with address space casts. This patch makes those casts noops.
Patch by Valentin Churavy.
Differential revision: https://reviews.llvm.org/D43781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327877
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Craig Topper [Mon, 19 Mar 2018 17:58:41 +0000 (17:58 +0000)]
[X86] Add the rest of the TEST with immediate instructions to the scheduler models to match their 8-bit counterpart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327874
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Craig Topper [Mon, 19 Mar 2018 17:46:59 +0000 (17:46 +0000)]
[X86] Add MOV16ri*/MOV32ri*/MOV64ri* to scheduler models to match MOV8ri. Correct SchedRW and itinerary for MOV32ri64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327872
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Craig Topper [Mon, 19 Mar 2018 17:31:41 +0000 (17:31 +0000)]
[X86] Remove sse41 specific code from lowering v16i8 multiply
With the SRAs removed from the SSE2 code in D44267, then there doesn't appear to be any advantage to the sse41 code. The punpcklbw instruction and pmovsx seem to have the same latency and throughput on most CPUs. And the SSE41 code requires moving the upper 64-bits into the lower 64-bit before the sign extend can be done. The unpckhbw in sse2 code can do better than that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327869
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Craig Topper [Mon, 19 Mar 2018 16:38:33 +0000 (16:38 +0000)]
[X86] Make the multiply and divide itineraries more consistent.
Sometimes we used the same itinerary for MEM and REG forms, but that seems inconsistent with our usual usage.
We also used the MUL8 itinerary for MULX32/64 which was also weird.
The test changes are because we were using IIC_IMUL32_RR and IIC_IMUL64_RR instead of IIC_IMUL32_REG/IIC_IMUL64_REG for the 32 and 64 bit multiplies that produce double width result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327866
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Zaara Syeda [Mon, 19 Mar 2018 16:19:44 +0000 (16:19 +0000)]
Revert [MachineLICM] This reverts commit rL327856
Failing build bots. Revert the commit now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327864
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Matt Davis [Mon, 19 Mar 2018 16:06:40 +0000 (16:06 +0000)]
[CodeGen] Avoid handling DBG_VALUE in the LivePhysRegs (addUses,removeDefs,stepForward)
Summary:
This patch prevents DBG_VALUE instructions from influencing
LivePhysRegs::stepBackwards and stepForwards. In at least one case,
specifically branch folding, the stepBackwards logic was having an
influence on code generation. The result was that certain code
compiled with '-g -O2' would differ from that compiled with '-O2'
alone. It seems that the original logic, accounting for DBG_VALUE,
was influencing the placement of an IMPLICIT_DEF which had a later
impact on how blocks were processed in branch folding.
Reviewers: kparzysz, MatzeB
Reviewed By: kparzysz
Subscribers: bjope, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D43850
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327862
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Erik Pilkington [Mon, 19 Mar 2018 15:18:23 +0000 (15:18 +0000)]
[demangler] Recopy the demangler from libcxxabi.
Some significant work has gone into libcxxabi's copy of this file:
- Uses an AST to represent mangled names.
- Support/bugfixes for many C++ features.
- Uses LLVM coding style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327859
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Sanjay Patel [Mon, 19 Mar 2018 15:14:30 +0000 (15:14 +0000)]
[InstCombine] canonicalize fcmp+select to fabs
This is complicated by -0.0 and nan. This is based on the DAG patterns
as shown in D44091. I'm hoping that we can just remove those DAG folds
and always rely on IR canonicalization to handle the matching to fabs.
We would still need to delete the broken code from DAGCombiner to fix
PR36600:
https://bugs.llvm.org/show_bug.cgi?id=36600
Differential Revision: https://reviews.llvm.org/D44550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327858
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Zaara Syeda [Mon, 19 Mar 2018 14:52:25 +0000 (14:52 +0000)]
[MachineLICM] Add functions to MachineLICM to hoist invariant stores
This patch adds functions to allow MachineLICM to hoist invariant stores.
Currently, MachineLICM does not hoist any store instructions, however
when storing the same value to a constant spot on the stack, the store
instruction should be considered invariant and be hoisted. The function
isInvariantStore iterates each operand of the store instruction and checks
that each register operand satisfies isCallerPreservedPhysReg. The store
may be fed by a copy, which is hoisted by isCopyFeedingInvariantStore.
This patch also adds the PowerPC changes needed to consider the stack
register as caller preserved.
Differential Revision: https://reviews.llvm.org/D40196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327856
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Simon Pilgrim [Mon, 19 Mar 2018 14:46:07 +0000 (14:46 +0000)]
[X86] Generalize schedule classes to support multiple stages
Currently the WriteResPair style multi-classes take a single pipeline stage and latency, this patch generalizes this to make it easier to create complex schedules with ResourceCycles and NumMicroOps be overriden from their defaults.
This has already been done for the Jaguar scheduler to remove a number of custom schedule classes and adding it to the other x86 targets will make it much tidier as we add additional classes in the future to try and replace so many custom cases.
I've converted some instructions but a lot of the models need a bit of cleanup after the patch has been committed - memory latencies not being consistent, the class not actually being used when we could remove some/all customs, etc. I'd prefer to keep this as NFC as possible so later patches can be smaller and target specific.
Differential Revision: https://reviews.llvm.org/D44612
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327855
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Sanjay Patel [Mon, 19 Mar 2018 14:26:50 +0000 (14:26 +0000)]
[x86] put nops into the WriteNop class and customize for Jaguar
1. Given that we already have a classification bucket with 'nop' in the name,
that's where 'nop' belongs. Right now, it's only used for prefix bytes and 'pause'.
2. Make the latency of this class '1' for Jaguar to tell the scheduler (and presumably
llvm-mca) how to model the resource requirements better even though a nop has no
dependencies.
Differential Revision: https://reviews.llvm.org/D44608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327853
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Ilya Biryukov [Mon, 19 Mar 2018 14:19:58 +0000 (14:19 +0000)]
Changed createTemporaryFile without FD to actually create a file.
Summary:
This commit changes semantics of createUniqueFile and
createTemporaryFile variants that do not return file descriptors.
Previously they only checked if files exist, therefore being subject
to race conditions. Now they will create an empty file to avoid them.
Functions that do not create a file are now called
getPotentiallyUniqueTempFileName and getPotentiallyUniqueFileName.
Reviewers: klimek, bkramer, krasimir, JDevlieghere, espindola
Reviewed By: klimek
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36827
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327851
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Nicolai Haehnle [Mon, 19 Mar 2018 14:14:28 +0000 (14:14 +0000)]
TableGen: Explicitly forbid self-references to field members
Summary:
Otherwise, patterns like in the test case produce cryptic error
messages about fields being resolved incompletely.
Change-Id: I713c0191f00fe140ad698675803ab1f8823dc5bd
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44476
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327850
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Nicolai Haehnle [Mon, 19 Mar 2018 14:14:20 +0000 (14:14 +0000)]
TableGen: Check the dynamic type of !cast<Rec>(string)
Summary:
The docs already claim that this happens, but so far it hasn't. As a
consequence, existing TableGen files get this wrong a lot, but luckily
the fixes are all reasonably straightforward.
To make this work with all the existing forms of self-references (since
the true type of a record is only built up over time), the lookup of
self-references in !cast is delayed until the final resolving step.
Change-Id: If5923a72a252ba2fbc81a889d59775df0ef31164
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D44475
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327849
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Nicolai Haehnle [Mon, 19 Mar 2018 14:14:10 +0000 (14:14 +0000)]
TableGen: Explicitly test some cases of self-references and !cast errors
Summary:
These are cases of self-references that exist today in practice. Let's
add tests for them to avoid regressions.
The self-references in PPCInstrInfo.td can be expressed in a simpler
way. Allowing this type of self-reference while at the same time
consistently doing late-resolve even for self-references is problematic
because there are references to fields that aren't in any class. Since
there's no need for this type of self-reference anyway, let's just
remove it.
Change-Id: I914e0b3e1ae7adae33855fac409b536879bc3f62
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: nemanjai, wdng, kbarton, llvm-commits
Differential Revision: https://reviews.llvm.org/D44474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327848
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Nicolai Haehnle [Mon, 19 Mar 2018 14:14:04 +0000 (14:14 +0000)]
TableGen: Only fold when some operand made resolve progress
Summary:
Make sure that we always fold immediately, so there's no point in
attempting to re-fold when nothing changes.
Change-Id: I069e1989455b6f2ca8606152f6adc1a5e817f1c8
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327847
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Nicolai Haehnle [Mon, 19 Mar 2018 14:13:59 +0000 (14:13 +0000)]
TableGen: Remove OpInit::Fold
Summary:
Virtual dispatch is not actually used anywhere.
Change-Id: I9829c5c59920ea27fb9bc17f1442156a3bb09a65
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327846
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Nicolai Haehnle [Mon, 19 Mar 2018 14:13:54 +0000 (14:13 +0000)]
TableGen: Move GenStrConcat to a helper function in BinOpInit
Summary:
Make it accessible for more users.
Change-Id: Ib05f09ba14e7942ced5d2f24b205efa285e40cd5
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327845
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Nicolai Haehnle [Mon, 19 Mar 2018 14:13:37 +0000 (14:13 +0000)]
TableGen: Remove the cast-from-string-to-variable-reference feature
Summary:
Cast-from-string for records isn't going away, but cast-from-string for
variables is a pretty dodgy feature to have, especially when referencing
template arguments. It's doubtful that this ever worked in a reliable
way, and nobody seems to be using it, so let's get rid of it and get
some related cleanups.
Change-Id: I395ac8a43fef4cf98e611f2f552300d21e99b66a
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327844
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Matt Arsenault [Mon, 19 Mar 2018 14:07:23 +0000 (14:07 +0000)]
AMDGPU/GlobalISel: RegBankSelect for basic int ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327843
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Matt Arsenault [Mon, 19 Mar 2018 14:07:15 +0000 (14:07 +0000)]
AMDGPU: Don't leave dead illegal VGPR->SGPR copies
Normally DCE kills these, but at -O0 these get left behind
leaving suspicious looking illegal copies.
Replace with IMPLICIT_DEF to avoid iterator issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327842
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Karl-Johan Karlsson [Mon, 19 Mar 2018 13:48:40 +0000 (13:48 +0000)]
[NFC] Fix minor typos in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327841
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Clement Courbet [Mon, 19 Mar 2018 13:37:04 +0000 (13:37 +0000)]
[MergeICmps] Re-land 324317 "Enable the MergeICmps Pass by default."
Now that PR36557 is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327840
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Sjoerd Meijer [Mon, 19 Mar 2018 13:35:25 +0000 (13:35 +0000)]
[ARM] Support for v4f16 and v8f16 vectors
This is the groundwork for adding the Armv8.2-A FP16 vector intrinsics, which
uses v4f16 and v8f16 vector operands and return values. All the moving parts
are tested with two intrinsics, a 1-operand v8f16 and a 2-operand v4f16
intrinsic. In a follow-up patch the rest of the intrinsics and tests will be
added.
Differential Revision: https://reviews.llvm.org/D44538
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327839
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Xin Tong [Mon, 19 Mar 2018 13:35:23 +0000 (13:35 +0000)]
Stylish change. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327838
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Andrea Di Biagio [Mon, 19 Mar 2018 13:23:07 +0000 (13:23 +0000)]
[llvm-mca] Add pipeline stall events.
This patch introduces a new class named HWStallEvent (see HWEventListener.h),
and updates the event listener interface. A HWStallEvent represents a pipeline
stall caused by the lack of hardware resources. Similarly to HWInstructionEvent,
the event type is an unsigned, and the exact meaning depends on the subtarget.
At the moment, HWStallEvent supports a few generic dispatch events.
The main goals of this patch is to remove the logic that counts dispatch stalls
from the DispatchUnit to the BackendStatistics view.
Previously, DispatchUnit was responsible for counting and classifying dispatch
stall events. With this patch, we delegate the task of counting and classifying
stall events to the listeners (i.e. in our case, it is view
"BackendStatistics"). So, the DispatchUnit doesn't have to do extra
(unnecessary) bookkeeping.
This patch also helps futher simplifying the Backend interface. Now class
BackendStatistics no longer has to query the Backend interface to obtain the
number of dispatch stalls. As a consequence, we can get rid of all the
'getNumXXX()' methods from class Backend.
The long term goal is to remove all the remaining dependencies between the
Backend and the BackendStatistics interface.
Differential Revision: https://reviews.llvm.org/D44621
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327837
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Hans Wennborg [Mon, 19 Mar 2018 13:05:37 +0000 (13:05 +0000)]
build_llvm_package.bat: Drop LLDB from the package.
I don't think anyone ever got this to work, what with getting exactly
the right Python dependency and so on. Removing it simplifies the
script, removes a number of hairy dependencies, and cuts ~30 MB off the
installer size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327835
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Jonas Paulsson [Mon, 19 Mar 2018 13:05:22 +0000 (13:05 +0000)]
[SystemZ] Bugfix of CC liveness in emitMemMemWrapper (CLC).
If DoneMBB becomes empty it must have CC added to its live-in list, since it
will fall-through into EndMBB. This happens when the CLC loop does the
complete range.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327834
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Hans Wennborg [Mon, 19 Mar 2018 12:55:58 +0000 (12:55 +0000)]
HexagonISelLowering.cpp: fix 'enum in bool context' warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327832
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Alex Bradbury [Mon, 19 Mar 2018 11:54:28 +0000 (11:54 +0000)]
[RISCV] Peephole optimisation for load/store of global values or constant addresses
(load (add base, off), 0) -> (load base, off)
(store val, (add base, off)) -> (store val, base, off)
This is similar to an equivalent peephole optimisation in PPCISelDAGToDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327831
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Alexander Potapenko [Mon, 19 Mar 2018 10:08:04 +0000 (10:08 +0000)]
[MSan] fix the types of RegSaveAreaPtrPtr and OverflowArgAreaPtrPtr
Despite their names, RegSaveAreaPtrPtr and OverflowArgAreaPtrPtr
used to be i8* instead of i8**.
This is important, because these pointers are dereferenced twice
(first in CreateLoad(), then in getShadowOriginPtr()), but for some
reason MSan allowed this - most certainly because it was possible
to optimize getShadowOriginPtr() away at compile time.
Differential revision: https://reviews.llvm.org/D44520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327830
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Alexander Potapenko [Mon, 19 Mar 2018 10:03:47 +0000 (10:03 +0000)]
[MSan] Don't create zero offsets in getShadowPtrForArgument(). NFC
For MSan instrumentation with MS.ParamTLS and MS.ParamOriginTLS being
TLS variables, the CreateAdd() with ArgOffset==0 is a no-op, because
the compiler is able to fold the addition of 0.
But for KMSAN, which receives ParamTLS and ParamOriginTLS from a call
to the runtime library, this introduces a stray instruction which
complicates reading/testing the IR.
Differential revision: https://reviews.llvm.org/D44514
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327829
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Alexander Potapenko [Mon, 19 Mar 2018 09:59:44 +0000 (09:59 +0000)]
[MSan] Introduce insertWarningFn(). NFC
This is a step towards the upcoming KMSAN implementation patch.
KMSAN is going to use a different warning function,
__msan_warning_32(uptr origin), so we'd better create the warning
calls in one place.
Differential Revision: https://reviews.llvm.org/D44513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327828
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Mikhail Maltsev [Mon, 19 Mar 2018 09:48:58 +0000 (09:48 +0000)]
[ARM] Fix warnings about missing parentheses in ARMAsmParser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327827
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Serguei Katkov [Mon, 19 Mar 2018 08:32:09 +0000 (08:32 +0000)]
[SCEV] Factor out isKnownViaInduction. NFC.
This just extracts the isKnownViaInduction from isKnownPredicate.
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327824
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Serguei Katkov [Mon, 19 Mar 2018 06:35:30 +0000 (06:35 +0000)]
[SCEV] Re-land: Fix isKnownPredicate
This is re-land of https://reviews.llvm.org/rL327362 with a fix
and regression test.
The crash was due to it is possible that for found MDL loop,
LHS or RHS may contain an invariant unknown SCEV which
does not dominate the MDL. Please see regression
test for an example.
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44553
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327822
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Craig Topper [Mon, 19 Mar 2018 04:21:42 +0000 (04:21 +0000)]
[X86] Merge XADD8rr regular expression with XADD16rr/XADD32rr/XADD64rr in a couple scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327821
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Craig Topper [Mon, 19 Mar 2018 04:21:40 +0000 (04:21 +0000)]
[X86] Add ADD16i16/ADD32i32/ADD64i32 and similar to the scheduler models to match ADD8i8.
Also move ADC8i8 and SBB8i8 in the Sandy Bridge model to the same class as ADC8ri and SBB8ri. That seems more accurate since its the 8i8 is just the register forced to AL instead of coming from modrm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327820
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Craig Topper [Mon, 19 Mar 2018 02:07:32 +0000 (02:07 +0000)]
[X6] Remove two unused InstrItinClass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327819
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Craig Topper [Mon, 19 Mar 2018 00:56:12 +0000 (00:56 +0000)]
[X86] Use IIC_CMOV64_RR/RM on 64-bit cmov instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327817
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Craig Topper [Mon, 19 Mar 2018 00:56:11 +0000 (00:56 +0000)]
[X86] Merge 32 and 64-bit RORX/SHLX/SARX/SHRX into single regular expressions in scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327816
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Craig Topper [Mon, 19 Mar 2018 00:56:09 +0000 (00:56 +0000)]
[X86] Merge 8-bit instructions into instregex with 16/32/64 instructions in the scheduler models as much as possible. NFCI
This reduces the total number of generated scheduler classes from 5404 to 5316.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327815
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Dylan McKay [Mon, 19 Mar 2018 00:55:50 +0000 (00:55 +0000)]
[AVR] Lower i128 divisions to runtime library calls
This patch adds i128 division support by instruction LLVM to lower
128-bit divisions to the __udivmodti4 and __divmodti4 rtlib functions.
This also adds test for 64-bit division and 128-bit division.
Patch by Peter Nimmervoll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327814
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Craig Topper [Sun, 18 Mar 2018 22:16:54 +0000 (22:16 +0000)]
[Mips] Remove duplicate lines from MipsScheduleP5600.td and enable FullInstRWOverlapCheck.
This fixes the errors found by the new check added in r327808.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327813
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Craig Topper [Sun, 18 Mar 2018 22:16:53 +0000 (22:16 +0000)]
[AArch64] Fix a few InstRWs in the A53 scheduler model and enable FullInstRWOverlapCheck.
This fixes the errors found by the new check added in r327808.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327812
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Craig Topper [Sun, 18 Mar 2018 21:28:11 +0000 (21:28 +0000)]
[SelectionDAG] Don't default the SelectionDAG* parameter to SDValue::dump to nullptr. Use two different signatures instead.
This matches what we do in SDNode.
This should allow SDValue::dump to be used in the debugger without getting an error if you don't pass an argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327811
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Craig Topper [Sun, 18 Mar 2018 19:56:15 +0000 (19:56 +0000)]
[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.
This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check.
So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag.
A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327808
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Simon Pilgrim [Sun, 18 Mar 2018 19:54:42 +0000 (19:54 +0000)]
[X86][Btver2] Fix crc32 schedule costs
The default is currently FAdd for some reason
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327807
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Simon Pilgrim [Sun, 18 Mar 2018 18:55:34 +0000 (18:55 +0000)]
[X86][Btver2] Add crc32 resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327805
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Simon Pilgrim [Sun, 18 Mar 2018 18:45:57 +0000 (18:45 +0000)]
[X86][Btver2] FADD/FHADD ymm instructions are double pumped on the JFPA functional pipe
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327804
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Simon Pilgrim [Sun, 18 Mar 2018 17:10:12 +0000 (17:10 +0000)]
[X86][Btver2] Float bitwise ymm instructions are double pumped on the JFPX (JFPA/JFPM) functional pipes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327803
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Simon Pilgrim [Sun, 18 Mar 2018 15:59:51 +0000 (15:59 +0000)]
[X86][Btver2] F16C instructions are performed on the JSTC functional pipe
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327801
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Anastasis Grammenos [Sun, 18 Mar 2018 15:59:19 +0000 (15:59 +0000)]
[LICM] Salvage DI from dying Instructions
LICM deletes trivially dead instructions which it won't attempt to sink.
Attempt to salvage debug values which reference these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327800
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Roman Lebedev [Sun, 18 Mar 2018 15:53:02 +0000 (15:53 +0000)]
[InstCombine] peek through unsigned FP casts for zero-equality compares (PR36682)
Summary:
This pattern came up in PR36682 / D44390
https://bugs.llvm.org/show_bug.cgi?id=36682
https://reviews.llvm.org/D44390
https://godbolt.org/g/oKvT5H
See also D44416
Reviewers: spatel, majnemer, efriedma, arsenm
Reviewed By: spatel
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327799
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