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Philippe Mathieu-Daudé [Mon, 7 Feb 2022 08:27:48 +0000 (09:27 +0100)]
hw/tpm: Clean includes
"tpm_ppi.h" only requires to include "exec/memory.h" to get
the MemoryRegion declaration.
tpm_ppi.c requires "hw/qdev-core.h" to use the DEVICE() macro,
tpm_crb.c is the only source file requiring "exec/address-spaces.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20220207082756.82600-2-f4bug@amsat.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Mon, 24 Jan 2022 10:20:01 +0000 (11:20 +0100)]
scripts: Remove the old switch-timer-api script
This script has been useful for the timer API rewrite in 2013, but
it is of no use anymore today. Let's remove it now.
Message-Id: <
20220124102001.35930-1-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Laurent Vivier [Thu, 3 Feb 2022 14:15:37 +0000 (15:15 +0100)]
tests/qtest: failover: migration abort test with failover off
Test abort during active migration when failover is disabled from QEMU
or from guest side.
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <
20220203141537.972317-8-lvivier@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Laurent Vivier [Thu, 3 Feb 2022 14:15:36 +0000 (15:15 +0100)]
tests/qtest: failover: test migration if the guest doesn't support failover
The primary device is not plugged and the migration is done only with
the standby device
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <
20220203141537.972317-7-lvivier@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Laurent Vivier [Thu, 3 Feb 2022 14:15:35 +0000 (15:15 +0100)]
tests/qtest: failover: check migration with failover off
If failover is off, the primary device is not plugged and
the migration is done only with the standby device.
On destination, the primary device must not be plugged.
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <
20220203141537.972317-6-lvivier@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Laurent Vivier [Thu, 3 Feb 2022 14:15:34 +0000 (15:15 +0100)]
tests/qtest: failover: check missing guest feature
If QEMU provides the VIRTIO_NET_F_STANDBY feature but the guest doesn't
the primary device must be kept hidden
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <
20220203141537.972317-5-lvivier@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Laurent Vivier [Thu, 3 Feb 2022 14:15:33 +0000 (15:15 +0100)]
tests/qtest: failover: check the feature is correctly provided
Check QEMU provides the VIRTIO_NET_F_STANDBY if failover is on,
and doesn't if failover is off
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <
20220203141537.972317-4-lvivier@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Laurent Vivier [Thu, 3 Feb 2022 14:15:32 +0000 (15:15 +0100)]
tests/qtest: failover: use a macro for check_one_card()
This allows g_assert() to correctly report the line number of the error
in the test case.
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <
20220203141537.972317-3-lvivier@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Laurent Vivier [Thu, 3 Feb 2022 14:15:31 +0000 (15:15 +0100)]
tests/qtest: failover: clean up pathname of tests
clearly indentify parameters, hotplug and migration tests
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <
20220203141537.972317-2-lvivier@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Fri, 21 Jan 2022 12:06:35 +0000 (13:06 +0100)]
tests/qtest/ide-test: Remove bad retry_isa test
The retry_isa test is not doing what it was intended for: The
test_retry_flush() function ignores the machine parameter completely
and thus this test does not get run with the "isapc" machine.
Moreover, in the course of time, the test_retry_flush() has been
changed to depend on PCI-related functions, so this also cannot
be fixed by simply using the machine parameter now. The correct
fix would be to switch the whole test to libqos, but until someone
has time to do this, let's simply drop the retry_isa test for now.
Message-Id: <
20220121120635.220644-1-thuth@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Eric Auger [Thu, 10 Feb 2022 14:52:50 +0000 (15:52 +0100)]
tests/qtest/vhost-user-test.c: Use vhostforce=on
-netdev vhost-user,vhostforce is deprecated and vhostforce=on
should be used instead.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <
20220210145254.157790-2-eric.auger@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Michael S. Tsirkin [Sun, 6 Feb 2022 09:35:57 +0000 (04:35 -0500)]
erst: drop cast to long long
The way to print uint64_t is with PRIx64, not with
a cast to long long.
Message-Id: <
20220206093547.
1282513-1-mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Dr. David Alan Gilbert [Tue, 15 Feb 2022 16:25:32 +0000 (16:25 +0000)]
tests/x86: Use 'pc' machine type for hotplug tests
Hotplug tests need a bridge setting up on q35, for now
keep them on 'pc'.
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <
20220215162537.605030-3-dgilbert@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Dr. David Alan Gilbert [Tue, 15 Feb 2022 16:25:31 +0000 (16:25 +0000)]
tests/x86: Use 'pc' machine type for old hardware tests
For tests that rely on old hardware, e.g. floppies or IDE drives,
explicitly select the 'pc' machine type.
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <
20220215162537.605030-2-dgilbert@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Peter Maydell [Sun, 20 Feb 2022 15:05:41 +0000 (15:05 +0000)]
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-
20220218' into staging
ppc-7.0 queue
* target/ppc: SPR registration cleanups (Fabiano)
* ppc: nested KVM HV for spapr virtual hypervisor (Nicholas)
* spapr: nvdimm: Introduce spapr-nvdimm device (Shivaprasad)
# gpg: Signature made Fri 18 Feb 2022 07:59:29 GMT
# gpg: using RSA key
A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* remotes/legoater/tags/pull-ppc-
20220218: (39 commits)
target/ppc: Move common SPR functions out of cpu_init
target/ppc: cpu_init: Move check_pow and QOM macros to a header
target/ppc: cpu_init: Move SPR registration macros to a header
target/ppc: cpu_init: Expose some SPR registration helpers
target/ppc: Rename spr_tcg.h to spr_common.h
target/ppc: cpu_init: Remove register_usprg3_sprs
target/ppc: cpu_init: Rename register_ne_601_sprs
target/ppc: cpu_init: Reuse init_proc_745 for the 755
target/ppc: cpu_init: Reuse init_proc_604 for the 604e
target/ppc: cpu_init: Reuse init_proc_603 for the e300
target/ppc: cpu_init: Move 604e SPR registration into a function
target/ppc: cpu_init: Move e300 SPR registration into a function
target/ppc: cpu_init: Move 755 L2 cache SPRs into a function
target/ppc: cpu_init: Deduplicate 7xx SPR registration
target/ppc: cpu_init: Deduplicate 745/755 SPR registration
target/ppc: cpu_init: Deduplicate 604 SPR registration
target/ppc: cpu_init: Deduplicate 603 SPR registration
target/ppc: cpu_init: Deduplicate 440 SPR registration
target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx
target/ppc: cpu_init: Decouple G2 SPR registration from 755
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Sat, 19 Feb 2022 15:24:12 +0000 (15:24 +0000)]
Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-
20220217b' into staging
V3: virtiofs pull 2022-02-17
Security label improvements from Vivek
- includes a fix for building against new kernel headers
[V3: checkpatch style fixes]
[V2: Fix building on old Linux]
Blocking flock disable from Sebastian
SYNCFS support from Greg
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
# gpg: Signature made Thu 17 Feb 2022 17:24:25 GMT
# gpg: using RSA key
45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7
# gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" [full]
# Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7
* remotes/dgilbert-gitlab/tags/pull-virtiofs-
20220217b:
virtiofsd: Add basic support for FUSE_SYNCFS request
virtiofsd: Add an option to enable/disable security label
virtiofsd: Create new file using O_TMPFILE and set security context
virtiofsd: Create new file with security context
virtiofsd: Add helpers to work with /proc/self/task/tid/attr/fscreate
virtiofsd: Move core file creation code in separate function
virtiofsd, fuse_lowlevel.c: Add capability to parse security context
virtiofsd: Extend size of fuse_conn_info->capable and ->want fields
virtiofsd: Parse extended "struct fuse_init_in"
linux-headers: Update headers to v5.17-rc1
virtiofsd: Fix breakage due to fuse_init_in size change
virtiofsd: Do not support blocking flock
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Sat, 19 Feb 2022 12:59:38 +0000 (12:59 +0000)]
Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-
20220217' into staging
9pfs: fixes and cleanup
* Fifth patch fixes a 9pfs server crash that happened on some systems due
to incorrect (system dependant) handling of struct dirent size.
* Tests: Second patch fixes a test error that happened on some systems due
mkdir() being called twice for creating the test directory for the 9p
'local' tests.
* Tests: Third patch fixes a memory leak.
* Tests: The remaining two patches are code cleanup.
# gpg: Signature made Thu 17 Feb 2022 16:19:25 GMT
# gpg: using RSA key
96D8D110CF7AF8084F88590134C2B58765A47395
# gpg: issuer "qemu_oss@crudebyte.com"
# gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: ECAB 1A45 4014 1413 BA38 4926 30DB 47C3 A012 D5F4
# Subkey fingerprint: 96D8 D110 CF7A F808 4F88 5901 34C2 B587 65A4 7395
* remotes/cschoenebeck/tags/pull-9p-
20220217:
9pfs: Fix segfault in do_readdir_many caused by struct dirent overread
tests/9pfs: Use g_autofree and g_autoptr where possible
tests/9pfs: Fix leak of local_test_path
tests/9pfs: fix mkdir() being called twice
tests/9pfs: use g_autofree where possible
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: Move common SPR functions out of cpu_init
Let's leave cpu_init with just generic CPU initialization and
QOM-related functions.
The rest of the SPR registration functions will be moved in the
following patches along with the code that uses them. These are only
the commonly used ones.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-28-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Move check_pow and QOM macros to a header
These will need to be accessed from other files once we move the CPUs
code to separate files.
The check_pow_hid0 and check_pow_hid0_74xx are too specific to be
moved to a header so I'll deal with them later when splitting this
code between the multiple CPU families.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-27-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Move SPR registration macros to a header
Put the SPR registration macros in a header that is accessible outside
of cpu_init.c. The following patches will move CPU-specific code to
separate files and will need to access it.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-26-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Expose some SPR registration helpers
The following patches will move CPU-specific code into separate files,
so expose the most used SPR registration functions:
register_sdr1_sprs | 22 callers
register_low_BATs | 20 callers
register_non_embedded_sprs | 19 callers
register_high_BATs | 10 callers
register_thrm_sprs | 8 callers
register_usprgh_sprs | 6 callers
register_6xx_7xx_soft_tlb | only 3 callers, but it helps to
keep the soft TLB code consistent.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-25-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: Rename spr_tcg.h to spr_common.h
Initial intent for the spr_tcg header was to expose the spr_read|write
callbacks that are only used by TCG code. However, although these
routines are TCG-specific, the KVM code needs access to env->sprs
which creation is currently coupled to the callback registration.
We are probably not going to decouple SPR creation and TCG callback
registration any time soon, so let's rename the header to spr_common
to accomodate the register_*_sprs functions that will be moved out of
cpu_init.c in the following patches.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-24-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Remove register_usprg3_sprs
This function registers just one SPR and has only two callers, so open
code it.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-23-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Rename register_ne_601_sprs
The important part of this function is that it applies to non-embedded
CPUs, not that it also applies to the 601. We removed support for the
601 anyway, so rename this function.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-22-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Reuse init_proc_745 for the 755
The init_proc_755 function is identical to the 745 one except for the
755-specific registers. I think it is worth it to make them share
code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-21-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Reuse init_proc_604 for the 604e
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-20-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Reuse init_proc_603 for the e300
init_proc_603 is defined after init_proc_e300, so I had to move some
code around to make it work.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-19-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Move 604e SPR registration into a function
This is done to improve init_proc readability and to make subsequent
patches that touch this code a bit cleaner.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-18-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Move e300 SPR registration into a function
This is done to improve init_proc readability and to make subsequent
patches that touch this code a bit cleaner.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-17-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Move 755 L2 cache SPRs into a function
This is just to have 755-specific registers contained into a function,
intead of leaving them open-coded in init_proc_755. It makes init_proc
easier to read and keeps later patches that touch this code a bit
cleaner.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-16-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Deduplicate 7xx SPR registration
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-15-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Deduplicate 745/755 SPR registration
The 745 and 755 can share the HID registration, so move it all into
register_755_sprs, which applies for both CPUs.
Also rename that function to register_745_sprs, since the 745 is the
earliest of the two. This will help with separating 755-specific
registers in a subsequent patch.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-14-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Deduplicate 604 SPR registration
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-13-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Deduplicate 603 SPR registration
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-12-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:15 +0000 (08:34 +0100)]
target/ppc: cpu_init: Deduplicate 440 SPR registration
Move some of the 440 registers that are being repeated in the 440*
CPUs to register_440_sprs.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx
We're considering these two to be from different CPU families, so
duplicate some code to keep them separate.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-10-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: cpu_init: Decouple G2 SPR registration from 755
We're considering these two to be in different CPU families (6xx and
7xx), so keep their SPR registration separate.
The code was copied into register_G2_sprs and the common function was
renamed to apply only to the 755.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-8-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: cpu_init: Move 405 SPRs into register_405_sprs
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-7-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: cpu_init: Avoid nested SPR register functions
Make sure that every register_*_sprs function only has calls to
spr_register* to register individual SPRs. Do not allow nesting. This
makes the code easier to follow and a look at init_proc_* should
suffice to know what SPRs a CPU has.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-6-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: cpu_init: Move Timebase registration into the common function
Now that the 601 was removed, all of our CPUs have a timebase, so that
can be moved into the common function.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: cpu_init: Group registration of generic SPRs
The top level init_proc calls register_generic_sprs but also registers
some other SPRs outside of that function. Let's group everything into
a single place.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: cpu_init: Remove G2LE init code
The G2LE CPU initialization code is the same as the G2. Use the latter
for both.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: cpu_init: Remove not implemented comments
The /* XXX : not implemented */ comments all over cpu_init are
confusing and ambiguous.
Do they mean not implemented by QEMU, not implemented in a specific
access mode? Not implemented by the CPU? Do they apply to just the
register right after or to a whole block? Do they mean we have an
action to take in the future to implement these? Are they only
informative?
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20220216162426.
1885923-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Nicholas Piggin [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
spapr: implement nested-hv capability for the virtual hypervisor
This implements the Nested KVM HV hcall API for spapr under TCG.
The L2 is switched in when the H_ENTER_NESTED hcall is made, and the
L1 is switched back in returned from the hcall when a HV exception
is sent to the vhyp. Register state is copied in and out according to
the nested KVM HV hcall API specification.
The hdecr timer is started when the L2 is switched in, and it provides
the HDEC / 0x980 return to L1.
The MMU re-uses the bare metal radix 2-level page table walker by
using the get_pate method to point the MMU to the nested partition
table entry. MMU faults due to partition scope errors raise HV
exceptions and accordingly are routed back to the L1.
The MMU does not tag translations for the L1 (direct) vs L2 (nested)
guests, so the TLB is flushed on any L1<->L2 transition (hcall entry
and exit).
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: checkpatch fixes ]
Message-Id: <
20220216102545.
1808018-10-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Nicholas Piggin [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: Introduce a vhyp framework for nested HV support
Introduce virtual hypervisor methods that can support a "Nested KVM HV"
implementation using the bare metal 2-level radix MMU, and using HV
exceptions to return from H_ENTER_NESTED (rather than cause interrupts).
HV exceptions can now be raised in the TCG spapr machine when running a
nested KVM HV guest. The main ones are the lev==1 syscall, the hdecr,
hdsi and hisi, hv fu, and hv emu, and h_virt external interrupts.
HV exceptions are intercepted in the exception handler code and instead
of causing interrupts in the guest and switching the machine to HV mode,
they go to the vhyp where it may exit the H_ENTER_NESTED hcall with the
interrupt vector numer as return value as required by the hcall API.
Address translation is provided by the 2-level page table walker that is
implemented for the bare metal radix MMU. The partition scope page table
is pointed to the L1's partition scope by the get_pate vhc method.
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <
20220216102545.
1808018-9-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Nicholas Piggin [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: Add powerpc_reset_excp_state helper
This moves the logic to reset the QEMU exception state into its own
function.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <
20220216102545.
1808018-8-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Nicholas Piggin [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: add helper for books vhyp hypercall handler
The virtual hypervisor currently always intercepts and handles
hypercalls but with a future change this will not always be the case.
Add a helper for the test so the logic is abstracted from the mechanism.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <
20220216102545.
1808018-7-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Nicholas Piggin [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: make vhyp get_pate method take lpid and return success
In prepartion for implementing a full partition table option for
vhyp, update the get_pate method to take an lpid and return a
success/fail indicator.
The spapr implementation currently just asserts lpid is always 0
and always return success.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <
20220216102545.
1808018-6-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Nicholas Piggin [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: add vhyp addressing mode helper for radix MMU
The radix on vhyp MMU uses a single-level radix table walk, with the
partition scope mapping provided by the flat QEMU machine memory.
A subsequent change will use the two-level radix walk on vhyp in some
situations, so provide a helper which can abstract that logic.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <
20220216102545.
1808018-5-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Nicholas Piggin [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
ppc: allow the hdecr timer to be created/destroyed
Machines which don't emulate the HDEC facility are able to use the
timer for something else. Provide functions to start and stop the
hdecr timer.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <
20220216102545.
1808018-4-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Nicholas Piggin [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
spapr: prevent hdec timer being set up under virtual hypervisor
The spapr virtual hypervisor does not require the hdecr timer.
Remove it.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <
20220216102545.
1808018-3-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Nicholas Piggin [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
target/ppc: raise HV interrupts for partition table entry problems
Invalid or missing partition table entry exceptions should cause HV
interrupts. HDSISR is set to bad MMU config, which is consistent with
the ISA and experimentally matches what POWER9 generates.
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <
20220216102545.
1808018-2-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Shivaprasad G Bhat [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
spapr: nvdimm: Introduce spapr-nvdimm device
If the device backend is not persistent memory for the nvdimm, there is
need for explicit IO flushes on the backend to ensure persistence.
On SPAPR, the issue is addressed by adding a new hcall to request for
an explicit flush from the guest when the backend is not pmem. So, the
approach here is to convey when the hcall flush is required in a device
tree property. The guest once it knows the device backend is not pmem,
makes the hcall whenever flush is required.
To set the device tree property, a new PAPR specific device type inheriting
the nvdimm device is implemented. When the backend doesn't have pmem=on
the device tree property "ibm,hcall-flush-required" is set, and the guest
makes hcall H_SCM_FLUSH requesting for an explicit flush. The new device
has boolean property pmem-override which when "on" advertises the device
tree property even when pmem=on for the backend. The flush function
invokes the fdatasync or pmem_persist() based on the type of backend.
The vmstate structures are made part of the spapr-nvdimm device object.
The patch attempts to keep the migration compatibility between source and
destination while rejecting the incompatibles ones with failures.
Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
164396256092.109112.
17933240273840803354.stgit@ltczzess4.aus.stglabs.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Shivaprasad G Bhat [Fri, 18 Feb 2022 07:34:14 +0000 (08:34 +0100)]
spapr: nvdimm: Implement H_SCM_FLUSH hcall
The patch adds support for the SCM flush hcall for the nvdimm devices.
To be available for exploitation by guest through the next patch. The
hcall is applicable only for new SPAPR specific device class which is
also introduced in this patch.
The hcall expects the semantics such that the flush to return with
H_LONG_BUSY_ORDER_10_MSEC when the operation is expected to take longer
time along with a continue_token. The hcall to be called again by providing
the continue_token to get the status. So, all fresh requests are put into
a 'pending' list and flush worker is submitted to the thread pool. The
thread pool completion callbacks move the requests to 'completed' list,
which are cleaned up after collecting the return status for the guest
in subsequent hcall from the guest.
The semantics makes it necessary to preserve the continue_tokens and
their return status across migrations. So, the completed flush states
are forwarded to the destination and the pending ones are restarted
at the destination in post_load. The necessary nvdimm flush specific
vmstate structures are also introduced in this patch which are to be
saved in the new SPAPR specific nvdimm device to be introduced in the
following patch.
Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
164396254862.109112.
16675611182159105748.stgit@ltczzess4.aus.stglabs.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Shivaprasad G Bhat [Fri, 18 Feb 2022 07:34:13 +0000 (08:34 +0100)]
nvdimm: Add realize, unrealize callbacks to NVDIMMDevice class
A new subclass inheriting NVDIMMDevice is going to be introduced in
subsequent patches. The new subclass uses the realize and unrealize
callbacks. Add them on NVDIMMClass to appropriately call them as part
of plug-unplug.
Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
164396253158.109112.
1926755104259023743.stgit@ltczzess4.aus.stglabs.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Greg Kurz [Tue, 15 Feb 2022 18:15:29 +0000 (19:15 +0100)]
virtiofsd: Add basic support for FUSE_SYNCFS request
Honor the expected behavior of syncfs() to synchronously flush all data
and metadata to disk on linux systems.
If virtiofsd is started with '-o announce_submounts', the client is
expected to send a FUSE_SYNCFS request for each individual submount.
In this case, we just create a new file descriptor on the submount
inode with lo_inode_open(), call syncfs() on it and close it. The
intermediary file is needed because O_PATH descriptors aren't
backed by an actual file and syncfs() would fail with EBADF.
If virtiofsd is started without '-o announce_submounts' or if the
client doesn't have the FUSE_CAP_SUBMOUNTS capability, the client
only sends a single FUSE_SYNCFS request for the root inode. The
server would thus need to track submounts internally and call
syncfs() on each of them. This will be implemented later.
Note that syncfs() might suffer from a time penalty if the submounts
are being hammered by some unrelated workload on the host. The only
solution to prevent that is to avoid shared mounts.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <
20220215181529.164070-2-groug@kaod.org>
Reviewed-by: Vivek Goyal <vgoyal@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Vivek Goyal [Tue, 8 Feb 2022 20:48:13 +0000 (15:48 -0500)]
virtiofsd: Add an option to enable/disable security label
Provide an option "-o security_label/no_security_label" to enable/disable
security label functionality. By default these are turned off.
If enabled, server will indicate to client that it is capable of handling
one security label during file creation. Typically this is expected to
be a SELinux label. File server will set this label on the file. It will
try to set it atomically wherever possible. But its not possible in
all the cases.
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <
20220208204813.682906-11-vgoyal@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Vivek Goyal [Tue, 8 Feb 2022 20:48:12 +0000 (15:48 -0500)]
virtiofsd: Create new file using O_TMPFILE and set security context
If guest and host policies can't work with each other, then guest security
context (selinux label) needs to be set into an xattr. Say remap guest
security.selinux xattr to trusted.virtiofs.security.selinux.
That means setting "fscreate" is not going to help as that's ony useful
for security.selinux xattr on host.
So we need another method which is atomic. Use O_TMPFILE to create new
file, set xattr and then linkat() to proper place.
But this works only for regular files. So dir, symlinks will continue
to be non-atomic.
Also if host filesystem does not support O_TMPFILE, we fallback to
non-atomic behavior.
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <
20220208204813.682906-10-vgoyal@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Vivek Goyal [Tue, 8 Feb 2022 20:48:11 +0000 (15:48 -0500)]
virtiofsd: Create new file with security context
This patch adds support for creating new file with security context
as sent by client. It basically takes three paths.
- If no security context enabled, then it continues to create files without
security context.
- If security context is enabled and but security.selinux has not been
remapped, then it uses /proc/thread-self/attr/fscreate knob to set
security context and then create the file. This will make sure that
newly created file gets the security context as set in "fscreate" and
this is atomic w.r.t file creation.
This is useful and host and guest SELinux policies don't conflict and
can work with each other. In that case, guest security.selinux xattr
is not remapped and it is passthrough as "security.selinux" xattr
on host.
- If security context is enabled but security.selinux xattr has been
remapped to something else, then it first creates the file and then
uses setxattr() to set the remapped xattr with the security context.
This is a non-atomic operation w.r.t file creation.
This mode will be most versatile and allow host and guest to have their
own separate SELinux xattrs and have their own separate SELinux policies.
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <
20220208204813.682906-9-vgoyal@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Vivek Goyal [Tue, 8 Feb 2022 20:48:10 +0000 (15:48 -0500)]
virtiofsd: Add helpers to work with /proc/self/task/tid/attr/fscreate
Soon we will be able to create and also set security context on the file
atomically using /proc/self/task/tid/attr/fscreate knob. If this knob
is available on the system, first set the knob with the desired context
and then create the file. It will be created with the context set in
fscreate. This works basically for SELinux and its per thread.
This patch just introduces the helper functions. Subsequent patches will
make use of these helpers.
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <
20220208204813.682906-8-vgoyal@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
dgilbert: Manually merged gettid syscall number fixup from Vivek
Vivek Goyal [Tue, 8 Feb 2022 20:48:09 +0000 (15:48 -0500)]
virtiofsd: Move core file creation code in separate function
Move core file creation bits in a separate function. Soon this is going
to get more complex as file creation need to set security context also.
And there will be multiple modes of file creation in next patch.
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <
20220208204813.682906-7-vgoyal@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Vivek Goyal [Tue, 8 Feb 2022 20:48:08 +0000 (15:48 -0500)]
virtiofsd, fuse_lowlevel.c: Add capability to parse security context
Add capability to enable and parse security context as sent by client
and put into fuse_req. Filesystems now can get security context from
request and set it on files during creation.
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <
20220208204813.682906-6-vgoyal@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Vivek Goyal [Tue, 8 Feb 2022 20:48:07 +0000 (15:48 -0500)]
virtiofsd: Extend size of fuse_conn_info->capable and ->want fields
->capable keeps track of what capabilities kernel supports and ->wants keep
track of what capabilities filesytem wants.
Right now these fields are 32bit in size. But now fuse has run out of
bits and capabilities can now have bit number which are higher than 31.
That means 32 bit fields are not suffcient anymore. Increase size to 64
bit so that we can add newer capabilities and still be able to use existing
code to check and set the capabilities.
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <
20220208204813.682906-5-vgoyal@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Vivek Goyal [Tue, 8 Feb 2022 20:48:06 +0000 (15:48 -0500)]
virtiofsd: Parse extended "struct fuse_init_in"
Add some code to parse extended "struct fuse_init_in". And use a local
variable "flag" to represent 64 bit flags. This will make it easier
to add more features without having to worry about two 32bit flags (->flags
and ->flags2) in "fuse_struct_in".
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <
20220208204813.682906-4-vgoyal@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
dgilbert: Fixed up long line
Vivek Goyal [Tue, 8 Feb 2022 20:48:05 +0000 (15:48 -0500)]
linux-headers: Update headers to v5.17-rc1
Update headers to 5.17-rc1. I need latest fuse changes.
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <
20220208204813.682906-3-vgoyal@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Vivek Goyal [Tue, 8 Feb 2022 20:48:04 +0000 (15:48 -0500)]
virtiofsd: Fix breakage due to fuse_init_in size change
Kernel version 5.17 has increased the size of "struct fuse_init_in" struct.
Previously this struct was 16 bytes and now it has been extended to
64 bytes in size.
Once qemu headers are updated to latest, it will expect to receive 64 byte
size struct (for protocol version major 7 and minor > 6). But if guest is
booting older kernel (older than 5.17), then it still sends older
fuse_init_in of size 16 bytes. And do_init() fails. It is expecting
64 byte struct. And this results in mount of virtiofs failing.
Fix this by parsing 16 bytes only for now. Separate patches will be
posted which will parse rest of the bytes and enable new functionality.
Right now we don't support any of the new functionality, so we don't
lose anything by not parsing bytes beyond 16.
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <
20220208204813.682906-2-vgoyal@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Vitaly Chikunov [Wed, 16 Feb 2022 18:18:21 +0000 (21:18 +0300)]
9pfs: Fix segfault in do_readdir_many caused by struct dirent overread
`struct dirent' returned from readdir(3) could be shorter (or longer)
than `sizeof(struct dirent)', thus memcpy of sizeof length will overread
into unallocated page causing SIGSEGV. Example stack trace:
#0 0x00005555559ebeed v9fs_co_readdir_many (/usr/bin/qemu-system-x86_64 + 0x497eed)
#1 0x00005555559ec2e9 v9fs_readdir (/usr/bin/qemu-system-x86_64 + 0x4982e9)
#2 0x0000555555eb7983 coroutine_trampoline (/usr/bin/qemu-system-x86_64 + 0x963983)
#3 0x00007ffff73e0be0 n/a (n/a + 0x0)
While fixing this, provide a helper for any future `struct dirent' cloning.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/841
Cc: qemu-stable@nongnu.org
Co-authored-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Reviewed-by: Dmitry V. Levin <ldv@altlinux.org>
Signed-off-by: Vitaly Chikunov <vt@altlinux.org>
Tested-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Acked-by: Greg Kurz <groug@kaod.org>
Tested-by: Vitaly Chikunov <vt@altlinux.org>
Message-Id: <
20220216181821.
3481527-1-vt@altlinux.org>
[C.S. - Fix typo in source comment. ]
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Greg Kurz [Tue, 1 Feb 2022 15:15:08 +0000 (16:15 +0100)]
tests/9pfs: Use g_autofree and g_autoptr where possible
It is recommended to use g_autofree or g_autoptr as it reduces
the odds of introducing memory leaks in future changes.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <
20220201151508.190035-3-groug@kaod.org>
Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Greg Kurz [Tue, 1 Feb 2022 15:15:07 +0000 (16:15 +0100)]
tests/9pfs: Fix leak of local_test_path
local_test_path is allocated in virtio_9p_create_local_test_dir() to hold the path
of the temporary directory. It should be freed in virtio_9p_remove_local_test_dir()
when the temporary directory is removed. Clarify the lifecycle of local_test_path
while here.
Based-on: <
f6602123c6f7d0d593466231b04fba087817abbd.
1642879848.git.qemu_oss@crudebyte.com>
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <
20220201151508.190035-2-groug@kaod.org>
Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Christian Schoenebeck [Sat, 22 Jan 2022 19:12:16 +0000 (20:12 +0100)]
tests/9pfs: fix mkdir() being called twice
The 9p test cases use mkdtemp() to create a temporary directory for
running the 'local' 9p tests with real files/dirs. Unlike mktemp()
which only generates a unique file name, mkdtemp() also creates the
directory, therefore the subsequent mkdir() was wrong and caused
errors on some systems.
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Fixes:
136b7af2 (tests/9pfs: fix test dir for parallel tests)
Reported-by: Daniel P. Berrangé <berrange@redhat.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/832
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Greg Kurz <Greg Kurz <groug@kaod.org>
Message-Id: <
f6602123c6f7d0d593466231b04fba087817abbd.
1642879848.git.qemu_oss@crudebyte.com>
Christian Schoenebeck [Tue, 16 Nov 2021 16:40:08 +0000 (17:40 +0100)]
tests/9pfs: use g_autofree where possible
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-Id: <E1mn1fA-0005qZ-TM@lizzy.crudebyte.com>
Sebastian Hasler [Thu, 13 Jan 2022 15:32:49 +0000 (16:32 +0100)]
virtiofsd: Do not support blocking flock
With the current implementation, blocking flock can lead to
deadlock. Thus, it's better to return EOPNOTSUPP if a user attempts
to perform a blocking flock request.
Signed-off-by: Sebastian Hasler <sebastian.hasler@stuvus.uni-stuttgart.de>
Message-Id: <
20220113153249.710216-1-sebastian.hasler@stuvus.uni-stuttgart.de>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Vivek Goyal <vgoyal@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Peter Maydell [Wed, 16 Feb 2022 09:57:11 +0000 (09:57 +0000)]
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-
20220216' into staging
Fourth RISC-V PR for QEMU 7.0
* Remove old Ibex PLIC header file
* Allow writing 8 bytes with generic loader
* Fixes for RV128
* Refactor RISC-V CPU configs
* Initial support for XVentanaCondOps custom extension
* Fix for vill field in vtype
* Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
* Support for svnapot, svinval and svpbmt extensions
# gpg: Signature made Wed 16 Feb 2022 06:24:52 GMT
# gpg: using RSA key
F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-
20220216: (35 commits)
docs/system: riscv: Update description of CPU
target/riscv: add support for svpbmt extension
target/riscv: add support for svinval extension
target/riscv: add support for svnapot extension
target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
target/riscv: Ignore reserved bits in PTE for RV64
hw/intc: Add RISC-V AIA APLIC device emulation
target/riscv: Allow users to force enable AIA CSRs in HART
hw/riscv: virt: Use AIA INTC compatible string when available
target/riscv: Implement AIA IMSIC interface CSRs
target/riscv: Implement AIA xiselect and xireg CSRs
target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
target/riscv: Implement AIA interrupt filtering CSRs
target/riscv: Implement AIA hvictl and hviprioX CSRs
target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
target/riscv: Implement AIA local interrupt priorities
target/riscv: Allow AIA device emulation to set ireg rmw callback
target/riscv: Add defines for AIA CSRs
target/riscv: Add AIA cpu feature
target/riscv: Allow setting CPU feature from machine/device emulation
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Yu Li [Tue, 8 Feb 2022 13:07:23 +0000 (21:07 +0800)]
docs/system: riscv: Update description of CPU
Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.
Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <
9040401e-8f87-ef4a-d840-
6703f08d068c@bytedance.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Weiwei Li [Fri, 4 Feb 2022 02:26:58 +0000 (10:26 +0800)]
target/riscv: add support for svpbmt extension
- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <
20220204022658.18097-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Weiwei Li [Fri, 4 Feb 2022 02:26:57 +0000 (10:26 +0800)]
target/riscv: add support for svinval extension
- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check
- do nothing other than extension check for sfence.w.inval and sfence.inval.ir
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <
20220204022658.18097-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Weiwei Li [Fri, 4 Feb 2022 02:26:56 +0000 (10:26 +0800)]
target/riscv: add support for svnapot extension
- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <
20220204022658.18097-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Weiwei Li [Fri, 4 Feb 2022 02:26:55 +0000 (10:26 +0800)]
target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <
20220204022658.18097-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Guo Ren [Fri, 4 Feb 2022 02:26:54 +0000 (10:26 +0800)]
target/riscv: Ignore reserved bits in PTE for RV64
Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit Virtual-Memory System
2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <
20220204022658.18097-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:54 +0000 (23:16 +0530)]
hw/intc: Add RISC-V AIA APLIC device emulation
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for wired interrupts called APLIC (Advanced
Platform Level Interrupt Controller). The APLIC is capabable of
forwarding wired interupts to RISC-V HARTs directly or as MSIs
(Message Signaled Interupts).
This patch adds device emulation for RISC-V AIA APLIC.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-19-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:53 +0000 (23:16 +0530)]
target/riscv: Allow users to force enable AIA CSRs in HART
We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-18-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:52 +0000 (23:16 +0530)]
hw/riscv: virt: Use AIA INTC compatible string when available
We should use the AIA INTC compatible string in the CPU INTC
DT nodes when the CPUs support AIA feature. This will allow
Linux INTC driver to use AIA local interrupt CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-17-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:51 +0000 (23:16 +0530)]
target/riscv: Implement AIA IMSIC interface CSRs
The AIA specification defines IMSIC interface CSRs for easy access
to the per-HART IMSIC registers without using indirect xiselect and
xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-16-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:50 +0000 (23:16 +0530)]
target/riscv: Implement AIA xiselect and xireg CSRs
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-15-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:49 +0000 (23:16 +0530)]
target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
The AIA specification introduces new [m|s|vs]topi CSRs for
reporting pending local IRQ number and associated IRQ priority.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-14-anup@brainfault.org
[ Changed by AF:
- Fixup indentation
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:48 +0000 (23:16 +0530)]
target/riscv: Implement AIA interrupt filtering CSRs
The AIA specificaiton adds interrupt filtering support for M-mode
and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
take local interrupt 13 or above and selectively inject same local
interrupt to lower privilege modes.
At the moment, we don't have any local interrupts above 12 so we
add dummy implementation (i.e. read zero and ignore write) of AIA
interrupt filtering CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-13-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:47 +0000 (23:16 +0530)]
target/riscv: Implement AIA hvictl and hviprioX CSRs
The AIA hvictl and hviprioX CSRs allow hypervisor to control
interrupts visible at VS-level. This patch implements AIA hvictl
and hviprioX CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-12-anup@brainfault.org
[ Changes by AF:
- Fix possible unintilised variable error in rmw_sie()
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:46 +0000 (23:16 +0530)]
target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-11-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:45 +0000 (23:16 +0530)]
target/riscv: Implement AIA local interrupt priorities
The AIA spec defines programmable 8-bit priority for each local interrupt
at M-level, S-level and VS-level so we extend local interrupt processing
to consider AIA interrupt priorities. The AIA CSRs which help software
configure local interrupt priorities will be added by subsequent patches.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
20220204174700.534953-10-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:44 +0000 (23:16 +0530)]
target/riscv: Allow AIA device emulation to set ireg rmw callback
The AIA device emulation (such as AIA IMSIC) should be able to set
(or provide) AIA ireg read-modify-write callback for each privilege
level of a RISC-V HART.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-9-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:43 +0000 (23:16 +0530)]
target/riscv: Add defines for AIA CSRs
The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-8-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:42 +0000 (23:16 +0530)]
target/riscv: Add AIA cpu feature
We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-7-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:41 +0000 (23:16 +0530)]
target/riscv: Allow setting CPU feature from machine/device emulation
The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example,
AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-6-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:40 +0000 (23:16 +0530)]
target/riscv: Improve delivery of guest external interrupts
The guest external interrupts from an interrupt controller are
delivered only when the Guest/VM is running (i.e. V=1). This means
any guest external interrupt which is triggered while the Guest/VM
is not running (i.e. V=0) will be missed on QEMU resulting in Guest
with sluggish response to serial console input and other I/O events.
To solve this, we check and inject interrupt after setting V=1.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-5-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:39 +0000 (23:16 +0530)]
target/riscv: Implement hgeie and hgeip CSRs
The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external interrupt
to Guest/VM running at VS-level.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-4-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:38 +0000 (23:16 +0530)]
target/riscv: Implement SGEIP bit in hip and hie CSRs
A hypervisor can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-3-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Fri, 4 Feb 2022 17:46:37 +0000 (23:16 +0530)]
target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
We should be returning illegal instruction trap when RV64 HS-mode tries
to access RV32 HS-mode CSR.
Fixes:
d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id:
20220204174700.534953-2-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Tue, 1 Feb 2022 06:46:01 +0000 (14:46 +0800)]
target/riscv: Fix vill field write in vtype
The guest should be able to set the vill bit as part of vsetvl.
Currently we may set env->vill to 1 in the vsetvl helper, but there
is nowhere that we set it to 0, so once it transitions to 1 it's stuck
there until the system is reset.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <
20220201064601.41143-1-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Philipp Tomsich [Wed, 2 Feb 2022 00:52:49 +0000 (01:52 +0100)]
target/riscv: add a MAINTAINERS entry for XVentanaCondOps
The XVentanaCondOps extension is supported by VRULL on behalf of the
Ventana Micro. Add myself as a point-of-contact.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <
20220202005249.
3566542-8-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>