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Jason Ekstrand [Wed, 22 Aug 2018 01:40:50 +0000 (20:40 -0500)]
anv: Disable the vertex cache when tessellating on SKL GT4
I have no idea if I'm correct about what's going wrong or if this is the
correct fix. However, in my multiple weeks of banging my head on this
hang, a VUE reference counting bug seems to match all the symptoms and
it definitely fixes the hang.
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107280
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 21 Aug 2018 22:52:54 +0000 (17:52 -0500)]
anv: Implement a VF cache invalidate workaround
Known to fix nothing whatsoever but it's in the docs.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 21 Aug 2018 22:14:38 +0000 (17:14 -0500)]
anv: Re-emit vertex buffers when the pipeline changes
Some of the bits of VERTEX_BUFFER_STATE such as access type, instance
data step rate, and pitch come from the pipeline.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Marek Olšák [Thu, 6 Sep 2018 03:13:56 +0000 (23:13 -0400)]
radeonsi: pin the winsys thread to the requested L3 cache (v2)
v2: rebase
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 6 Sep 2018 03:12:27 +0000 (23:12 -0400)]
gallium/u_threaded: implement set_context_param for thread pinning (v2)
v2: - use set_context_param
- set set_context_param even if the driver doesn't implement it
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 6 Sep 2018 03:10:57 +0000 (23:10 -0400)]
st/mesa: pin driver threads to a specific L3 cache on AMD Zen (v2)
v2: use set_context_param
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 6 Sep 2018 02:57:19 +0000 (22:57 -0400)]
gallium: add pipe_context::set_context_param for tuning perf on AMD Zen (v2)
State trackers will not use the new param directly, but will instead use
a helper in MakeCurrent that does the right thing.
v2: rework the interface
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 6 Sep 2018 03:00:07 +0000 (23:00 -0400)]
gallium/os_thread: simplify helper pipe_current_thread_get_time_nano
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 6 Sep 2018 01:30:44 +0000 (21:30 -0400)]
gallium/u_cpu_detect: get the number of cores per L3 cache for AMD Zen
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 6 Sep 2018 00:11:34 +0000 (20:11 -0400)]
gallium/u_cpu_detect: fix parsing the CPU family
According to:
https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf
Also Intel:
https://www.microbe.cz/docs/CPUID.pdf
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 5 Sep 2018 23:15:56 +0000 (19:15 -0400)]
gallium/u_cpu_detect: fix a race condition on initialization
Reviewed-by: Brian Paul <brianp@vmware.com>
Dylan Baker [Tue, 21 Aug 2018 16:46:46 +0000 (09:46 -0700)]
Replace uses of _mesa_bitcount with util_bitcount
and _mesa_bitcount_64 with util_bitcount_64. This fixes a build problem
in nir for platforms that don't have popcount or popcountll, such as
32bit msvc.
v2: - Fix additional uses of _mesa_bitcount added after this was
originally written
Acked-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Dylan Baker [Fri, 17 Aug 2018 00:20:38 +0000 (17:20 -0700)]
move u_math to src/util
Currently we have two sets of functions for bit counts, one in gallium
and one in core mesa. The ones in core mesa are header only in many
cases, since they reduce to "#define _mesa_bitcount popcount", but they
provide a fallback implementation. This is important because 32bit msvc
doesn't have popcountll, just popcount; so when nir (for example)
includes the core mesa header it doesn't (and shouldn't) link with core
mesa. To fix this we'll promote the version out of gallium util, then
replace the core mesa uses with the util version, since nir (and other
non-core mesa users) can and do link with mesautils.
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Dylan Baker [Fri, 7 Sep 2018 17:19:33 +0000 (10:19 -0700)]
docs: update calendar, add news item and link release notes for X.Y.Z
Signed-off-by: Dylan Baker <dylan@pnwbakers.com>
Dylan Baker [Fri, 7 Sep 2018 17:10:13 +0000 (10:10 -0700)]
docs/relnotes: Add sha256 sums for mesa 18.1.8
Dylan Baker [Fri, 7 Sep 2018 15:27:26 +0000 (08:27 -0700)]
docs: Add release notes for 18.1.8
Jason Ekstrand [Fri, 7 Sep 2018 05:40:54 +0000 (00:40 -0500)]
i965: Workaround the gen9 hw astc5x5 sampler bug
gen9 hardware has a bug in the sampler cache that can cause GPU hangs
whenever an texture with aux compression enabled is in the sampler cache
together with an ASTC5x5 texture. Because we can't control what the
client binds at any given time, we have two options: resolve the CCS or
decompresss the ASTC. Doing a CCS or HiZ resolve is far less drastic
and will likely have a smaller performance impact.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Eric Anholt [Fri, 24 Aug 2018 22:45:37 +0000 (15:45 -0700)]
v3d: Fix setup of the VCM cache size.
There were two bugs working together to make things mostly work: I wasn't
dividing the VPM output size available by the size of a batch (vertex),
but I also had the size of the VPM reduced by a factor of 8.
Fixes dEQP-GLES3.functional.vertex_array_objects.all_attributes and it
seems also my intermittent varying failures.
Fixes:
1561e4984eb0 ("v3d: Emit the VCM_CACHE_SIZE packet.")
Eric Anholt [Thu, 6 Sep 2018 20:37:37 +0000 (13:37 -0700)]
v3d: Fix SRC_ALPHA_SATURATE blending for RTs without alpha.
Fixes
dEQP-GLES3.functional.fragment_ops.blend.default_framebuffer.rgb_func_alpha_func.dst.src_alpha_saturate_src_alpha_saturate
and friends with --deqp-egl-config-name=rgb565d0s0
Cc: "18.2" <mesa-stable@lists.freedesktop.org>
Lionel Landwerlin [Fri, 7 Sep 2018 10:55:45 +0000 (11:55 +0100)]
intel/genxml: turn SLM Enable bit into boolean
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Sergii Romantsov [Thu, 6 Sep 2018 09:59:47 +0000 (12:59 +0300)]
i965/tools: 32bit compilation with meson
Building of 32bit mesa with meson causes issue:
"implicit declaration of function ‘__builtin_ia32_clflush’".
Fixed by adding msse2 compilation flag.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107843
Fixes:
314879f7fec0 (i965: Fix asynchronous mappings on !LLC platforms.)
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Sergii Romantsov [Thu, 6 Sep 2018 08:07:45 +0000 (11:07 +0300)]
intel: compiler option msse2 and mstackrealign
Seems in case of 32-bit library, usage of msse2 makes
some stack corruption or incorrect instructions.
Usage with mstackrealign fixes that case.
v2: Fixed meson.
v3: Definition of c_sse2_args moved on the top (L.Landwerlin).
Added mstackrealign for Android's mks where msee4.1 is used.
v4: Added for Vulkan also.
v5: Commit message correction.
CC: <mesa-stable@lists.freedesktop.org>
Fixes:
6b05c080f202 (i965: Compile with -msse3)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107779
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Rob Clark [Fri, 7 Sep 2018 11:41:43 +0000 (07:41 -0400)]
freedreno: fix rast->depth_cleap_near/far
Fixes:
daa19363def gallium: split depth_clip into depth_clip_near & depth_clip_far
Signed-off-by: Rob Clark <robdclark@gmail.com>
Marek Olšák [Wed, 22 Aug 2018 02:00:11 +0000 (22:00 -0400)]
gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsi
Marek Olšák [Wed, 22 Aug 2018 01:59:23 +0000 (21:59 -0400)]
gallium: split depth_clip into depth_clip_near & depth_clip_far
for AMD_depth_clamp_separate.
Jason Ekstrand [Tue, 4 Sep 2018 18:58:01 +0000 (13:58 -0500)]
anv/pipeline: Only consider double elements which actually exist
The brw_vs_prog_data::double_inputs_read field comes directly from
shader_info::double_inputs which may contain inputs which are not
actually read. Instead of using it directly, AND it with inputs_read
which is only things which are read. Otherwise, we may end up
subtracting too many elements when computing elem_count.
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103241
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 31 Aug 2018 12:35:17 +0000 (07:35 -0500)]
nir: Drop the vs_inputs_dual_locations option
It was very inconsistently handled; the only things that made use of it
were glsl_to_nir, glspirv, and nir_gather_info. In particular,
nir_lower_io completely ignored it so anyone using nir_lower_io on
64-bit vertex attributes was going to be in for a shock. Also, as of
the previous commit, it's set by every driver that supports 64-bit
vertex attributes. There's no longer any reason to have it be an option
so let's just delete it.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Jason Ekstrand [Fri, 31 Aug 2018 12:55:07 +0000 (07:55 -0500)]
radeonsi/nir: Set vs_inputs_dual_locations and let NIR do the remap
We were going out of our way to disable dual-location re-mapping in NIR
only to then do the remapping in st_glsl_to_nir.cpp. Presumably, this
was so that double_inputs would be correct for the core state tracker.
However, now that we've it to gl_program::DualSlotInputs which is
unaffected by NIR lowering, we can let NIR lower things for us. The one
tricky bit here is that we have to remap the inputs_read bitfield back
to the single-slot convention for the gallium state tracker to use.
Since radeonsi is the only NIR-capable gallium driver that also supports
GL_ARB_vertex_attrib_64bit, we only have to worry about radeonsi when
making core gallium state tracker changes.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Jason Ekstrand [Thu, 30 Aug 2018 20:02:25 +0000 (15:02 -0500)]
compiler: Move double_inputs to gl_program::DualSlotInputs
Previously, we had two field in shader_info: double_inputs_read and
double_inputs. Presumably, the one was for all double inputs that are
read and the other is all that exist. However, because nir_gather_info
regenerates these two values, there is a possibility, if a variable gets
deleted, that the value of double_inputs could change over time. This
is a problem because double_inputs is used to remap the input locations
to a two-slot-per-dvec3/4 scheme for i965. If that mapping were to
change between glsl_to_nir and back-end state setup, we would fall over
when trying to map the NIR outputs back onto the GL location space.
This commit changes the way slot re-mapping works. Instead of the
double_inputs field in shader_info, it adds a DualSlotInputs bitfield to
gl_program. By having it in gl_program, we more easily guarantee that
NIR passes won't touch it after it's been set. It also makes more sense
to put it in a GL data structure since it's really a mapping from GL
slots to back-end and/or NIR slots and not really a NIR shader thing.
Tested-by: Alejandro Piñeiro <apinheiro@igalia.com> (ARB_gl_spirv tests)
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Thu, 6 Sep 2018 04:09:27 +0000 (00:09 -0400)]
gallium: add PIPE_CAP_RASTERIZER_SUBPIXEL_BITS
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Eric Engestrom [Tue, 17 Jul 2018 14:12:32 +0000 (15:12 +0100)]
meson: disable asserts by default on release builds
By the time Mesa 18.3 comes out (probably December '18), Meson 0.45 will
be 9 months old (March '18), so I think this is reasonable.
(btw, the currently-required Meson 0.44.1 was released less than 12 days
before 0.45, so we're really not bumping by much.)
Currently, the Meson versions in the major distributions are:
Arch: ships 0.47.2
CentOS: 7 ships 0.47.1
Debian: stable ships 0.37.1, so it hasn't been usable in a long time.
everything more recent ships 0.47.2
Fedora: 28 ships 0.45.1
FreeBSD: ships 0.46.1 (ports)
Gentoo: ships 0.46.1
OpenSUSE: 15 ships 0.46
Ubuntu: 18.04 ships 0.45.1
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Andrii Simiklit [Thu, 6 Sep 2018 14:43:54 +0000 (17:43 +0300)]
mesa/util: add missing va_end() after va_copy()
MSDN:
"va_end must be called on each argument list that's initialized
with va_start or va_copy before the function returns."
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107810
Fixes:
c6267ebd6c8a "gallium/util: Stop bundling our snprintf implementation."
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Andrii Simiklit [Thu, 6 Sep 2018 14:43:53 +0000 (17:43 +0300)]
mesa/util: don't ignore NULL returned from 'malloc'
We should exit from the function 'util_vasprintf'
with error code -1 for case where 'malloc'
returns NULL
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes:
864148d69e1e "util: add util_vasprintf() for Windows (v2)"
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Andrii Simiklit [Thu, 6 Sep 2018 14:43:52 +0000 (17:43 +0300)]
mesa/util: don't use the same 'va_list' instance twice
The first usage of the 'va_list' instance could change it.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes:
864148d69e1e "util: add util_vasprintf() for Windows (v2)"
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Andrii Simiklit [Thu, 6 Sep 2018 14:43:51 +0000 (17:43 +0300)]
apple/glx/log: added missing va_end() after va_copy()
Each invocation of va_copy() must be matched by a
corresponding invocation of va_end()
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes:
51691f0767f6 "darwin: Use ASL for logging"
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Eric Engestrom [Thu, 6 Sep 2018 14:39:07 +0000 (15:39 +0100)]
meson: drop unnecessary llvm version hacks
The current minimum meson version supported is 0.44.1, so we have met
both the 0.43 and 0.44 requirement to not need these hacks anymore :)
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Danylo Piliaiev [Thu, 6 Sep 2018 14:01:07 +0000 (17:01 +0300)]
mesa: add missing return statement for GL_RG_SNORM case
Fixes:
0d356cf4781bece0dc9a7 "mesa: enable EXT_render_snorm extension"
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Engestrom [Tue, 28 Aug 2018 16:16:48 +0000 (17:16 +0100)]
meson: consolidate langs lists
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Mon, 3 Sep 2018 17:07:45 +0000 (18:07 +0100)]
intel/compiler: remove unused get_image_base_type()
Unused since
09f1de97a76a4990fd7c "anv,i965: Lower away image derefs in
the driver".
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Mathias Fröhlich [Fri, 10 Aug 2018 09:37:43 +0000 (11:37 +0200)]
tnl: Fix green gun regression in xonotic.
Fix an other regression of
mesa: Make gl_vertex_array contain pointers to first order VAO members.
The regression showed up with drivers using the tnl module and
was reproducible using xonotic-glx -benchmark demos/the-big-keybench.dem.
Fixes:
64d2a204805
mesa: Make gl_vertex_array contain pointers to first order VAO members.
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Lionel Landwerlin [Thu, 6 Sep 2018 11:25:07 +0000 (12:25 +0100)]
Revert "i965/tools: 32bit compilation with meson"
This reverts commit
4aec44c0d9c4c0649c362199fac97efe0a3b38a4.
Unfortunately this patch needed a another one to be committed first.
Sergii Romantsov [Thu, 6 Sep 2018 09:59:47 +0000 (12:59 +0300)]
i965/tools: 32bit compilation with meson
Building of 32bit mesa with meson causes issue:
"implicit declaration of function ‘__builtin_ia32_clflush’".
Fixed by adding msse2 compilation flag.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107843
Fixes:
314879f7fec0 (i965: Fix asynchronous mappings on !LLC platforms.)
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Sat, 1 Sep 2018 13:57:38 +0000 (23:57 +1000)]
glsl: fixer lexer for unreachable defines
If we have something like:
#ifdef NOT_DEFINED
#define A_MACRO(x) \
if (x)
#endif
The # on the #define is not skipped but the define itself is so
this then gets recognised as #if.
Until
28a3731e3f this didn't happen because we ended up in
<HASH>{NONSPACE} where BEGIN INITIAL was called stopping the
problem from happening.
This change makes sure we never call RETURN_TOKEN_NEVER_SKIP for
if/else/endif when processing a define.
Cc: Ian Romanick <idr@freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107772
Tested-By: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Hyunjun Ko [Thu, 30 Aug 2018 02:58:54 +0000 (11:58 +0900)]
freedreno/ir3: insert mov if same instruction in the outputs.
For example,
result0 = texture(sampler[indexBase + 5], coords);
result1 = texture(sampler[indexBase + 0], coords);
result2 = texture(sampler[indexBase + 0], coords);
out_result0 = result0;
out_result1 = result1;
out_result2 = result2;
In this kind of case we need to insert an extra mov to the outputs
so that the result could be assigned to each register respectively.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Hyunjun Ko [Thu, 30 Aug 2018 02:58:53 +0000 (11:58 +0900)]
freedreno/ir3: make immediates array dynamic
Since most shaders wouldn't need that large array of immediates, making
the array dynamic could save unnecessary spaces.
In addition, sometimes we can potentially have a much larger array
of immediates to be lowered, which might be more than 64.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 3 Sep 2018 20:33:59 +0000 (16:33 -0400)]
freedreno: allocate ctx's batch on demand
Don't fall over when app wants more than 32 contexts. Instead allocate
contexts on demand.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 3 Sep 2018 20:07:17 +0000 (16:07 -0400)]
freedreno: add fd_context_batch() accessor
For cases in which (after the following commit) ctx->batch may be null.
Prep work for following commit.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 2 Sep 2018 17:24:12 +0000 (13:24 -0400)]
freedreno/a6xx: fix mem2gmem for zsbuf
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 29 Aug 2018 20:04:22 +0000 (16:04 -0400)]
freedreno/batch: fix crash in !reorder case
We aren't using the batch-cache if reorder==false.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 29 Aug 2018 19:31:13 +0000 (15:31 -0400)]
freedreno/ir3: better compile_error() printing
Try to show the error at the appropriate line of nir
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 22 Aug 2018 13:33:06 +0000 (09:33 -0400)]
freedreno/a6xx: bordercolor fixes
Port fixes from a5xx (
f0715442)
TODO maybe this should move to shared code, since it seems to be the
same.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 22 Aug 2018 13:07:37 +0000 (09:07 -0400)]
freedreno: fix context teardown harder
The border_color_uploaders need to be torn down before the transfer_pool
is destroyed.
Fixes:
e11e9d63943 freedreno: fix context teardown race
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 21 Aug 2018 12:33:39 +0000 (08:33 -0400)]
freedreno/ir3: ignore unused inputs
We could end up w/ inputs larger than vec4, simply because unused inputs
are not split.
Fixes things like dEQP-GLES31.functional.separate_shader.random.77 (and
probably a handful of others)
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 20 Aug 2018 14:55:37 +0000 (10:55 -0400)]
freedreno/a6xx: fix debug build crash
Porting
0c8d9e923aa9239e20f9bc969faf9caa0b85237f to a6xx.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Dylan Baker [Tue, 4 Sep 2018 21:42:07 +0000 (14:42 -0700)]
meson: Print a message about why a libdrm version was selected
We require a single version of libdrm for all of our libdrm
dependencies (core and driver), but the way this is structured can make
the error message less than helpful, as one driver might be the one
setting the libdrm requirement, while another might be the one that
generates the version failure.
This adds a simple message to the output announcing which libdrm module
set the version, which might be more helpful.
v2: - Use message suggested by Eric Engstrom
Fixes:
c445b1d56f47922206de55e557444aadb62e11f6
("meson: Use the same version for all libdrm checks")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Charmaine Lee [Fri, 5 May 2017 19:16:33 +0000 (12:16 -0700)]
svga: rename face to layer_face
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Mon, 31 Jul 2017 12:40:12 +0000 (06:40 -0600)]
svga: encode sample count in resource declarations
No regressions before the corresponding host-side change.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Charmaine Lee [Thu, 1 Jun 2017 22:12:14 +0000 (15:12 -0700)]
svga: sync with upstream changes to surface flags
SVGA device now supports 64 bits surface flags. This patch
updates the winsys interface to allow 64 bits surface flags.
The linux winsys layer will for now only honor the lower 32 bits of
the surface flags.
Reviewed-by: Brian Paul <brianp@vmware.com>
Neha Bhende [Wed, 10 May 2017 19:17:44 +0000 (12:17 -0700)]
svga: avoid try_blit() for some depth formats on non vgpu10.
On non vgpu10, driver doesn't support util_blitter_blit for SVGA3D_Z_D16,
SVGA3D_Z_D24x8, SVGA3D_Z_D24S8. Patch fixes following piglit tests regression on hwv8 caused
by commit
27bf35caea5e:
spec@arb_depth_texture@fbo-depth-gl-depth-component16-blit
spec@arb_depth_texture@fbo-depth-gl-depth-component24-blit
spec@arb_depth_texture@fbo-depth-gl-depth-component32-blit
Tested with mtt-piglit on hw 8,9,10,11,13 and mtt-glretrace on windows and linux.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Neha Bhende [Thu, 4 May 2017 18:25:04 +0000 (11:25 -0700)]
svga: convert dst format to linear when blending is enabled.
When blending is enabled, framebuffer colorspace has to be linear.
Previously, we never hit this case because we were not supporting sRGB
drawable. Previous patch added that support.
Tested with mtt glretrace, viewperf, piglit, conform.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Neha Bhende [Wed, 29 Mar 2017 17:35:12 +0000 (10:35 -0700)]
winsys/svga: Avoid cap2 code path for now
CAP2 functionality is not yet part of vmwgfx. This is causing unnecessary
dmesg error messages.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Neha Bhende [Mon, 6 Mar 2017 23:55:04 +0000 (15:55 -0800)]
svga: start using SVGA3dCmdIntraSurfaceCopy command for svga_blit.
Basically, SVGA3dCmdIntraSurfaceCopy command allow copying when
source and destination are same.
Tested with MTT piglit, glretrace, viewperf, conform
v2: changes as per Charmaine's comment
v3: changes as per Charmaine's comment
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Neha Bhende [Mon, 6 Mar 2017 23:50:20 +0000 (15:50 -0800)]
svga/winsys: Add cap2 support in winsys
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Neha Bhende [Mon, 6 Mar 2017 23:53:58 +0000 (15:53 -0800)]
svga: Add SVGA3dCmdIntraSurfaceCopy command support in OpenGL driver
v2: changes as per Charmaine's comment
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Wed, 5 Sep 2018 16:28:25 +0000 (10:28 -0600)]
svga: update device header files from upstream
This is a squash commit of several earlier patches.
Signed-off-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Thu, 9 Aug 2018 23:22:52 +0000 (16:22 -0700)]
winsys/drm: Fix assert when try to accumulate an invalid fd
This patch makes sure there is a valid fd before merging it
to the context's fd in vmw_svga_winsys_fence_server_sync().
This fixes the assert running webot.
No regression running kmscube.
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Eric Anholt [Thu, 30 Aug 2018 17:24:51 +0000 (10:24 -0700)]
loader: Drop unused argument from dri3_update_drawable().
The argument has never been used since the function was added.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Alejandro Piñeiro [Tue, 4 Sep 2018 11:02:57 +0000 (13:02 +0200)]
i965/fs: include multisamplers on image_intrinsic_coord_components
This is the second patch needed to fix the following piglit tests:
tests/spec/arb_gl_spirv/linker/uniform/multisampler.shader_test
tests/spec/arb_gl_spirv/linker/uniform/multisampler-array.shader_test
Although in this case it doesn't affect so many borrowed tests, as
there aren't too many tests using multisamplers on Intel.
It is worth to note that this patch is also needed when those tests
are run on GLSL mode (using the --glsl option). Although most Intel
drivers would not be able to run/execute tests using multisamplers, as
GL_MAX_IMAGE_SAMPLES is zero, technically those tests are expected to
link correctly, so linking tests should pass.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Wed, 5 Sep 2018 10:39:35 +0000 (12:39 +0200)]
i965: move brw_nir_lower_gl_images call
At this moment that lowering is using info coming from the
UniformStorage, so for the ARB_gl_spirv codepath, it needs to be done
after calling gl_nir_link_uniforms. As for the GLSL codepath it can
also be called later, we just move the call on both cases, to avoid
adding several shader->spirv_data checks, and keep the patch as small
as possible.
This is the first patch needed to fix the following piglit tests:
tests/spec/arb_gl_spirv/linker/uniform/multisampler.shader_test
tests/spec/arb_gl_spirv/linker/uniform/multisampler-array.shader_test
but fixes thousands of tests when borrowing the tests from other specs
(that needs to be done manually right now).
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Wed, 5 Sep 2018 10:34:47 +0000 (12:34 +0200)]
intel/compiler: rename brw_nir_lower_glsl_images
To brw_nir_lower_gl_images, as it will be also used on the
ARB_gl_spirv codepath, that doesn't involves GLSL at all. So the
lowering is about images following the OpenGL semantics. In any case
"brw_nir_lower_opengl_images" seemed too long to me, so I just used
gl. That shortening is already used on other parts of the code.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Tue, 4 Sep 2018 10:43:07 +0000 (12:43 +0200)]
intel/compiler: remove unused variable num_images
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Gert Wollny [Tue, 4 Sep 2018 07:36:53 +0000 (09:36 +0200)]
winsys/virgl/vtest: Correct off-by-one error in resource allocation
The resource bo array must already extended when the target index is
equal to the current size of the array.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Gert Wollny [Mon, 3 Sep 2018 08:14:07 +0000 (10:14 +0200)]
winsys/virgl: Initialize value to silence valgrind
Silences:
Conditional jump or move depends on uninitialised value(s)
at 0xB72F2C0: virgl_drm_winsys_create (virgl_drm_winsys.c:854)
by 0xB72F2C0: virgl_drm_screen_create (virgl_drm_winsys.c:926)
by 0xB21C885: pipe_virgl_create_screen (drm_helper.h:275)
by 0xB7201F0: pipe_loader_create_screen (pipe_loader.c:137)
by 0xB639C91: dri2_init_screen (dri2.c:2112)
by 0xB634F68: driCreateNewScreen2 (dri_util.c:153)
by 0x63023E6: dri3_create_screen (dri3_glx.c:893)
by 0x62D35BD: AllocAndFetchScreenConfigs (glxext.c:820)
by 0x62D35BD: __glXInitialize (glxext.c:946)
by 0x62CECB3: GetGLXPrivScreenConfig (glxcmds.c:174)
by 0x62CF69C: glXQueryExtensionsString (glxcmds.c:1304)
by 0x60AA7D9: ??? (in /usr/lib/x86_64-linux-gnu/libwaffle-1.so.0.5.2)
by 0x4F81450: wfl_checked_display_connect (piglit-util-waffle.h:74)
by 0x4F829E0: piglit_wfl_framework_init (piglit_wfl_framework.c:627)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Gert Wollny [Mon, 3 Sep 2018 08:05:44 +0000 (10:05 +0200)]
winsys/virgl: correct resource and handle allocation (v2)
Fixes crash with
piglit/bin/map_buffer_range-invalidate CopyBufferSubData \
increment-offset -auto -fbo
* Resize the resource storage already when the count is equal to the
allocated size, fixes:
Invalid write of size 8
at 0xB72E4CF: virgl_drm_add_res (virgl_drm_winsys.c:629)
by 0xB72E4CF: virgl_drm_emit_res (virgl_drm_winsys.c:663)
by 0xB72A44A: virgl_encode_resource_copy_region (virgl_encode.c:776)
by 0xB40CD12: st_copy_buffer_subdata (st_cb_bufferobjects.c:585)
by 0xB244A3B: _mesa_CopyBufferSubData (bufferobj.c:2940)
by 0x109A1E: upload (invalidate.c:169)
by 0x109C2F: piglit_display (invalidate.c:215)
by 0x4F80FBE: run_test (piglit_fbo_framework.c:52)
by 0x4F66E5F: piglit_gl_test_run (piglit-framework-gl.c:229)
by 0x10949D: main (invalidate.c:47)
Address 0xbe07d30 is 0 bytes after a block of size 4,096 alloc'd
at 0x4C31B25: calloc (in
/usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
by 0xB72DAAF: virgl_drm_cmd_buf_create (virgl_drm_winsys.c:567)
* Also resize the space allocated for the handles, fixes:
Invalid write of size 4
at 0xB72E4F0: virgl_drm_add_res (virgl_drm_winsys.c:631)
by 0xB72E4F0: virgl_drm_emit_res (virgl_drm_winsys.c:663)
by 0xB72A44A: virgl_encode_resource_copy_region (virgl_encode.c:776)
by 0xB40CD12: st_copy_buffer_subdata (st_cb_bufferobjects.c:585)
by 0xB244A3B: _mesa_CopyBufferSubData (bufferobj.c:2940)
by 0x109A1E: upload (invalidate.c:169)
by 0x109C2F: piglit_display (invalidate.c:215)
by 0x4F80FBE: run_test (piglit_fbo_framework.c:52)
by 0x4F66E5F: piglit_gl_test_run (piglit-framework-gl.c:229)
by 0x10949D: main (invalidate.c:47)
Address 0xbe08570 is 0 bytes after a block of size 2,048 alloc'd
at 0x4C2FB0F: malloc (
in /usr/lib/valgrind/vgpreload_memcheck-amd64- linux.so)
by 0xB72DAC8: virgl_drm_cmd_buf_create (virgl_drm_winsys.c:572)
Fixes:
4b15b5e803e ("virgl: resize resource bo allocation if we need to.")
v2: - Use REALLOC macro and avoid memory leak when re-allocation fails
- add Fixes tag (both Emil Velikov)
- reorder commit message
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Tomeu Vizoso [Tue, 17 Jul 2018 11:13:21 +0000 (13:13 +0200)]
virgl: use hw-atomics instead of in-ssbo ones
Emulating atomics on top of ssbos can lead to too small max SSBO count,
so let's use the hw-atomics mechanism to expose atomic buffers instead.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Erik Faye-Lund [Wed, 29 Aug 2018 07:07:26 +0000 (09:07 +0200)]
virgl: update minor differences to upstream header
virgl_protocol.h is considered to have it's upstream in the
virglrenderer repository, and somehow these minor differences has
crept in.
Let's sync with the upstream to avoid this.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Erik Faye-Lund [Wed, 29 Aug 2018 14:11:14 +0000 (16:11 +0200)]
gallium: add PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER{S,_BUFFERS}
This moves the evergreen-specific max-sizes out as a driver-cap, so
other drivers with less strict requirements also can use hw-atomics.
Remove ssbo_atomic as it's no longer needed.
We should now be able to use hw-atomics for some stages and not for
other, if needed.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Erik Faye-Lund [Thu, 30 Aug 2018 09:04:17 +0000 (11:04 +0200)]
gallium: add PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS
This gets rid of a r600 specific hack in the state-tracker, and prepares
for other drivers to be able to use hw-atomics.
While we're at it, clean up some indentation in the various drivers.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Erik Faye-Lund [Wed, 29 Aug 2018 13:48:29 +0000 (15:48 +0200)]
st/mesa: simplify MaxAtomicBufferSize-logic
MaxAtomicCounters has already been assigned in the loop above in the
ssbo_atomic = true case, so this will calculate the same value as the
default.
While we're at it, fixup indentation on the MaxAtomicBufferBindings
assign.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Erik Faye-Lund [Wed, 29 Aug 2018 13:35:11 +0000 (15:35 +0200)]
st/mesa: clean up atomic vs ssbo code
This makes the code a bit easier to follow; we first set up
MaxShaderStorageBlocks, then we either set up a dedicated
MaxAtomicBuffers, or we split MaxShaderStorageBlocks in two.
While we're at it, also make the SSBO-splitting code tolerate the
hypothetical case of having an odd number of SSBOs without incorrectly
dropping the last SSBO.
This has the nice result that the SSBOs and atomic buffers are dealt
with almost completely orthogonally, easing some upcoming patches.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Erik Faye-Lund [Wed, 29 Aug 2018 13:24:26 +0000 (15:24 +0200)]
st/mesa: use real bool for can_ubo
We're doing full c99 now, so there's no point in using the old boolean
type.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Marek Olšák [Sat, 1 Sep 2018 07:10:27 +0000 (03:10 -0400)]
gallium/u_threaded: increase batch size to increase performance
This reduces mutex overhead.
radeonsi: +4.4% performance with piglit/drawoverhead, DrawElements, Ryzen X1700
iris_dri.so: +14% with piglit/drawoverhead, DrawArrays, i7 7700HQ.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Marek Olšák [Mon, 20 Aug 2018 18:52:52 +0000 (14:52 -0400)]
st/vdpau: silence an unitialized-variable warning
Marek Olšák [Tue, 21 Aug 2018 01:33:24 +0000 (21:33 -0400)]
st/mesa: help fix stencil border color for GL_DEPTH_STENCIL textures
GL_STENCIL_INDEX uses GL_INTENSITY for the border color, which is nicer
to hardware that doesn't read the stencil border value from the X channel.
This fixes a bunch of dEQP tests on Vega & Raven.
Cc: 18.1 18.2 <mesa-stable@lists.freedesktop.org>
Ernestas Kulik [Thu, 30 Aug 2018 16:02:44 +0000 (19:02 +0300)]
glsl_to_tgsi: Fix potential leak
Reported by Coverity: arr_live_ranges is freed in a different branch
than the one in which it was allocated.
Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Ernestas Kulik [Thu, 30 Aug 2018 16:02:45 +0000 (19:02 +0300)]
u_vbuf: Fix leak
Reported by Coverity: data is heap-allocated, but only freed in the
info->index_size != 0 branch.
Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Cc: 18.2 <mesa-stable@lists.freedesktop.org>
Eric Anholt [Sat, 11 Aug 2018 01:15:45 +0000 (18:15 -0700)]
freedreno: Drop a bunch of duplicated gallium PIPE_CAP default code.
Now that we have the util function for the default values, we can get rid
of the boilerplate.
v2: Rebase on new gallium caps
Reviewed-by: Rob Clark <robdclark@gmail.com> (v1)
Eric Anholt [Sat, 11 Aug 2018 01:04:40 +0000 (18:04 -0700)]
v3d: Drop a bunch of duplicated gallium PIPE_CAP default code.
Now that we have the util function for the default values, we can get rid
of the boilerplate.
v2: Rebase on new gallium caps
Eric Anholt [Sat, 11 Aug 2018 01:02:02 +0000 (18:02 -0700)]
vc4: Drop a bunch of duplicated gallium PIPE_CAP default code.
Now that we have the util function for the default values, we can get rid
of the boilerplate.
v2: drop GLSL level in favor of defaults.
v3: Rebase on new gallium caps
Eric Anholt [Fri, 10 Aug 2018 23:57:31 +0000 (16:57 -0700)]
gallium: Add a helper for implementing PIPE_CAP_* default values.
One of the pains of implementing a gallium driver is filling in a million
pipe caps you don't know about yet when you're just starting out. One of
the pains of working on gallium is copy-and-pasting your new PIPE_CAP into
each driver. We can fix both of these by having each driver call into the
default helper from their default case, so that both sides can ignore each
other until they need to.
v2: fix i915g build, revert swr change to avoid breaking scons build
(https://travis-ci.org/anholt/mesa/jobs/
419739857)
v3: Rebase on 3 new gallium caps.
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Cc: Bruce Cherniak <bruce.cherniak@intel.com>
Cc: George Kyriazis <george.kyriazis@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Mon, 3 Sep 2018 18:20:54 +0000 (13:20 -0500)]
intel/compiler: Remove redundant nir_remove_dead_variables call
As of
07a2098a708a2, brw_nir_optimize calls nir_remove_dead_variables as
the last optimization. Doing it again is just pointless.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Lionel Landwerlin [Thu, 23 Aug 2018 13:34:19 +0000 (14:34 +0100)]
intel: compiler: remove dead local variables at optimization pass
We're hitting an assert in gfxbench because one of the local variable
is a sampler (according to Jason this isn't valid) :
testfw_app: ../src/compiler/nir_types.cpp:551: void glsl_get_natural_size_align_bytes(const glsl_type*, unsigned int*, unsigned int*): Assertion `!"type does not have a natural size"' failed.
Since this particular variable isn't used, it can be eliminated by
removing unused local variables at the end of the optimization loop.
This makes sense also for valid local variables.
v2: Move additional local variable removal out of optimization loop,
but before large constant removal (Jason/Lionel)
v3: Move the removal at the end of brw_nir_optimize()
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107806
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Andrii Simiklit [Mon, 20 Aug 2018 16:20:59 +0000 (19:20 +0300)]
intel/decoder: fix the possible out of bounds group_iter
The "gen_group_get_length" function can return a negative value
and it can lead to the out of bounds group_iter.
v2: printing of "unknown command type" was added
v3: just the asserts are added
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bas Nieuwenhuizen [Mon, 3 Sep 2018 00:34:04 +0000 (02:34 +0200)]
radv: Fix CMASK dimensions.
Mirrors
1e40f694831 "ac/surface: fix CMASK fast clear for NPOT textures with mipmapping on SI/CI/VI"
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Mon, 3 Sep 2018 00:30:48 +0000 (02:30 +0200)]
radv: Use a lower max offchip buffer count.
No clue what gets fixed by this but both radeonsi and amdvlk do it.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Mon, 3 Sep 2018 00:19:25 +0000 (02:19 +0200)]
radv: Add VEGA20 support.
Just mirror the radeonsi bits. Since this is just adding the extra
switch entries for new HW I think this should be fine for stable.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Fri, 31 Aug 2018 05:55:15 +0000 (15:55 +1000)]
radv: don't expose linear depth surfaces on SI/CIK/VI either.
ac_surface.c: gfx6_compute_surface says
/* DB doesn't support linear layouts. */
Now if we expose linear depth and create a linear depth image
and use CmdCopyImage to copy into it, we can't map the underlying
memory and read it linearly which I think should work.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Mauro Rossi [Wed, 15 Aug 2018 12:46:25 +0000 (14:46 +0200)]
egl/android: do not indent HAVE_DRM_GRALLOC preprocessor directive
Fixes:
3f7bca44d9 ("egl/android: #ifdef out flink name support")
Fixes:
c7bb82136b ("egl/android: Add DRM node probing and filtering")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Jason Ekstrand [Sat, 1 Sep 2018 14:11:17 +0000 (09:11 -0500)]
anv/blorp: Fix a comment as per Nanley's review feedback
This accidentally didn't make it into
62378c5e9e5
Jason Ekstrand [Thu, 30 Aug 2018 17:05:06 +0000 (12:05 -0500)]
anv/blorp: Do more flushing around HiZ clears
We make the flush after a HiZ clear unconditional and add a flush/stall
before the clear as well.
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107760
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>