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Devang Patel [Tue, 3 Jan 2012 18:22:10 +0000 (18:22 +0000)]
Intel style asm variant does not need '%' prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147453
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Stepan Dyatkovskiy [Tue, 3 Jan 2012 14:05:04 +0000 (14:05 +0000)]
Type: replaced usage of ID with getTypeID().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147446
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Elena Demikhovsky [Tue, 3 Jan 2012 11:59:04 +0000 (11:59 +0000)]
Fixed a bug in SelectionDAG.cpp.
The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.
The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.
I added a special test that checks vector shuffle on win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147445
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Andrew Trick [Mon, 2 Jan 2012 21:25:10 +0000 (21:25 +0000)]
Fix SCEVExpander to handle loops with no preheader when LSR gives it a
"phony" insertion point.
Fixes rdar://
10619599: "SelectionDAGBuilder shouldn't visit PHI nodes!" assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147439
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Duncan Sands [Mon, 2 Jan 2012 16:55:01 +0000 (16:55 +0000)]
Correct spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147435
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Chandler Carruth [Mon, 2 Jan 2012 09:19:48 +0000 (09:19 +0000)]
Undo the hack in r147427 and move this unittest to a better home. This
is testing the bitcode reader's functionality, not VMCore's. Add the
what is a hope sufficient build system mojo to build and run a new
unittest.
Also clean up some of the test's naming. The goal for the file should be
to unittest the Bitcode Reader, and this is just one particular test
among potentially many in the future. Also, reverse my position and
relegate the PR# to a comment, but stash the comment on the same line as
the test name so it doesn't get lost. This makes the code more
self-documenting hopefully w/o losing track of the PR number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147431
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Craig Topper [Mon, 2 Jan 2012 09:17:37 +0000 (09:17 +0000)]
Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147430
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Craig Topper [Mon, 2 Jan 2012 08:46:48 +0000 (08:46 +0000)]
Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147428
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Chandler Carruth [Mon, 2 Jan 2012 08:40:40 +0000 (08:40 +0000)]
Fix unittest makefile after r147425. This should unbreak the makefile
build. This didn't show up in the CMake build because the CMake build
for the unittests is rather poorly factored.
This probably isn't the correct fix. This should be a bitcode reader
unittest not a VMCore unittest. I'll move it and clean various parts of
the unittest up in a follow-up patch, but I wanted to unbreak the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147427
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Nadav Rotem [Mon, 2 Jan 2012 08:05:46 +0000 (08:05 +0000)]
Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147426
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Rafael Espindola [Mon, 2 Jan 2012 07:49:53 +0000 (07:49 +0000)]
Materialize functions whose basic blocks are used by global variables. Fixes
PR11677.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147425
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Craig Topper [Sun, 1 Jan 2012 19:51:58 +0000 (19:51 +0000)]
Allow CRC32 instructions to be selected when AVX is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147411
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Craig Topper [Sun, 1 Jan 2012 19:40:22 +0000 (19:40 +0000)]
Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147409
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Benjamin Kramer [Sun, 1 Jan 2012 17:55:36 +0000 (17:55 +0000)]
X86Disassembler: Fix undefined behavior found by GCC 4.6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147404
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Benjamin Kramer [Sun, 1 Jan 2012 17:55:30 +0000 (17:55 +0000)]
PatternMatch: Introduce a matcher for instructions with the "exact" bit. Use it to simplify a few matchers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147403
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Benjamin Kramer [Sun, 1 Jan 2012 17:55:23 +0000 (17:55 +0000)]
PatternMatch: Simplify code by reusing the Operator class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147402
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Rafael Espindola [Sun, 1 Jan 2012 17:36:23 +0000 (17:36 +0000)]
Revert 147399. It broke CodeGen/ARM/vext.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147400
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Elena Demikhovsky [Sun, 1 Jan 2012 16:22:47 +0000 (16:22 +0000)]
Fixed a bug in SelectionDAG.cpp.
The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.
The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.
I added a special test that checks vector shuffle on win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147399
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NAKAMURA Takumi [Sun, 1 Jan 2012 08:16:56 +0000 (08:16 +0000)]
Happy new year 2012!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147395
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Craig Topper [Sat, 31 Dec 2011 23:50:21 +0000 (23:50 +0000)]
Merge X86 SHUFPS and SHUFPD node types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147394
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Craig Topper [Sat, 31 Dec 2011 23:24:49 +0000 (23:24 +0000)]
Add patterns for integer forms of SHUFPD/VSHUFPD with a memory load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147393
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Craig Topper [Sat, 31 Dec 2011 23:15:11 +0000 (23:15 +0000)]
Fix typo in a SHUFPD and VSHUFPD pattern that prevented SHUFPD/VSHUFPD with a load from being selected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147392
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Nick Lewycky [Sat, 31 Dec 2011 21:30:22 +0000 (21:30 +0000)]
Make use of the exact bit when optimizing '(X >>exact 3) << 1' to eliminate the
'and' that would zero out the trailing bits, and to produce an exact shift
ourselves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147391
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Dylan Noblesmith [Sat, 31 Dec 2011 13:58:58 +0000 (13:58 +0000)]
VMCore: add assert for miscompile
See PR11652. Trying to add this assert to
setSubclassData() itself actually prevented
the miscompile entirely, so it has to be here.
This makes the source of the bug more obvious
than the other asserts triggering later on did.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147390
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Bruno Cardoso Lopes [Fri, 30 Dec 2011 21:09:41 +0000 (21:09 +0000)]
Cleanup Mips code and rename some variables. Patch by Jack Carter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147383
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Bruno Cardoso Lopes [Fri, 30 Dec 2011 21:04:30 +0000 (21:04 +0000)]
Improve Mips JIT.
Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.
Patch by Sasa Stankovic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147382
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Nick Lewycky [Fri, 30 Dec 2011 19:17:23 +0000 (19:17 +0000)]
Remove extraneous ".get()->" which is just "->". No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147379
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Craig Topper [Fri, 30 Dec 2011 07:16:00 +0000 (07:16 +0000)]
Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147369
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Craig Topper [Fri, 30 Dec 2011 06:23:39 +0000 (06:23 +0000)]
Add disassembler support for VPERMIL2PD and VPERMIL2PS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368
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Craig Topper [Fri, 30 Dec 2011 05:20:36 +0000 (05:20 +0000)]
Add FMA4 instructions to disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367
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Craig Topper [Fri, 30 Dec 2011 04:48:54 +0000 (04:48 +0000)]
Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147366
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Craig Topper [Fri, 30 Dec 2011 03:33:59 +0000 (03:33 +0000)]
Combine FMA4 SS/SD patterns with the instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147365
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Craig Topper [Fri, 30 Dec 2011 03:17:15 +0000 (03:17 +0000)]
Combine FMA4 PS/PD patterns with the instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147364
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Craig Topper [Fri, 30 Dec 2011 02:18:36 +0000 (02:18 +0000)]
Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147361
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Craig Topper [Fri, 30 Dec 2011 01:49:53 +0000 (01:49 +0000)]
Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147360
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Hal Finkel [Fri, 30 Dec 2011 00:34:00 +0000 (00:34 +0000)]
Cleanup stack/frame register define/kill states. This fixes two bugs:
1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).
2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147359
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Rafael Espindola [Thu, 29 Dec 2011 21:43:03 +0000 (21:43 +0000)]
Implement cfi_restore. Patch by Brian Anderson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147356
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Rafael Espindola [Thu, 29 Dec 2011 21:09:08 +0000 (21:09 +0000)]
Rename Remember and Restore to RememberState and RestoreState for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147354
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Craig Topper [Thu, 29 Dec 2011 20:43:40 +0000 (20:43 +0000)]
Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353
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Rafael Espindola [Thu, 29 Dec 2011 20:24:47 +0000 (20:24 +0000)]
Implement .cfi_escape. Patch by Brian Anderson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147352
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Craig Topper [Thu, 29 Dec 2011 20:03:14 +0000 (20:03 +0000)]
Expose FMA3 instructions to the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147351
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Craig Topper [Thu, 29 Dec 2011 19:46:19 +0000 (19:46 +0000)]
Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147349
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Craig Topper [Thu, 29 Dec 2011 19:25:56 +0000 (19:25 +0000)]
Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147348
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Craig Topper [Thu, 29 Dec 2011 18:47:31 +0000 (18:47 +0000)]
Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147347
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Craig Topper [Thu, 29 Dec 2011 18:08:36 +0000 (18:08 +0000)]
Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147345
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Craig Topper [Thu, 29 Dec 2011 18:00:08 +0000 (18:00 +0000)]
Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147344
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Craig Topper [Thu, 29 Dec 2011 17:41:56 +0000 (17:41 +0000)]
Remove the separate explicit AES instruction patterns. They are equivalent to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147342
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Craig Topper [Thu, 29 Dec 2011 15:51:45 +0000 (15:51 +0000)]
Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147339
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Craig Topper [Thu, 29 Dec 2011 03:34:54 +0000 (03:34 +0000)]
Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147337
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Craig Topper [Thu, 29 Dec 2011 03:20:51 +0000 (03:20 +0000)]
Remove some elses after returns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147336
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Craig Topper [Thu, 29 Dec 2011 03:09:33 +0000 (03:09 +0000)]
Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147335
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Rafael Espindola [Thu, 29 Dec 2011 02:15:06 +0000 (02:15 +0000)]
Fix grammar error noticed by Duncan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147333
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Nick Lewycky [Wed, 28 Dec 2011 23:24:21 +0000 (23:24 +0000)]
Change CaptureTracking to pass a Use* instead of a Value* when a value is
captured. This allows the tracker to look at the specific use, which may be
especially interesting for function calls.
Use this to fix 'nocapture' deduction in FunctionAttrs. The existing one does
not iterate until a fixpoint and does not guarantee that it produces the same
result regardless of iteration order. The new implementation builds up a graph
of how arguments are passed from function to function, and uses a bottom-up walk
on the argument-SCCs to assign nocapture. This gets us nocapture more often, and
does so rather efficiently and independent of iteration order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147327
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Eli Friedman [Wed, 28 Dec 2011 21:24:44 +0000 (21:24 +0000)]
Fix type-checking for load transformation which is not legal on floating-point types. PR11674.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147323
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Bob Wilson [Wed, 28 Dec 2011 18:51:08 +0000 (18:51 +0000)]
Update OCaml bindings for the new half float type.
Patch by Jonathan Ragan-Kelley!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147314
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Rafael Espindola [Wed, 28 Dec 2011 17:08:00 +0000 (17:08 +0000)]
Add support for mipsel in configure. Fixes PR11669. Patch by Sylvestre Ledru.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147312
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Nadav Rotem [Wed, 28 Dec 2011 13:08:20 +0000 (13:08 +0000)]
PR11662.
Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147309
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Elena Demikhovsky [Wed, 28 Dec 2011 08:14:01 +0000 (08:14 +0000)]
Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR.
Matching MOVLP mask for AVX (265-bit vectors) was wrong.
The failure was detected by conformance tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147308
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Nick Lewycky [Wed, 28 Dec 2011 06:57:32 +0000 (06:57 +0000)]
Demystify this comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147307
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Rafael Espindola [Tue, 27 Dec 2011 21:37:11 +0000 (21:37 +0000)]
PR11642 has been fixed, enable -fvisibility-inlines-hidden everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147296
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Benjamin Kramer [Tue, 27 Dec 2011 20:35:07 +0000 (20:35 +0000)]
Switch StringMap from an array of structures to a structure of arrays.
- -25% memory usage of the main table on x86_64 (was wasted in struct padding).
- no significant performance change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147294
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Nick Lewycky [Tue, 27 Dec 2011 18:27:22 +0000 (18:27 +0000)]
Use false not zero, as a bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147292
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Nick Lewycky [Tue, 27 Dec 2011 18:25:50 +0000 (18:25 +0000)]
Turn cos(-x) into cos(x). Patch by Alexander Malyshev!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147291
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Benjamin Kramer [Tue, 27 Dec 2011 11:41:05 +0000 (11:41 +0000)]
Clean up some Release build warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147289
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Craig Topper [Tue, 27 Dec 2011 06:27:23 +0000 (06:27 +0000)]
Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147287
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Nick Lewycky [Tue, 27 Dec 2011 04:31:52 +0000 (04:31 +0000)]
Teach simplifycfg to recompute branch weights when merging some branches, and
to discard weights when appropriate. Still more to do (and a new TODO), but
it's a start!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147286
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Nick Lewycky [Tue, 27 Dec 2011 01:17:40 +0000 (01:17 +0000)]
Using Inst->setMetadata(..., NULL) should be safe to remove metadata even when
there is non of that type to remove. This fixes a crasher in the particular
case where the instruction has metadata but no metadata storage in the context
(this is only possible if the instruction has !dbg but no other metadata info).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147285
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Rafael Espindola [Mon, 26 Dec 2011 23:12:42 +0000 (23:12 +0000)]
Fix warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147284
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Eli Friedman [Mon, 26 Dec 2011 22:49:32 +0000 (22:49 +0000)]
Make sure DAGCombiner doesn't introduce multiple loads from the same memory location. PR10747, part 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147283
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Nick Lewycky [Mon, 26 Dec 2011 20:54:14 +0000 (20:54 +0000)]
Update the branch weight metadata when reversing the order of a branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147280
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Nick Lewycky [Mon, 26 Dec 2011 20:37:40 +0000 (20:37 +0000)]
Sort includes, canonicalize whitespace, fix typos. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147279
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Nadav Rotem [Sun, 25 Dec 2011 21:32:35 +0000 (21:32 +0000)]
Update the LangRef documentation: the codegen does support this instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147274
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Nadav Rotem [Sun, 25 Dec 2011 20:01:38 +0000 (20:01 +0000)]
Fix a typo in the widening of vectors in PromoteIntRes. Patch by Shemer Anat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147272
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Venkatraman Govindaraju [Sun, 25 Dec 2011 18:50:24 +0000 (18:50 +0000)]
Sparc: Implement emitFrameIndexDebugValue and getDebugValue Location hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147269
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Bill Wendling [Sun, 25 Dec 2011 06:56:22 +0000 (06:56 +0000)]
Add braces to remove silly warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147264
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Rafael Espindola [Sun, 25 Dec 2011 01:20:19 +0000 (01:20 +0000)]
Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147261
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Chandler Carruth [Sat, 24 Dec 2011 22:34:15 +0000 (22:34 +0000)]
Add an explicit test that we now fold cttz.i32(..., true) >> 5 -> 0.
This is a result of Benjamin's work on ValueTracking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147259
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Benjamin Kramer [Sat, 24 Dec 2011 17:31:53 +0000 (17:31 +0000)]
InstCombine: Add a combine that turns (2^n)-1 ^ x back into (2^n)-1 - x iff x is smaller than 2^n and it fuses with a following add.
This was intended to undo the sub canonicalization in cases where it's not profitable, but it also
finds some cases on it's own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147256
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Benjamin Kramer [Sat, 24 Dec 2011 17:31:46 +0000 (17:31 +0000)]
ComputeMaskedBits: Make knownzero computation more aggressive for ctlz with undef zero.
unsigned foo(unsigned x) { return 31 - __builtin_clz(x); }
now compiles into a single "bsrl" instruction on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147255
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Benjamin Kramer [Sat, 24 Dec 2011 17:31:38 +0000 (17:31 +0000)]
InstCombine: Canonicalize (2^n)-1 - x into (2^n)-1 ^ x iff x is known to be smaller than 2^n.
This has the obvious advantage of being commutable and is always a win on x86 because
const - x wastes a register there. On less weird architectures this may lead to
a regression because other arithmetic doesn't fuse with it anymore. I'll address that
problem in a followup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147254
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Rafael Espindola [Sat, 24 Dec 2011 14:47:52 +0000 (14:47 +0000)]
Section relative fixups are a coff concept, not a x86 one. Replace the
x86 specific reloc_coff_secrel32 with a generic FK_SecRel_4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147252
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Chandler Carruth [Sat, 24 Dec 2011 12:12:34 +0000 (12:12 +0000)]
Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when the
LZCNT instructions are available. Force promotion to i32 to get
a smaller encoding since the fix-ups necessary are just as complex for
either promoted type
We can't do standard promotion for CTLZ when lowering through BSR
because it results in poor code surrounding the 'xor' at the end of this
instruction. Essentially, if we promote the entire CTLZ node to i32, we
end up doing the xor on a 32-bit CTLZ implementation, and then
subtracting appropriately to get back to an i8 value. Instead, our
custom logic just uses the knowledge of the incoming size to compute
a perfect xor. I'd love to know of a way to fix this, but so far I'm
drawing a blank. I suspect the legalizer could be more clever and/or it
could collude with the DAG combiner, but how... ;]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147251
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Chandler Carruth [Sat, 24 Dec 2011 11:46:10 +0000 (11:46 +0000)]
Add systematic testing for cttz as well, and fix the bug I spotted by
inspection earlier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147250
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Chandler Carruth [Sat, 24 Dec 2011 11:26:59 +0000 (11:26 +0000)]
Add i8 and i64 testing for ctlz on x86. Also simplify the i16 test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147249
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Chandler Carruth [Sat, 24 Dec 2011 11:26:57 +0000 (11:26 +0000)]
Tidy up this rather crufty test. Put the declarations at the top to make
my C-brain happy. Remove the unnecessary bits of pedantic IR fluff like
nounwind. Remove stray uses comments. Name things semantically rather
than tN so that adding a new test in the middle doesn't cause pain, and
so that new tests can be grouped semantically.
This exposes how little systematic testing is going on here. I noticed
this by finding several bugs via inspection and wondering why this test
wasn't catching any of them. =[
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147248
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Benjamin Kramer [Sat, 24 Dec 2011 11:23:32 +0000 (11:23 +0000)]
Chandler fixed this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147247
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Chandler Carruth [Sat, 24 Dec 2011 11:11:38 +0000 (11:11 +0000)]
Expand more when we have a nice 'tzcnt' instruction, to avoid generating
'bsf' instructions here.
This one is actually debatable to my eyes. It's not clear that any chip
implementing 'tzcnt' would have a slow 'bsf' for any reason, and unless
EFLAGS or a zero input matters, 'tzcnt' is just a longer encoding.
Still, this restores the old behavior with 'tzcnt' enabled for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147246
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Chandler Carruth [Sat, 24 Dec 2011 11:11:36 +0000 (11:11 +0000)]
Tidy up some of these tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147245
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Chandler Carruth [Sat, 24 Dec 2011 10:55:54 +0000 (10:55 +0000)]
Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to the
X86ISelLowering C++ code. Because this is lowered via an xor wrapped
around a bsr, we want the dagcombine which runs after isel lowering to
have a chance to clean things up. In particular, it is very common to
see code which looks like:
(sizeof(x)*8 - 1) ^ __builtin_clz(x)
Which is trying to compute the most significant bit of 'x'. That's
actually the value computed directly by the 'bsr' instruction, but if we
match it too late, we'll get completely redundant xor instructions.
The more naive code for the above (subtracting rather than using an xor)
still isn't handled correctly due to the dagcombine getting confused.
Also, while here fix an issue spotted by inspection: we should have been
expanding the zero-undef variants to the normal variants when there is
an 'lzcnt' instruction. Do so, and test for this. We don't want to
generate unnecessary 'bsr' instructions.
These two changes fix some regressions in encoding and decoding
benchmarks. However, there is still a *lot* to be improve on in this
type of code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147244
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Chandler Carruth [Sat, 24 Dec 2011 10:55:42 +0000 (10:55 +0000)]
Cleanup this test a bit, sorting things and grouping them more clearly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147243
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Jakob Stoklund Olesen [Sat, 24 Dec 2011 04:17:01 +0000 (04:17 +0000)]
Fix Comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147238
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Akira Hatanaka [Sat, 24 Dec 2011 03:11:18 +0000 (03:11 +0000)]
Add MachineMemOperands to instructions generated in storeRegToStackSlot or
loadRegFromStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147235
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Akira Hatanaka [Sat, 24 Dec 2011 03:07:37 +0000 (03:07 +0000)]
Detect unaligned loads/stores that have been added for Mips64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147234
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Akira Hatanaka [Sat, 24 Dec 2011 03:05:43 +0000 (03:05 +0000)]
Test case for r147232.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147233
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Akira Hatanaka [Sat, 24 Dec 2011 02:59:27 +0000 (02:59 +0000)]
If target ABI is N64, LEA should be daddiu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147232
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Rafael Espindola [Sat, 24 Dec 2011 02:14:02 +0000 (02:14 +0000)]
Move x86 specific bits of the COFF writer to lib/Target/X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147231
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Rafael Espindola [Sat, 24 Dec 2011 01:53:13 +0000 (01:53 +0000)]
Define trivial destructor inline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147230
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Rafael Espindola [Sat, 24 Dec 2011 01:36:25 +0000 (01:36 +0000)]
Make GetRelocType pure virtual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147229
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Nick Lewycky [Fri, 23 Dec 2011 23:49:25 +0000 (23:49 +0000)]
Fix typo "infinte".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147226
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Nick Lewycky [Fri, 23 Dec 2011 18:41:31 +0000 (18:41 +0000)]
Move this test from date-name to feature-name, and port it to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147223
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