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Russell King [Sat, 5 Apr 2014 10:50:38 +0000 (11:50 +0100)]
ARM: l2c: tegra: convert to common l2c310 early resume functionality
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 01:17:21 +0000 (01:17 +0000)]
ARM: l2c: tegra: remove cache size override
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 28 Apr 2014 14:49:48 +0000 (15:49 +0100)]
ARM: l2c: sti: convert to generic l2c OF initialisation
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. We can remove the .init_machine as it becomes
the same as the generic version.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 12:18:02 +0000 (12:18 +0000)]
ARM: l2c: spear13xx: remove cache size override
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 28 Apr 2014 14:55:59 +0000 (15:55 +0100)]
ARM: l2c: socfpga: convert to generic l2c OF initialisation
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 12:16:36 +0000 (12:16 +0000)]
ARM: l2c: shmobile: remove cache size override
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 28 Apr 2014 14:27:59 +0000 (15:27 +0100)]
ARM: l2c: rockchip: convert to generic l2c OF initialisation
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. This also allows us to eliminate the
.init_machine function as this becomes the same as the generic version.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 14:53:54 +0000 (14:53 +0000)]
ARM: l2c: realview: improve commentry about the L2 cache requirements
Add better commentry about the L2 cache requirements on these platforms.
Unfortunately, the auxiliary control register is not pre-set to indicate
the correct cache parameters, so we have to manually program these.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 28 Apr 2014 14:41:08 +0000 (15:41 +0100)]
ARM: l2c: prima2: convert to generic l2c OF initialisation
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. Along with this change, we can delete l2x0.c
from prima2.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 12:14:18 +0000 (12:14 +0000)]
ARM: l2c: prima2: remove cache size override
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sekhar Nori [Tue, 22 Apr 2014 08:28:03 +0000 (13:58 +0530)]
ARM: l2c: AM43x: add L2 cache support
Add support for L2 cache controller (PL310) on AM437x SoC.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sekhar Nori [Tue, 22 Apr 2014 08:28:01 +0000 (13:58 +0530)]
ARM: l2c: omap2+: get rid of init call
Get rid of init call to initialize L2 cache. Instead use the init_early
machine hook. This helps in using the initialization routine across
SoCs without the need of ugly cpu_is_*() checks.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sekhar Nori [Tue, 22 Apr 2014 08:28:02 +0000 (13:58 +0530)]
ARM: l2c: omap2+: get rid of redundant cache replacement policy setting
L2 cache initialization for OMAP4 redundantly sets the cache policy to
Round-Robin. This is not needed since thats the PL310 default anyway.
Removing this reduces the number of platform specific aux control
settings.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 5 Apr 2014 09:57:44 +0000 (10:57 +0100)]
ARM: l2c: omap2: avoid reading directly from the L2 registers in platform code
Avoid reading directly from the L2 registers in platform code. The L2
code will have already saved the register values itself into the
l2x0_saved_regs structure, so platform code should just move these
values to where they're required.
This is safe because the L2x0 will have been initialised by an early
initcall, whereas the OMAP4 PM code is initialised late.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Thu, 10 Apr 2014 23:48:25 +0000 (00:48 +0100)]
ARM: l2c: omap2: remove explicit non-secure access bits
Since we now always enable NS access to the unlock registers, this can
be removed from OMAP4. Remove the NS access bit for the interrupt
registers from OMAP4 as well - nothing in the kernel accesses that yet,
and we can add it in core code when we have the need.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 17 Mar 2014 16:53:31 +0000 (16:53 +0000)]
ARM: l2c: omap2: remove cache size override
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 17 Mar 2014 16:35:46 +0000 (16:35 +0000)]
ARM: l2c: omap2: remove explicit SMI calls to enable L2 cache
Now that OMAP2 uses the write_sec method, we don't need to enable the L2
cache in OMAP2 specific code; this can be done via the normal mechanisms
in the L2C code. Remove the OMAP2 specific code.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 17:45:56 +0000 (17:45 +0000)]
ARM: l2c: omap2: implement new write_sec method
With the write_sec method, we no longer need to override the default
L2C disable method, and we no longer need the L2C set_debug method.
Both of these can be handled via the write_sec method.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 28 Apr 2014 14:27:59 +0000 (15:27 +0100)]
ARM: l2c: nomadik: convert to generic l2c OF initialisation
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. This also allows us to eliminate the
.init_machine function as it is identical to the generic version.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 12:10:16 +0000 (12:10 +0000)]
ARM: l2c: nomadik: remove cache size override
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 28 Apr 2014 14:44:47 +0000 (15:44 +0100)]
ARM: l2c: mvebu: convert to generic l2c OF initialisation
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 28 Apr 2014 14:48:14 +0000 (15:48 +0100)]
ARM: l2c: imx vf610: convert to generic l2c OF initialisation
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. Since the .init_irq method only calls
irqchip_init(), we can remove that too as the generic code will take
care of that.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 5 Apr 2014 10:55:03 +0000 (11:55 +0100)]
ARM: l2c: imx: convert to common l2c310 early resume functionality
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Fri, 28 Mar 2014 14:36:38 +0000 (14:36 +0000)]
ARM: l2c: imx: remove direct write to power control register
Now that we handle this in core code, we don't need platforms enabling
the low power modes directly.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 28 Apr 2014 14:34:11 +0000 (15:34 +0100)]
ARM: l2c: highbank: convert to generic l2c OF initialisation
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 17 Mar 2014 22:42:48 +0000 (22:42 +0000)]
ARM: l2c: highbank: remove explicit SMI call in L2 cache initialisation
Now that highbank uses the write_sec method, we don't need to enable
the L2 cache in SoC specific code; this can be done via the normal
mechanisms in the L2C code.
Checking with Rob Herring:
> > Can we kill the "highbank_smc1(0x102, 0x1);" here? That means
> > l2x0_of_init() will see the L2 cache disabled, and will try to enable
> > it via the write_sec hook, so it should do the right thing.
>
> Yes, that should work. You should be able to just call l2x0_of_init
> unconditionally. The condition was really to just avoid the smc on
> Midway which does get handled on h/w, but not if running virtualized.
So also drop the DT check too. I'm leaving the config check in place
so that if L2 is disabled, the write_sec hook can be optimised away.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 17:53:23 +0000 (17:53 +0000)]
ARM: l2c: highbank: implement new write_sec method
With the write_sec method, we no longer need to override the default L2C
disable method. This can be handled via the write_sec method instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 28 Apr 2014 14:54:08 +0000 (15:54 +0100)]
ARM: l2c: exynos: convert to generic l2c OF initialisation (and thereby fix it)
exynos was unconditionally calling the L2 cache initialisation from an
early_initcall. This breaks multiplatform kernels. Thankfully,
converting to generic l2c initialisation fixes this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 5 Apr 2014 10:45:34 +0000 (11:45 +0100)]
ARM: l2c: exynos: convert to common l2c310 early resume functionality
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 12:07:34 +0000 (12:07 +0000)]
ARM: l2c: exynos: remove cache size override
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 12:06:27 +0000 (12:06 +0000)]
ARM: l2c: cns3xxx: remove cache size override
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 28 Apr 2014 14:57:21 +0000 (15:57 +0100)]
ARM: l2c: berlin: convert to generic l2c OF initialisation
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. We can remove the explicit machine init too
as this becomes identical to the generic version.
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 28 Apr 2014 14:27:59 +0000 (15:27 +0100)]
ARM: l2c: bcm_5301x: convert to generic l2c OF initialisation
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. We can remove the explicit machine init too
as this becomes identical to the generic version.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 5 Apr 2014 10:39:57 +0000 (11:39 +0100)]
ARM: l2c: provide common PL310 early resume code
Provide a common assembly implementation for PL310 resume code. Certain
platforms need to re-initialise the L2C cache early as it may preserve
data across a S2RAM cycle, and therefore must be enabled along with the
L1 cache and MMU.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 28 Apr 2014 14:24:10 +0000 (15:24 +0100)]
ARM: l2c: add platform independent core L2 cache OF initialisation
Add a hook into the core ARM code to perform L2 cache initialisation
in a platform independent manner. Platforms still get to indicate
their auxiliary control register values and mask, but the
initialisation call will now be made from generic code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Thu, 10 Apr 2014 23:48:25 +0000 (00:48 +0100)]
ARM: l2c: always enable non-secure access to lockdown registers
Since we always write to these during the cache initialisation, it is
a good idea to always have the non-secure access bit set. Set it in
core code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Fri, 28 Mar 2014 14:22:04 +0000 (14:22 +0000)]
ARM: l2c: always enable low power modes
Always enable the L2C low power modes on L2C-310 R3P0 and newer parts.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 12:44:41 +0000 (12:44 +0000)]
ARM: l2c: remove platforms/SoCs setting early BRESP
Since we now automatically enable early BRESP in core L2C-310 code when
we detect a Cortex-A9, we don't need platforms/SoCs to set this bit
explicitly. Instead, they should seek to preserve the value of bit 30
in the auxiliary control register.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 15:39:09 +0000 (15:39 +0000)]
ARM: l2c: add automatic enable of early BRESP
The AXI bus protocol requires that a write response should only be
sent back to the master when the last write has been accepted. Early
BRESP allows the L2C-310 to send the write response as soon as the
store buffer accepts the write address.
Cortex-A9 processors can signal to the L2C-310 that they wish to be
notified early, and if this optimisation is enabled, the L2C-310 can
signal an early write response.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Fri, 28 Mar 2014 14:18:35 +0000 (14:18 +0000)]
ARM: l2c: move L2 cache register saving to a more sensible location
Move the L2 cache register saving to a more sensible location - after
the cache has been enabled, and fixups have been run. We move the
saving of the auxiliary control register into the ->save function as
well which makes everything operate in a sane and maintainable way.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 17 Mar 2014 12:59:08 +0000 (12:59 +0000)]
ARM: l2c: check that DT files specify the required "cache-unified" property
This is a required property, and should always be specified.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 20:52:25 +0000 (20:52 +0000)]
ARM: l2c: fix register naming
We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess. Split them out
into those which are L2C-310 specific and ones which refer to earlier
devices. Provide full auxiliary control register definitions.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 20:02:06 +0000 (20:02 +0000)]
ARM: l2c: implement L2C-310 erratum 752271 in core L2C code
Rather than having SoCs work around L2C erratum themselves, move them
into core code. This erratum affects the double linefill feature which
needs to be disabled for r3p0 to r3p1-50rel0.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 17:38:08 +0000 (17:38 +0000)]
ARM: l2c: provide generic hook to intercept writes to secure registers
When Linux is running in the non-secure world, any write to a secure
L2C register will generate an abort. Platforms normally have to call
firmware to work around this. Provide a hook for them to intercept
any L2C secure register write.
l2c_write_sec() avoids writes to secure registers which are already set
to the appropriate value, thus avoiding the overhead of needlessly
calling into the secure monitor.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 12:12:11 +0000 (12:12 +0000)]
ARM: l2c: move errata configuration options to arch/arm/mm/Kconfig
Move the L2C-310 errata configuration options to arch/arm/mm/Kconfig
along side the option which enables support for this device.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 23:26:24 +0000 (23:26 +0000)]
ARM: l2c: move way size calculation data into l2c_init_data
Move the way size calculation data (base of way size) out of the
switch statement into the provided initialisation data.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 23:07:07 +0000 (23:07 +0000)]
ARM: l2c: add decode for L2C-220 cache ways
Rather than assuming these are always 8-way, it can be decoded from the
auxillary register in the same manner as L2C-210.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 23:04:10 +0000 (23:04 +0000)]
ARM: l2c: move type string into l2c_init_data structure
Rather than decoding this from the ID register, store it in the
l2c_init_data structure. This simplifies things some more, and
allows us to better provide further details as to how we're
driving the cache. We print the cache ID value anyway should we
need to precisely identify the cache hardware.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 22:44:38 +0000 (22:44 +0000)]
ARM: l2c: remove obsolete l2x0 ops for non-OF init
non-OF initialisation has never been used with any cache controller
which isn't an ARM cache controller, so we can safely get rid of the
old (and buggy) l2x0_*-based operations structure.
This is also the last reference to:
- l2x0_clean_line()
- l2x0_inv_line()
- l2x0_flush_line()
- l2x0_flush_all()
- l2x0_clean_all()
- l2x0_inv_all()
- l2x0_inv_range()
- l2x0_clean_range()
- l2x0_flush_range()
- l2x0_enable()
- l2x0_resume()
so kill those functions too.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 19:14:13 +0000 (19:14 +0000)]
ARM: l2c: convert Broadcom L2C-310 to new code
The Broadcom L2C-310 devices use ARMs L2C-310 R2P3 or later. These
require no errata workarounds, and so we can directly call the l2c210
functions from their methods.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 21:29:28 +0000 (21:29 +0000)]
ARM: l2c: add L2C-220 specific handlers
The L2C-220 is different from the L2C-210 and L2C-310 in that every
operation is a background operation: this means we have to use
spinlocks to protect all operations, and we have to wait for every
operation to complete.
Should a second operation be attempted while a previous operation
is in progress, the response will be an imprecise abort.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 20:51:47 +0000 (20:51 +0000)]
ARM: l2c: use L2C-210 handlers for L2C-310 errata-less implementations
Where no errata affect the L2C-310 handlers, they are functionally
equivalent to L2C-210. Re-use the L2C-210 handlers for the L2C-310
part.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 19:08:11 +0000 (19:08 +0000)]
ARM: l2c: implement L2C-310 erratum 588369 as a method override
Implement L2C-310 erratum 588369 by overriding the invalidate range
and flush range methods in the outer_cache operations structure.
This allows us to sensibly contain the erratum code in one place
without affecting other locations/implemetations.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:18 +0000 (16:48 +0000)]
ARM: l2c: implement L2C-310 erratum 727915 as a method override
Implement L2C-310 erratum 727915 by overriding the flush_all method
in the outer_cache operations structure. This allows us to sensibly
contain the erratum code in one place without affecting other
locations or implementations.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 18:55:53 +0000 (18:55 +0000)]
ARM: l2c: add L2C-210 specific handlers
Add L2C-210 specific cache operation handlers. These are tailored to
the requirements of the L2C-210 cache controller, which doesn't
require any workarounds. We avoid using the way operations during
normal operation, which means we can avoid locking: the only time
we use the way operations are during initialisation, and when
disabling the cache.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:16 +0000 (16:48 +0000)]
ARM: l2c: move pl310_set_debug() into l2c-310 code
Move the pl310_set_debug() into the l2c-310 code area, and don't hide
it with ifdefs. Rename it to l2c310_set_debug().
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 22:49:59 +0000 (22:49 +0000)]
ARM: l2c: simplify l2x0 unlocking code
The l2x0 unlocking code is only called from l2x0_enable() now, so move
the logic entirely into that function and simplify it.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:13 +0000 (16:48 +0000)]
ARM: l2c: clean up save/resume functions
Rename the pl310 save/resume functions to have a l2c310 prefix - this
is it's official name. Use a local cached copy of the l2x0_base
virtual address, and also realise that many of the resume function
tails are the same as the enable functions, so make a call to the
enable function instead of duplicating that code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:11 +0000 (16:48 +0000)]
ARM: l2c: move and add ARM L2C-2x0/L2C-310 save/resume code to non-OF
Add the save/resume code hooks to the non-OF implementations as well.
There's no reason for the non-OF implementations to be any different
from the OF implementations.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:08 +0000 (16:48 +0000)]
ARM: l2c: clean up L2 cache initialisation messages
Make one of them purely "English", and the other purely technical.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:07 +0000 (16:48 +0000)]
ARM: l2c: implement fixups for L2 cache controller quirks/errata
Rather than putting quirk handling in __l2c_init(), move it out to a
separate function which individual implementations can specify. This
helps to localise the quirks to those implementations which require
them.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:59 +0000 (16:47 +0000)]
ARM: l2c: move aurora broadcast setup to enable function
Rather than having this hacked into the OF initialiation function, we
can handle this via the enable function instead. While here, clean
up that code and comments a little.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 17 Mar 2014 20:10:31 +0000 (20:10 +0000)]
ARM: l2c: only write the auxiliary control register if required
Avoid unnecessary writes to the auxiliary control register if the
register already contains the required value. This allows us to
avoid invoking the platforms secure monitor code unnecessarily.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Mon, 17 Mar 2014 17:15:02 +0000 (17:15 +0000)]
ARM: l2c: write auxctrl register before unlocking
We should write the auxillary control register before unlocking: the
write may be necessary to enable non-secure access to the lock
registers.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:57 +0000 (16:47 +0000)]
ARM: l2c: provide enable method
Providing an enable method gives L2 cache controllers a chance to do
special handling at enable time. This allows us to remove a hack in
l2x0_unlock() for Marvell Aurora L2 caches.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:06 +0000 (16:48 +0000)]
ARM: l2c: group implementation specific code together
Back in the mists of time, someone decided that it would be a good idea
to group like functions together - so all the save functions in one
place, all the resume functions in another, all the OF parsing functions
some place else.
This makes it difficult to get an overview on what a particular
implementation is doing - grouping an implementations specific functions
together makes more sense, because you can see what it's doing without
the clutter of other implementations.
Organise it according to implementation.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:04 +0000 (16:48 +0000)]
ARM: l2c: move l2c save function to __l2c_init()
There's no reason this functionality should be specific to DT, so move
it into the common initialisation function.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:55 +0000 (16:47 +0000)]
ARM: l2c: pass iomem address into data->save function
Pass the iomem address into this function so we don't have to keep
accessing it from a global.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:52 +0000 (16:47 +0000)]
ARM: l2c: clean up OF initialisation a bit
Rather than having a boolean and other tricks to disable some bits of
l2x0_init(), split this function into two parts: a common part shared
between OF and non-OF, and the non-OF part.
The common part can take a block of function pointers, and the cache
ID (to cope with Aurora's DT specified ID.) Eliminate the redundant
setting of l2x0_base in the OF case, moving it to the non-OF init
function.
This allows us to localise the OF-specific initialisation handling
from the non-OF handling.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:49 +0000 (16:47 +0000)]
ARM: l2c: add and use L2C revision constants
The revision namespace is specific to the L2 cache part, so don't name
these with generic identifiers, use a part specific identifier.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:14 +0000 (16:48 +0000)]
ARM: l2c: rename cache_wait_way()
cache_wait_way() is actually used to wait for a particular mask to
report clear; it's not really got much to do with cache ways at all.
Indeed, it gets used to wait for the C bit to clear on older caches.
Rename this with a more generic function name which better reflects
its purpose: l2c_wait_mask().
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:56 +0000 (16:47 +0000)]
ARM: l2c: provide generic helper for way-based operations
Provide a generic helper function for way based operations. These are
always background operations, and thus have to be waited for before a
new operation is commenced. This helper extracts that requirement from
several locations in the code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:50 +0000 (16:47 +0000)]
ARM: l2c: split out cache unlock code
Split the cache unlock code out of l2x0_unlock(). We want to be able
to re-use this functionality later.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 17:19:21 +0000 (17:19 +0000)]
ARM: l2c: provide generic function for calling set_debug method
Provide a generic function which always calls the set_debug method.
This will be used later in the series as some work-arounds require
that the debug register be written.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:54 +0000 (16:47 +0000)]
ARM: l2c: rename OF specific things, making l2x0_of_data available to all
Rename a few things to help distinguish their function(s):
l2x0_of_data -> l2c_init_data
setup -> of_parse
add of_ prefix to OF specific data
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:03 +0000 (16:48 +0000)]
ARM: l2c: tidy up l2x0_of_data declarations
Remove NULL initialisers, make these all __initconst structures, and
order their members in the same order as the structure declaration.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:48:01 +0000 (16:48 +0000)]
ARM: l2c: add helper for L2 cache controller DT IDs
Make it easier to declare L2 cache controller DT IDs by using a macro.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 13:14:38 +0000 (13:14 +0000)]
ARM: outer cache: add WARN_ON() to outer_disable()
Add WARN_ON() conditions to outer_disable() to ensure that its
requirements aren't violated.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sun, 16 Mar 2014 10:52:55 +0000 (10:52 +0000)]
ARM: outer cache: add documentation of outer cache functions
Add some documentation to cover the outer cache functions so that their
requirements can be better understood. Of particular note are the
flush_all() and disable() methods which must not be called except in
very specific circumstances.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 12:50:53 +0000 (12:50 +0000)]
ARM: l2c: remove unnecessary UL-suffix to mask values
They're u32, they're not unsigned long. The UL suffix is not required
here.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 19 Mar 2014 13:38:10 +0000 (13:38 +0000)]
ARM: l2c: omap2: remove ES1.0 support
Santosh says:
> But we should kill all of that since we long back decided to remove
> ES1.0 related code. The mach-omap code alreasy has removed the ES1.0
> compatibility so feel free to remove any specific ES1.0
> related stuff. That silicon is long dead.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:47 +0000 (16:47 +0000)]
ARM: l2c: avoid calling outer_flush_all() unnecessarily (Spear)
Spear calls outer_flush_all() from it's SMP bringup function. This
is potentially dangerous as the L2C set/way operations which implement
this don't take kindly to concurrent operations. Besides, there's
better solutions to this, as implemented on other platforms.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:45 +0000 (16:47 +0000)]
ARM: l2c: remove unnecessary call to outer_flush_all()
outer_disable() is defined to safely turn the L2 cache off without data
loss: this means that outer_flush_all() should never be called unless
you need to implement some special L2 cache disabling, and even then
only from your replacement L2 cache disable function.
Acked-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Sat, 15 Mar 2014 16:47:44 +0000 (16:47 +0000)]
ARM: l2c: remove outer_inv_all() method
No one ever calls this function anywhere in the kernel, so let's
completely remove it from the outer cache API and turn it into an
internal-only thing.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Linus Torvalds [Wed, 21 May 2014 21:42:02 +0000 (06:42 +0900)]
Linux 3.15-rc6
Linus Torvalds [Wed, 21 May 2014 20:55:12 +0000 (05:55 +0900)]
Merge branch 'merge' of git://git./linux/kernel/git/benh/powerpc
Pull two powerpc fixes from Ben Herrenschmidt:
"Here are a couple of fixes for 3.15. One from Anton fixes a nasty
regression I introduced when trying to fix a loss of irq_work whose
consequences is that we can completely lose timer interrupts on a
CPU... not pretty.
The other one is a change to our PCIe reset hook to use a firmware
call instead of direct config space accesses to trigger a fundamental
reset on the root port. This is necessary so that the FW gets a
chance to disable the link down error monitoring, which would
otherwise trip and cause subsequent fatal EEH error"
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
powerpc: irq work racing with timer interrupt can result in timer interrupt hang
powerpc/powernv: Reset root port in firmware
Linus Torvalds [Wed, 21 May 2014 20:40:13 +0000 (05:40 +0900)]
Merge branch 'for-linus' of git://git./linux/kernel/git/mason/linux-btrfs
Pull two btrfs fixes from Chris Mason:
"This has two fixes that we've been testing for 3.16, but since both
are safe and fix real bugs, it makes sense to send for 3.15 instead"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux-btrfs:
Btrfs: send, fix incorrect ref access when using extrefs
Btrfs: fix EIO on reading file after ioctl clone works on it
Linus Torvalds [Wed, 21 May 2014 20:38:51 +0000 (05:38 +0900)]
Merge branch 'for-linus' of git://git./linux/kernel/git/sage/ceph-client
Pull two ceph fixes from Sage Weil:
"The first patch fixes a problem when we have a page count of 0 for
sendpage which is triggered by zfs. The second fixes a bug in CRUSH
that was resolved in the userland code a while back but fell through
the cracks on the kernel side"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sage/ceph-client:
crush: decode and initialize chooseleaf_vary_r
libceph: fix corruption when using page_count 0 page in rbd
Linus Torvalds [Wed, 21 May 2014 20:36:07 +0000 (05:36 +0900)]
Merge tag 'xfs-for-linus-3.15-rc6' of git://oss.sgi.com/xfs/xfs
Pull xfs fixes from Dave Chinner:
"Code inspection of the XFS error number sign translations found a
bunch of issues, including returning incorrectly signed errors for
some data integrity operations.
These leak to userspace and result in applications not getting the
errors correctly reported. Hence they need fixing sooner rather than
later.
A couple of the bugs are in data integrity operations, a couple more
are in the new COLLAPSE_RANGE code. One of these came in through a
recent ext4 merge and so I had to update the base tree to 3.15-rc5
before fixing the issues"
* tag 'xfs-for-linus-3.15-rc6' of git://oss.sgi.com/xfs/xfs:
xfs: list_lru_init returns a negative error
xfs: negate xfs_icsb_init_counters error value
xfs: negate mount workqueue init error value
xfs: fix wrong err sign on xfs_set_acl()
xfs: fix wrong errno from xfs_initxattrs
xfs: correct error sign on COLLAPSE_RANGE errors
xfs: xfs_commit_metadata returns wrong errno
xfs: fix incorrect error sign in xfs_file_aio_read
xfs: xfs_dir_fsync() returns positive errno
Linus Torvalds [Wed, 21 May 2014 20:34:57 +0000 (05:34 +0900)]
Merge branch 'renameat2' of git://git./linux/kernel/git/mszeredi/vfs
Pull renameat2 arch support from Miklos Szeredi:
"I've collected architecture patches for the renameat2 syscall that
maintainers acked and/or asked me to queue.
This adds architecture support for the renameat2 syscall to m68k,
parisc, ia64 and through asm-generic to arc, arm64, c6x, hexagon,
metag, openrisc, score, tile, unicore32"
* 'renameat2' of git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/vfs:
scripts/checksyscalls.sh: Make renameat optional
asm-generic: Add renameat2 syscall
ia64: add renameat2 syscall
parisc: add renameat2 syscall
m68k: add renameat2 syscall
Linus Torvalds [Wed, 21 May 2014 19:29:39 +0000 (04:29 +0900)]
Merge tag 'iommu-fixes-v3.15-rc5' of git://git./linux/kernel/git/joro/iommu
Pull iommu fixes from Joerg Roedel:
"Three fixes for the AMD IOMMU driver:
- fix a locking issue around get_user_pages()
- fix two issues with device aliasing and exclusion range handling"
* tag 'iommu-fixes-v3.15-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/amd: fix enabling exclusion range for an exact device
iommu/amd: Take mmap_sem when calling get_user_pages
iommu/amd: Fix interrupt remapping for aliased devices
Linus Torvalds [Wed, 21 May 2014 19:28:21 +0000 (04:28 +0900)]
Merge tag 'stable/for-linus-3.15-rc5-tag' of git://git./linux/kernel/git/konrad/ibft
Pull iscsi_ibft fix from Konrad Rzeszutek Wilk:
"Fix iBFT regression on Broadcom NICs introduced in 3.2"
* tag 'stable/for-linus-3.15-rc5-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/ibft:
iscsi_ibft: Fix finding Broadcom specific ibft sign
Linus Torvalds [Wed, 21 May 2014 19:26:23 +0000 (04:26 +0900)]
Merge tag 'renesas-sh-drivers-for-v3.15' of git://git./linux/kernel/git/horms/renesas
Pull SH driver fix from Simon Horman:
"Compile drivers/sh/pm_runtime.c if ARCH_SHMOBILE_MULTI
This resolves a regression introduced in v3.14 by commit
bf98c1eac1d4
("ARM: Rename ARCH_SHMOBILE to ARCH_SHMOBILE_LEGACY")"
* tag 'renesas-sh-drivers-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
drivers: sh: compile drivers/sh/pm_runtime.c if ARCH_SHMOBILE_MULTI
Linus Torvalds [Wed, 21 May 2014 10:01:08 +0000 (19:01 +0900)]
Merge branch 'v4l_for_linus' of git://git./linux/kernel/git/mchehab/linux-media
Pull media fixes from Mauro Carvalho Chehab:
"Most of the changes are drivers fixes (rtl28xuu, fc2580, ov7670,
davinci, gspca, s5p-fimc and s5c73m3).
There is also a compat32 fix and one infoleak fixup at the media
controller"
* 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media:
[media] V4L2: fix VIDIOC_CREATE_BUFS in 64- / 32-bit compatibility mode
[media] V4L2: ov7670: fix a wrong index, potentially Oopsing the kernel from user-space
[media] media-device: fix infoleak in ioctl media_enum_entities()
[media] fc2580: fix tuning failure on 32-bit arch
[media] Prefer gspca_sonixb over sn9c102 for all devices
[media] media: davinci: vpfe: make sure all the buffers unmapped and released
[media] staging: media: davinci: vpfe: make sure all the buffers are released
[media] media: davinci: vpbe_display: fix releasing of active buffers
[media] media: davinci: vpif_display: fix releasing of active buffers
[media] media: davinci: vpif_capture: fix releasing of active buffers
[media] s5p-fimc: Fix YUV422P depth
[media] s5c73m3: Add missing rename of v4l2_of_get_next_endpoint() function
[media] rtl28xxu: silence error log about disabled rtl2832_sdr module
[media] rtl28xxu: do not hard depend on staging SDR module
Linus Torvalds [Wed, 21 May 2014 10:00:09 +0000 (19:00 +0900)]
Merge tag 'staging-3.15-rc6' of git://git./linux/kernel/git/gregkh/staging
Pull staging driver fixes from Greg KH:
"Here are five staging driver fixes for 3.15-rc6 that resolve some
reported issues. They are for the imx and rtl8723au drivers"
* tag 'staging-3.15-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging:
staging: rtl8723au: Do not reset wdev->iftype in netdev_close()
staging: rtl8723au: Use correct pipe type for USB interrupts
imx-drm: imx-tve: correct DDC property name to 'ddc-i2c-bus'
imx-drm: imx-drm-core: skip components whose parent device is disabled
imx-drm: imx-drm-core: fix imx_drm_encoder_get_mux_id
Linus Torvalds [Wed, 21 May 2014 09:59:25 +0000 (18:59 +0900)]
Merge tag 'driver-core-3.15-rc6' of git://git./linux/kernel/git/gregkh/driver-core
Pull driver core fixes from Greg KH:
"Here are two driver core (well, sysfs) fixes for 3.15-rc6 that resolve
some reported issues and a regression from 3.13"
* tag 'driver-core-3.15-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core:
sysfs: make sure read buffer is zeroed
kernfs, sysfs, cgroup: restrict extra perm check on open to sysfs
Linus Torvalds [Wed, 21 May 2014 09:57:25 +0000 (18:57 +0900)]
Merge tag 'pci-v3.15-fixes-2' of git://git./linux/kernel/git/helgaas/pci
Pull PCI fixes from Bjorn Helgaas:
"These are fixes for an SHPCHP hotplug regression, a "wait for pending
transaction" problem (used in device reset paths), and an email
address update.
PCI device hotplug:
- Fix SHPCHP bus speed mismatch issue (Marcel Apfelbaum)
Miscellaneous:
- Fix pci_wait_for_pending_transaction() (Gavin Shan)
- Update email address (Ben Hutchings)"
* tag 'pci-v3.15-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
PCI: Wrong register used to check pending traffic
PCI: shpchp: Check bridge's secondary (not primary) bus speed
PCI: Update my email address
Linus Torvalds [Wed, 21 May 2014 09:56:35 +0000 (18:56 +0900)]
Merge tag 'random_for_linus' of git://git./linux/kernel/git/tytso/random
Pull /dev/random fix from Ted Ts'o:
"This fixes a BUG_ON-causing regression that was introduced during the
last merge window"
* tag 'random_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/random:
random: fix BUG_ON caused by accounting simplification
Linus Torvalds [Wed, 21 May 2014 09:55:17 +0000 (18:55 +0900)]
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework fixes from Mike Turquette:
"Clock framework and driver fixes, all of which fix user-visible
regressions.
As usual most fixes are for platform-specific clock drivers, but there
are also two fixes to the clk core after recent changes to the way
that clock unregistration is handled"
* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
clk: tegra: Fix wrong value written to PLLE_AUX
clk: shmobile: clk-mstp: change to using clock-indices
clk: Fix slab corruption in clk_unregister()
clk: Fix double free due to devm_clk_register()
clk: socfpga: fix clock driver for 3.15
clk: divider: Fix best div calculation for power-of-two and table dividers
clk: bcm281xx: don't use unnamed structs or unions
Linus Torvalds [Wed, 21 May 2014 09:53:55 +0000 (18:53 +0900)]
Merge tag 'spi-v3.15-rc5' of git://git./linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown:
"A few core fixes around outlying cases here, nothing that should
affect most users but useful fixes. The diffstat is rather larger
than one might hope due some simple code motion in the fix for
!CONFIG_DMA, the actual meaningful change is much smaller.
- Fix handling of unsupported dual and quad mode support on slave
registration so that drivers that can degrade gracefully do so,
preventing regressions for drivers this is added.
- Fix build in !CONFIG_DMA cases following addition of generic DMA
mapping support.
- Fix error handling for queue creation which due to wider kernel
changes can be triggered more easily.
- A couple of driver specific fixes"
* tag 'spi-v3.15-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi/pxa2xx: Prevent DMA from transferring too many bytes
spi: core: Don't destroy master queue if we fail to create it
spi: qup: Fix return value checking for pm_runtime_get_sync()
spi: core: Protect DMA code by #ifdef CONFIG_HAS_DMA
spi: core: Ignore unsupported Dual/Quad Transfer Mode bits