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Jake Ehrlich [Thu, 12 Apr 2018 00:40:50 +0000 (00:40 +0000)]
Revert "[llvm-objcopy] Switch over to using TableGen for parsing arguments"
TableGen seems to work differently on windows. I'll need to revert this
This reverts commit
7a153ddea067b24da59f6a66c733d79205969501.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329867
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Michael Zolotukhin [Wed, 11 Apr 2018 23:37:53 +0000 (23:37 +0000)]
Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time.
This reapplies commit r329644.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329865
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Michael Zolotukhin [Wed, 11 Apr 2018 23:37:37 +0000 (23:37 +0000)]
[SSAUpdaterBulk] Fix linux bootstrap/sanitizer failures: explicitly specify order of evaluation.
The standard says that the order of evaluation of an expression
s[x] = foo()
is unspecified. In our case, we first create an empty entry in the map,
then call foo(), then store its return value to the created entry. The
problem is that foo uses the map as a cache, so if it finds that there
is an entry in the map, it stops computation. This change explicitly
sets the order, thus fixing this heisenbug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329864
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Jake Ehrlich [Wed, 11 Apr 2018 23:37:03 +0000 (23:37 +0000)]
[llvm-objcopy] Switch over to using TableGen for parsing arguments
Swithces from using the command line library to using TableGen. This will allow
llvm-strip to exist and allow refinements of the command line syntax.
Differential Revision: https://reviews.llvm.org/D44236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329863
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Simon Pilgrim [Wed, 11 Apr 2018 23:24:38 +0000 (23:24 +0000)]
[X86] Remove unused itinerary argument from FMA3/FMA4/XOP instructions. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329862
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Weiming Zhao [Wed, 11 Apr 2018 23:09:20 +0000 (23:09 +0000)]
Add missing vtable anchors
Summary: This patch adds anchor() for MemoryBuffer, raw_fd_ostream, RTDyldMemoryManager, SectionMemoryManager, etc.
Reviewers: jlebar, eli.friedman, dblaikie
Reviewed By: dblaikie
Subscribers: mehdi_amini, mgorny, dblaikie, weimingz, llvm-commits
Differential Revision: https://reviews.llvm.org/D45244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329861
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Simon Pilgrim [Wed, 11 Apr 2018 23:08:30 +0000 (23:08 +0000)]
X86FoldTableEntry - avoid unnecessary std::string creation. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329860
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whitequark [Wed, 11 Apr 2018 22:40:42 +0000 (22:40 +0000)]
[LLVM-C] Add LLVMGetHostCPU{Name,Features}.
Without these functions it's hard to create a TargetMachine for
Orc JIT that creates efficient native code.
It's not sufficient to just expose LLVMGetHostCPUName(), because
for some CPUs there's fewer features actually available than
the CPU name indicates (e.g. AVX might be missing on some CPUs
identified as Skylake).
Differential Revision: https://reviews.llvm.org/D44861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329856
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Simon Pilgrim [Wed, 11 Apr 2018 22:24:48 +0000 (22:24 +0000)]
Don't repeatedly evaluate size() in the for loop. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329853
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Nemanja Ivanovic [Wed, 11 Apr 2018 21:25:44 +0000 (21:25 +0000)]
[PowerPC] Fix condition for 64-bit rotate when replacing r+r instr with r+i
This patch fixes https://bugs.llvm.org/show_bug.cgi?id=37039
The condition only covers one of the two 64-bit rotate instructions. This just
adds the second (RLDICLo).
Patch by Josh Stone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329852
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Puyan Lotfi [Wed, 11 Apr 2018 20:29:32 +0000 (20:29 +0000)]
Attempting to work around a non-determinism issue.
The main thing that matters with this test is that the COPYs
are moved together not where the REG_SEQUENCES are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329850
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Yonghong Song [Wed, 11 Apr 2018 20:24:52 +0000 (20:24 +0000)]
bpf: signal error instead of silent drop for certain invalid asm insn
Currently, an invalid asm insn, either in an asm file or
in an inline asm format, might be silently dropped. This patch
fixed two places where this may happen by
signaling the error so user knows what goes wrong.
The following is an example to demonstrate error messages:
-bash-4.2$ cat t.c
int test(void *ctx) {
#if defined(NO_ERROR)
asm volatile("r0 = *(u16 *)skb[%0]" : : "i"(2));
#elif defined(ERROR_1)
asm volatile("r20 = *(u16 *)skb[%0]" : : "i"(2));
#elif defined(ERROR_2)
asm volatile("r0 = *(u16 *)(r1 + ?)" : :);
#endif
return 0;
}
-bash-4.2$ cat run.sh
for macro in NO_ERROR ERROR_1 ERROR_2; do
echo "===== compile for macro" $macro
clang -D${macro} -O2 -target bpf -emit-llvm -S t.c
echo "==llc=="
llc -march=bpf -filetype=obj t.ll
done
-bash-4.2$ ./run.sh
===== compile for macro NO_ERROR
==llc==
===== compile for macro ERROR_1
==llc==
<inline asm>:1:2: error: invalid register/token name
r20 = *(u16 *)skb[2]
^
note: !srcloc = 135
===== compile for macro ERROR_2
==llc==
<inline asm>:1:21: error: unexpected token
r0 = *(u16 *)(r1 + ?)
^
note: !srcloc = 210
-bash-4.2$
Acked-by: Alexei Starovoitov <ast@kernel.org>
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329849
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Gabor Buella [Wed, 11 Apr 2018 20:01:57 +0000 (20:01 +0000)]
[X86] Describe wbnoinvd instruction
Similar to the wbinvd instruction, except this
one does not invalidate caches. Ring 0 only.
The encoding matches a wbinvd instruction with
an F3 prefix.
Reviewers: craig.topper, zvi, ashlykov
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D43816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329847
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Daniel Neilson [Wed, 11 Apr 2018 19:46:02 +0000 (19:46 +0000)]
[DSE] Add tests for atomic memory intrinsics (NFC)
Summary:
These tests show that DSE currently does nothing with the atomic memory
intrinsics. Future work will teach DSE how to simplify these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329845
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David Blaikie [Wed, 11 Apr 2018 18:49:37 +0000 (18:49 +0000)]
Rename *CommandFlags.def to *CommandFlags.inc
These aren't the .def style files used in LLVM that require a macro
defined before their inclusion - they're just basic non-modular includes
to stamp out command line flag variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329840
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Daniel Neilson [Wed, 11 Apr 2018 18:43:10 +0000 (18:43 +0000)]
[DSE] Regenerate tests with update_test_checks.py (NFC)
Summary:
In preparation for a future commit, this regenerates the test checks for
test/Transforms/DeadStoreElimination/OverwriteStoreBegin.ll
test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329839
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Peter Collingbourne [Wed, 11 Apr 2018 18:24:03 +0000 (18:24 +0000)]
CodeGen: Don't try to canonicalize Unix-style paths in CodeView debug info.
Most importantly, we should not replace slashes with backslashes
because that would invalidate the path.
Differential Revision: https://reviews.llvm.org/D45473
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329838
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Simon Pilgrim [Wed, 11 Apr 2018 18:23:01 +0000 (18:23 +0000)]
[X86][Atom] Convert Atom scheduler model to SchedRW (PR32431)
Atom is the only x86 target that still uses schedule itineraries, if we can remove this then we can begin the work on removing x86 itineraries. I've also found that it will help with PR36550.
I've focussed on matching the existing model as closely as possible (relying on the schedule tests), PR36895 indicated a lot of these were incorrect but we can just as easily fix these after this patch as before. Hopefully we can get llvm-exegesis to help here,
There are a few instructions that rely on itinerary scheduling (mainly push/pop/return) of multiple resource stages, but I don't think any of these are show stoppers.
There are also a few codegen changes that seem related to the post-ra scheduler acting a little differently, I haven't tracked these down but they don't seem critical.
NOTE: I don't have access to any Atom hardware, so this hasn't been tested in the wild.
Differential Revision: https://reviews.llvm.org/D45486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329837
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Andrea Di Biagio [Wed, 11 Apr 2018 18:05:23 +0000 (18:05 +0000)]
[llvm-mca] Let the Scheduler notify dispatch stall events caused by the lack of scheduling resources.
This patch moves part of the logic that notifies dispatch stall events from the
DispatchUnit to the Scheduler.
The main goal of this patch is to remove (yet another) dependency between the
DispatchUnit and the Scheduler. Before this patch, the DispatchUnit had to know
about `Scheduler::Event` and how to classify stalls due to the lack of scheduling
resources. This patch removes that knowledge and simplifies the logic in
DispatchUnit::checkScheduler.
This is another change done in preparation for the work to fix PR36663.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329835
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Simon Pilgrim [Wed, 11 Apr 2018 18:05:17 +0000 (18:05 +0000)]
[X86] Generalize X86PadShortFunction to work with TargetSchedModel
Pre-commit for D45486, don't rely on itinerary scheduler model to determine latencies for padding, use the generic TargetSchedModel::computeInstrLatency call.
Also, replace hard coded (atom specific) 2*uop creation per padding cycle with a version based on the scheduler model's issue width.
Differential Revision: https://reviews.llvm.org/D45486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329834
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Artem Belevich [Wed, 11 Apr 2018 17:51:33 +0000 (17:51 +0000)]
[NVPTX] Removed 'satom' feature which is no longer used.
Differential Revision: https://reviews.llvm.org/D45061
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329830
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Artem Belevich [Wed, 11 Apr 2018 17:51:19 +0000 (17:51 +0000)]
[NVPTX, CUDA] Improved feature constraints on NVPTX target builtins.
When NVPTX TARGET_BUILTIN specifies sm_XX or ptxYY as required feature,
consider those features available if we're compiling for GPU >= sm_XX or have
enabled PTX version >= ptxYY.
Differential Revision: https://reviews.llvm.org/D45061
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329829
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Tim Renouf [Wed, 11 Apr 2018 17:18:36 +0000 (17:18 +0000)]
[AMDGPU] Ensure there are enough registers for wave dispatch
Summary:
This fixes the number of SGPRs and VGPRs in the *_RSRC1 register to
allow for registers set up in wave dispatch, even if those registers are
not used in the shader.
Re-landed after noticing that the buildbot failure from 329808 seemed to
be unrelated.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45503
Change-Id: I6575f0e0d2a528d1319d0b289f0ebe4510fa5771
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329826
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Daniel Neilson [Wed, 11 Apr 2018 16:50:04 +0000 (16:50 +0000)]
[DSE] Regenerate tests with update_test_checks.py (NFC)
Summary:
In preparation for a future commit, this regenerates the test checks for
test/Transforms/DeadStoreElimination/simple.ll
test/Transforms/DeadStoreElimination/memintrinsics.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329824
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Reid Kleckner [Wed, 11 Apr 2018 16:03:07 +0000 (16:03 +0000)]
[FastISel] Disable local value sinking by default
This is causing compilation timeouts on code with long sequences of
local values and calls (i.e. foo(1); foo(2); foo(3); ...). It turns out
that code coverage instrumentation is a great way to create sequences
like this, which how our users ran into the issue in practice.
Intel has a tool that detects these kinds of non-linear compile time
issues, and Andy Kaylor reported it as PR37010.
The current sinking code scans the whole basic block once per local
value sink, which happens before emitting each call. In theory, local
values should only be introduced to be used by instructions between the
current flush point and the last flush point, so we should only need to
scan those instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329822
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Sanjay Patel [Wed, 11 Apr 2018 15:57:18 +0000 (15:57 +0000)]
[InstCombine] limit X - (cast(-Y) --> X + cast(Y) with hasOneUse()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329821
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Paul Robinson [Wed, 11 Apr 2018 15:14:05 +0000 (15:14 +0000)]
[DWARFv5] Fuss with asm syntax for conveying MD5 checksum.
Previously the MD5 option of the .file directive provided the checksum
as a quoted hex string; now it's a normal hex number with 0x prefix,
same as the .octa directive accepts.
Differential Revision: https://reviews.llvm.org/D45459
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329820
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Petar Jovanovic [Wed, 11 Apr 2018 15:12:32 +0000 (15:12 +0000)]
[MIPS GlobalISel] Select add i32, i32
Add the minimal support necessary to lower a function that returns the
sum of two i32 values.
Support argument/return lowering of i32 values through registers only.
Add tablegen for regbankselect and instructionselect.
Patch by Petar Avramovic.
Differential Revision: https://reviews.llvm.org/D44304
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329819
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Haicheng Wu [Wed, 11 Apr 2018 15:09:49 +0000 (15:09 +0000)]
[SLP] update a test case. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329818
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Yaxun Liu [Wed, 11 Apr 2018 14:46:15 +0000 (14:46 +0000)]
[AMDGPU] Fix lowering enqueue_kernel
Two issues were fixed:
runtime has difficulty to allocate memory for an external symbol of a
kernel and set the address of the external symbol, therefore make the runtime
handle of an enqueued kernel an ordinary global variable. Runtime only needs
to store the address of the loaded kernel to the handle and has verified
that this approach works.
handle the situation where __enqueue_kernel* gets inlined therefore
the enqueued kernel may be used through a constant expr instead
of an instruction.
Differential Revision: https://reviews.llvm.org/D45187
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329815
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Andrea Di Biagio [Wed, 11 Apr 2018 14:35:23 +0000 (14:35 +0000)]
Revert "[llvm-mca][CMake] Remove unused libraries from set LLVM_LINK_COMPONENTS"
It caused a buildbot failure (clang-ppc64le-linux-multistage - build #6424)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329812
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Tim Renouf [Wed, 11 Apr 2018 14:27:41 +0000 (14:27 +0000)]
Revert "[AMDGPU] Ensure there are enough registers for wave dispatch"
This reverts 329808. That change caused a report of a failure in
test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir that I didn't see. I suspect
it is an expensive-check-only error.
Change-Id: I8133f26f15e7d5ec2b09c687c12cd70e918461b0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329811
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Sander de Smalen [Wed, 11 Apr 2018 14:10:37 +0000 (14:10 +0000)]
[AArch64][AsmParser] Split index parsing from vector list.
Summary:
Place parsing of a vector index into a separate function to reduce
duplication, since the code is duplicated in both the parsing of a
Neon vector register operand and a Neon vector list.
This is patch [2/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329809
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Tim Renouf [Wed, 11 Apr 2018 14:02:41 +0000 (14:02 +0000)]
[AMDGPU] Ensure there are enough registers for wave dispatch
Summary:
This fixes the number of SGPRs and VGPRs in the *_RSRC1 register to
allow for registers set up in wave dispatch, even if those registers are
not used in the shader.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45503
Change-Id: I6575f0e0d2a528d1319d0b289f0ebe4510fa5771
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329808
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Andrea Di Biagio [Wed, 11 Apr 2018 13:52:42 +0000 (13:52 +0000)]
[llvm-mca][CMake] Remove unused libraries from set LLVM_LINK_COMPONENTS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329807
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Simon Pilgrim [Wed, 11 Apr 2018 13:49:19 +0000 (13:49 +0000)]
[X86] Add variable shuffle schedule classes
Split variable index shuffles from immediate index shuffles
WriteFVarShuffle - variable 'in-lane' shuffles (VPERMILPS/VPERMIL2PS etc.)
WriteVarShuffle - variable 'in-lane' shuffles (PSHUFB/VPPERM etc.)
WriteFVarShuffle256 - variable 'cross-lane' shuffles (VPERMPS etc.)
WriteVarShuffle256 - variable 'cross-lane' shuffles (VPERMD etc.)
Differential Revision: https://reviews.llvm.org/D45404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329806
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Francis Visoiu Mistrih [Wed, 11 Apr 2018 13:37:25 +0000 (13:37 +0000)]
[AArch64] Add test case for r329797
Forgot to add a test case in the previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329805
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Simon Pilgrim [Wed, 11 Apr 2018 13:15:36 +0000 (13:15 +0000)]
[X86][SSE] Tweak cmpps schedule test so that it works properly with just sse1
movhps/movlps test are still broken so we can't disable sse2 yet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329802
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Dmitry Preobrazhensky [Wed, 11 Apr 2018 13:13:30 +0000 (13:13 +0000)]
[AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32
See bug 36845: https://bugs.llvm.org/show_bug.cgi?id=36845
Differential Revision: https://reviews.llvm.org/D45443
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329801
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Francis Visoiu Mistrih [Wed, 11 Apr 2018 12:36:55 +0000 (12:36 +0000)]
[AArch64] Fix regression after r329691
In r329691, we would choose FP even if the offset wouldn't fit, just
because the offset is smaller than the one from BP. This made many
accesses through FP need to scavenge a register, which resulted in
slower and bigger code for no good reason.
This patch now always picks the offset that fits first, even if FP is
preferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329797
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Andrea Di Biagio [Wed, 11 Apr 2018 12:31:44 +0000 (12:31 +0000)]
[llvm-mca] Minor code cleanup. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329796
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Andrea Di Biagio [Wed, 11 Apr 2018 12:12:53 +0000 (12:12 +0000)]
[llvm-mca] Renamed BackendStatistics to RetireControlUnitStatistics.
Also, removed flag -verbose in favor of flag -retire-stats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329794
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Andrea Di Biagio [Wed, 11 Apr 2018 11:37:46 +0000 (11:37 +0000)]
[llvm-mca] Move the logic that prints scheduler statistics from BackendStatistics to its own view.
Added flag -scheduler-stats to print scheduler related statistics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329792
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Artur Gainullin [Wed, 11 Apr 2018 10:29:37 +0000 (10:29 +0000)]
Eliminate a bitwise 'not' op of 'not' min/max by inverting the min/max.
Bitwise 'not' of the min/max could be eliminated in the pattern:
%notx = xor i32 %x, -1
%cmp1 = icmp sgt[slt/ugt/ult] i32 %notx, %y
%smax = select i1 %cmp1, i32 %notx, i32 %y
%res = xor i32 %smax, -1
https://rise4fun.com/Alive/lCN
Reviewers: spatel
Reviewed by: spatel
Subscribers: a.elovikov, llvm-commits
Differential Revision: https://reviews.llvm.org/D45317
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329791
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Sjoerd Meijer [Wed, 11 Apr 2018 09:28:04 +0000 (09:28 +0000)]
[ARM] FP16 VSEL codegen
This is a follow up of rL327695 to instruction select more variants of VSELGT
and VSELGE, for which it is necessary to custom lower SELECT.
More work is required in this area, which will be addressed soon:
- more variants need to be regression tested, but this depends on the next point.
- first LowerConstantFP need to be adjusted for fp16 values.
Differential Revision: https://reviews.llvm.org/D45205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329788
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Clement Courbet [Wed, 11 Apr 2018 07:39:00 +0000 (07:39 +0000)]
[Build][NFC] Split off libpfm detection to a separate module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329783
91177308-0d34-0410-b5e6-
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Sander de Smalen [Wed, 11 Apr 2018 07:36:10 +0000 (07:36 +0000)]
[AArch64][AsmParser] Unify code for parsing Neon/SVE vectors.
Summary:
Merged 'tryMatchVectorRegister' (specific to Neon) and
'tryParseSVERegister' into a single 'tryParseVectorRegister' function, and
created a generic 'parseVectorKind()' function that returns the #Elements
and ElementWidth of a vector suffix. This reduces the duplication of
this functionality between two the vector implementations.
This is patch [1/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: fhahn
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329782
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Clement Courbet [Wed, 11 Apr 2018 07:32:43 +0000 (07:32 +0000)]
[llvm-exegesis] Add a flag to disable libpfm even if present.
Summary: Fixes PR37053.
Reviewers: uabelho, gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D45436
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329781
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Petr Hosek [Wed, 11 Apr 2018 05:18:03 +0000 (05:18 +0000)]
[CMake][runtimes] Process common options in runtimes build
This was removed in D39932 but turned out this is actually needed
because runtimes such as compiler-rt and libc++ rely on common options
processing for setting certain flags such as -ffunction-sections and
-fdata-sections.
Differential Revision: https://reviews.llvm.org/D45507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329778
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 11 Apr 2018 04:55:04 +0000 (04:55 +0000)]
[X86] Remove 128/256-bit masked pmaddubsw and pmaddwd intrinsics. Replace 512-bit masked intrinsic with unmasked intrinsic and a select.
The 128/256-bit versions were no longer used by clang. It uses the legacy SSE/AVX2 version and a select. The 512-bit was changed to the same for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329774
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Craig Topper [Wed, 11 Apr 2018 01:09:10 +0000 (01:09 +0000)]
[X86] In X86FlagsCopyLowering, when rewriting a memory setcc we need to emit an explicit MOV8mr instruction.
Previously the code only knew how to handle setcc to a register.
This should fix a crash in the chromium build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329771
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Craig Topper [Wed, 11 Apr 2018 01:05:32 +0000 (01:05 +0000)]
[X86] Switch a test from grep to FileCheck. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329769
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Sriraman Tallam [Tue, 10 Apr 2018 23:32:36 +0000 (23:32 +0000)]
Simplification of libcall like printf->puts must check for RtLibUseGOT metadata.
With -fno-plt, for example, calls to printf when getting converted to puts
still use the PLT. This patch checks for the metadata "RtLibUseGOT" and
annotates the declaration with the right attributes.
Differential Revision: https://reviews.llvm.org/D45180
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329768
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Rui Ueyama [Tue, 10 Apr 2018 22:58:08 +0000 (22:58 +0000)]
Use contains_lower() instead of find_lower() != StringRef::npos. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329767
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Sriraman Tallam [Tue, 10 Apr 2018 22:50:05 +0000 (22:50 +0000)]
GOTPCREL references must always use RIP.
With -fno-plt, global value references can use GOTPCREL and RIP must be used.
Differential Revision: https://reviews.llvm.org/D45460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329765
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Marek Olsak [Tue, 10 Apr 2018 22:48:23 +0000 (22:48 +0000)]
AMDGPU: enable 128-bit for local addr space under an option
Author: Samuel Pitoiset
ds_read_b128 and ds_write_b128 have been recently enabled
under the amdgpu-ds128 option because the performance benefit
is unclear.
Though, using 128-bit loads/stores for the local address space
appears to introduce regressions in tessellation shaders. Not
sure what is broken, but as ds_read_b128/ds_write_b128 are not
enabled by default, just introduce a global option and enable
128-bit only if requested (until it's fixed/used correctly).
v2: - fix regressions in merge-stores.ll and multiple_tails.ll
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329764
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Galina Kistanova [Tue, 10 Apr 2018 22:07:29 +0000 (22:07 +0000)]
Disable flaky tests till they get fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329763
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Geoff Berry [Tue, 10 Apr 2018 21:43:03 +0000 (21:43 +0000)]
[AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass.
Summary:
When inserting MOVs to avoid Falkor HWPF collisions, the non-base
register operand of load instructions (e.g. a register offset) was not
being considered live, so it could potentially have been used as a
scratch register, clobbering the actual offset value.
Reviewers: mcrosier
Subscribers: rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329761
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Sanjay Patel [Tue, 10 Apr 2018 20:42:39 +0000 (20:42 +0000)]
[CVP] simplify phi with constant incoming values that match common variable edge values
This is based on an example that was recently posted on llvm-dev:
void *propagate_null(void* b, int* g) {
if (!b) {
return 0;
}
(*g)++;
return b;
}
https://godbolt.org/g/xYk3qG
The original code or constant propagation in other passes has obscured the fact
that the phi can be removed completely.
Differential Revision: https://reviews.llvm.org/D45448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329755
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Daniel Neilson [Tue, 10 Apr 2018 20:23:50 +0000 (20:23 +0000)]
[Verifier] Refactor duplicate code for atomic mem intrinsic verification (NFC)
Summary:
The verification rules for the intrinsics for atomic memcpy, atomic memmove,
and atomic memset are basically code clones. This change merges their verification
rules into a single block to remove duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329753
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Steven Wu [Tue, 10 Apr 2018 20:16:35 +0000 (20:16 +0000)]
[MachO] Emit Weak ReadOnlyWithRel to ConstDataSection
Summary:
Darwin dynamic linker can handle weak symbols in ConstDataSection.
ReadonReadOnlyWithRel symbols should be emitted in ConstDataSection
instead of normal DataSection.
rdar://problem/
39298457
Reviewers: dexonsmith, kledzik
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329752
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Daniel Neilson [Tue, 10 Apr 2018 19:51:44 +0000 (19:51 +0000)]
[IR] Refactor memset inst classes (NFC)
Summary:
A simple refactor to remove duplicate code in the definitions of
MemSetInst, AtomicMemSetInst, and AnyMemSetInst. Introduce a
templated base class that contains all of the methods unique to
a memset intrinsic, and derive these three classes from that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329747
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Jessica Paquette [Tue, 10 Apr 2018 19:46:43 +0000 (19:46 +0000)]
Recommit r329716 "Add missing nullptr check before getSection() to AArch64MachObjectWriter::recordRelocation"
This commit fixes the bot failures that were coming up before with r329716.
The fix was to move the check for "isInSection()" inside of the if condition
and emit the error there instead of waiting to get past the unreachable statement.
This should work in debug and release builds now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329746
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Daniel Neilson [Tue, 10 Apr 2018 19:23:11 +0000 (19:23 +0000)]
[IR] Refactor memtransfer inst classes (NFC)
Summary:
A simple refactor to remove duplicate code in the definitions of
MemTransferInst, AtomicMemTransferInst, and AnyMemTransferInst.
Introduce a templated base class that contains all of the methods
unique to a memory transfer intrinsic, and derive these three
classes from that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329744
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Amara Emerson [Tue, 10 Apr 2018 19:01:58 +0000 (19:01 +0000)]
[AArch64] Fix isel failure when BUILD_PAIR nodes are left over.
rdar://
39175175
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329743
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Gabor Buella [Tue, 10 Apr 2018 18:59:13 +0000 (18:59 +0000)]
[X86] Split up -march=icelake to -client & -server
Reviewers: craig.topper, zvi, echristo
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D45055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329742
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Sanjay Patel [Tue, 10 Apr 2018 18:38:19 +0000 (18:38 +0000)]
[InstSimplify] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329736
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Craig Topper [Tue, 10 Apr 2018 18:21:04 +0000 (18:21 +0000)]
[X86] Change the name string for the newly add DF flag register to 'dirflag' to match the clobber name supported by clang for MS inline assembly.
This should fix the failure found by Chromium reported here https://bugs.chromium.org/p/chromium/issues/detail?id=831158
The test case will be added in clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329734
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Aaron Smith [Tue, 10 Apr 2018 18:12:49 +0000 (18:12 +0000)]
[DebugInfoPDB] Add missing test for findSymbolByRVA and findSymbolByAddr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329733
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Sanjay Patel [Tue, 10 Apr 2018 18:10:14 +0000 (18:10 +0000)]
[llvm-mca] reorder text
On 2nd reading, putting the C example after the bit about
multiple regions makes this flow better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329732
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Robert Widmann [Tue, 10 Apr 2018 18:10:10 +0000 (18:10 +0000)]
[LLVM-C] Add Missing 'break's in InlineAsm bindings
Summary: Noticed by Andrea Di Biagio while reviewing r329369
Reviewers: whitequark, harlanhaskins
Reviewed By: harlanhaskins
Subscribers: llvm-commits, abergmeier-dsfishlabs
Differential Revision: https://reviews.llvm.org/D45496
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329731
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Sanjay Patel [Tue, 10 Apr 2018 17:56:24 +0000 (17:56 +0000)]
[llvm-mca] fix formatting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329729
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Jessica Paquette [Tue, 10 Apr 2018 17:53:41 +0000 (17:53 +0000)]
Revert 329716 "Add missing nullptr check before getSection() to AArch64MachObjectWriter::recordRelocation"
This broke a bunch of bots so I'm reverting while I figure it out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329728
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Sanjay Patel [Tue, 10 Apr 2018 17:49:45 +0000 (17:49 +0000)]
[llvm-mca] add example workflow for source code
This is copied from Andrea's text in PR36875:
https://bugs.llvm.org/show_bug.cgi?id=36875
As noted there, this is a hack...but it's a good one!
It's important to show potential workflows up-front
with examples, so customers can copy and experiment
with them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329726
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Aaron Smith [Tue, 10 Apr 2018 17:33:18 +0000 (17:33 +0000)]
[DebugInfoPDB] Add DIA implementations of findSymbolByRVA and findSymbolByAddr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329724
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Jessica Paquette [Tue, 10 Apr 2018 17:32:12 +0000 (17:32 +0000)]
Fix test failure in arm64-no-section.ll
There was a missing not line. Also, tail call before ret -> call before ret.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329723
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Krzysztof Parzyszek [Tue, 10 Apr 2018 16:46:13 +0000 (16:46 +0000)]
[CodeGen] Fix printing bundles in MIR output
Delay printing the newline until after the opening bracket was
printed, e.g.
BUNDLE implicit-def $r1, implicit-def $r21, implicit $r1 {
renamable $r1 = S2_asr_i_r renamable $r1, 1
renamable $r21 = A2_tfrsi 0
}
instead of
BUNDLE implicit-def $r1, implicit-def $r21, implicit $r1
{ renamable $r1 = S2_asr_i_r renamable $r1, 1
renamable $r21 = A2_tfrsi 0
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329719
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Peter Collingbourne [Tue, 10 Apr 2018 16:19:30 +0000 (16:19 +0000)]
Revert r329611, "AArch64: Allow offsets to be folded into addresses with ELF."
Caused a build failure in check-tsan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329718
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Jessica Paquette [Tue, 10 Apr 2018 15:53:28 +0000 (15:53 +0000)]
Add missing nullptr check to AArch64MachObjectWriter::recordRelocation
There was missing nullptr check before a call to getSection() in
recordRelocation. This would result in a segfault in code like the attached
test.
This adds the missing check and a test which makes sure we get the expected
error output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329716
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Nicolai Haehnle [Tue, 10 Apr 2018 15:46:43 +0000 (15:46 +0000)]
AMDGPU/MC: Allow disassembling without symbol info
Summary:
We would like the UMR debugging tool[0] to be able to provide
disassembly for currently live waves based on plain memory
dumps, and we want to leverage the LLVM disassembler for this.
This mostly works, except that UMR clearly can't provide real
symbol info, so it wants to set DisInfo == nullptr.
[0] https://cgit.freedesktop.org/amd/umr/
Reviewers: arsenm, rampitec, artem.tamazov, dp
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45477
Change-Id: Ibb2c5af2e66f2e100b4702fd81308e1932bc4ee6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329715
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Aaron Smith [Tue, 10 Apr 2018 15:25:04 +0000 (15:25 +0000)]
[PDB] Remove dead code and run clang format; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329712
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Andrea Di Biagio [Tue, 10 Apr 2018 15:14:15 +0000 (15:14 +0000)]
[llvm-mca] Simplify code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329711
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Chad Rosier [Tue, 10 Apr 2018 14:57:13 +0000 (14:57 +0000)]
Fix spelling. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329709
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Andrea Di Biagio [Tue, 10 Apr 2018 14:55:14 +0000 (14:55 +0000)]
[llvm-mca] Move the logic that prints dispatch unit statistics from BackendStatistics to its own view.
This patch moves the logic that collects and analyzes dispatch events to the
DispatchStatistics view.
Added flag -dispatch-stats to print statistics related to the dispatch logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329708
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Aaron Smith [Tue, 10 Apr 2018 14:47:12 +0000 (14:47 +0000)]
[pdbutil] Print the checksum hex string when using the '-lines' option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329707
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Pavel Labath [Tue, 10 Apr 2018 14:23:41 +0000 (14:23 +0000)]
[CodeGen/Dwarf] Rename the "sizetype" synthetic type and add it to the accelerator table
Summary:
This type is created on-demand and used as the base type for array
ranges. Since it is "special", its construction did not go through the
createTypeDIE function and so it was never inserted into the accelerator
table, although it clearly belongs there.
I add an explicit addAccelType call to insert it into the table.
During review, we also decided to rename the type to something more
unique to avoid confusion in case the user has own "sizetype" type. The
new name for the type size __ARRAY_SIZE_TYPE__.
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329705
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Simon Pilgrim [Tue, 10 Apr 2018 14:21:33 +0000 (14:21 +0000)]
Fix whitespace indentation. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329704
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Pavel Labath [Tue, 10 Apr 2018 14:11:53 +0000 (14:11 +0000)]
[Testing/Support] Make Failed() matcher work with abstract error types
Failed<ErrorInfoBase>() did not compile, because it was attempting to
create a copy of the Error object when passing it to the nested matcher,
which was not possible because ErrorInfoBase is abstract.
This commit fixes the problem by making sure we pass the ErrorInfo
object by reference, which also improves the handling of non-abstract
objects, as we avoid potentially slicing an object during the copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329703
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Gabor Buella [Tue, 10 Apr 2018 13:58:57 +0000 (13:58 +0000)]
[X86] Disable SGX for Skylake Server
Reviewers: craig.topper, zvi, echristo
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D45057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329700
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Andrea Di Biagio [Tue, 10 Apr 2018 12:50:03 +0000 (12:50 +0000)]
[llvm-mca] Increase the default number of iterations to 100.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329694
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David Green [Tue, 10 Apr 2018 11:37:21 +0000 (11:37 +0000)]
[DA] Improve alias checking in dependence analysis
Improve the alias analysis to account for cases where we
know that src/dst pairs cannot alias due to things like
TBAA. As we know they are noalias, we know no dependency
can occur. Also fixes issues around the size parameter
to AA being incorrect.
Differential Revision: https://reviews.llvm.org/D42381
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329692
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Francis Visoiu Mistrih [Tue, 10 Apr 2018 11:29:40 +0000 (11:29 +0000)]
[AArch64] Use FP to access the emergency spill slot
In the presence of variable-sized stack objects, we always picked the
base pointer when resolving frame indices if it was available.
This makes us hit an assert where we can't reach the emergency spill
slot if it's too far away from the base pointer. Since on AArch64 we
decide to place the emergency spill slot at the top of the frame, it
makes more sense to use FP to access it.
The changes here don't affect only emergency spill slots but all the
frame indices. The goal here is to try to choose between FP, BP and SP
so that we minimize the offset and avoid scavenging, or worse, asserting
when trying to access a slot allocated by the scavenger.
Previously discussed here: https://reviews.llvm.org/D40876.
Differential Revision: https://reviews.llvm.org/D45358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329691
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Tim Renouf [Tue, 10 Apr 2018 11:25:15 +0000 (11:25 +0000)]
[AMDGPU] For OS type AMDPAL, fixed scratch on compute shader
Summary:
For OS type AMDPAL, the scratch descriptor is loaded from offset 0 of
the GIT, whose 32 bit pointer is in s0 (s8 for gfx9 merged shaders).
This commit fixes that to use offset 0x10 instead of offset 0 for a
compute shader, per the PAL ABI spec.
V2: Ensure s0 (s8 for gfx9 merged shader) is marked live-in when loading
scratch descriptor from GIT.
Reviewers: kzhuravl, nhaehnle, timcorringham
Subscribers: kzhuravl, wdng, yaxunl, t-tye, llvm-commits, dstuttard, nhaehnle, arsenm
Differential Revision: https://reviews.llvm.org/D44468
Change-Id: I93dffa647758e37f613bb5e0dfca840d82e6d26f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329690
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Tim Northover [Tue, 10 Apr 2018 11:04:29 +0000 (11:04 +0000)]
AArch64: diagnose unpredictable store-exclusive instructions
Much like any written register in load/store instructions, the status register
is not allowed to overlap with any others. So diagnose it like we already do
with the other cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329687
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Andrea Di Biagio [Tue, 10 Apr 2018 10:49:41 +0000 (10:49 +0000)]
[X86][Broadwell] HWPort5 should not be added to BroadwellModelProcResources.
The BroadwellModelProcResources had an entry for HWPort5, which is a Haswell
resource, and not a Broadwell processor resource. That entry was added to the
Broadwell model because variable blends were consuming it.
This was clearly a typo (the resource name should have been BWPort5), which
unfortunately was never caught before. It was not reported as an error because
HWPort5 is a resource defined by the Haswell model. It has been found when
testing some code with llvm-mca: the list of resources in the resource pressure
view was odd.
This patch fixes the issue; now variable blend instructions consume 2 cycles on
BWPort5 instead of HWPort5. This is enough to get rid of the extra (spurious)
entry in the BroadWellModelProcResources table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329686
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Alexandre Ganea [Tue, 10 Apr 2018 10:26:23 +0000 (10:26 +0000)]
[llvm-ar] Temporarily make the tool case detection test Windows-only to fix the build (introduced in r329658)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329683
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Sander de Smalen [Tue, 10 Apr 2018 10:03:13 +0000 (10:03 +0000)]
[AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45371
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329681
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Andrea Di Biagio [Tue, 10 Apr 2018 09:55:33 +0000 (09:55 +0000)]
Reapply "[llvm-mca] Do not separate iterations with a newline in the timeline view."
This reapplies r329403 with a fix for the floating point rounding issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329680
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Clement Courbet [Tue, 10 Apr 2018 08:43:46 +0000 (08:43 +0000)]
[MC][TableGen] Fix r329675.
Caught by bots with -Wmissing-braces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329676
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Clement Courbet [Tue, 10 Apr 2018 08:16:37 +0000 (08:16 +0000)]
[MC][TableGen] Add optional libpfm counter names for ProcResUnits.
Summary:
Subtargets can define the libpfm counter names that can be used to
measure cycles and uops issued on ProcResUnits.
This allows making llvm-exegesis available on more targets.
Fixes PR36984.
Reviewers: gchatelet, RKSimon, andreadb, craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329675
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